PY32f002bxx_pac/rcc/
iopenr.rs

1#[doc = "Register `IOPENR` reader"]
2pub struct R(crate::R<IOPENR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<IOPENR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<IOPENR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<IOPENR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `IOPENR` writer"]
17pub struct W(crate::W<IOPENR_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<IOPENR_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<IOPENR_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<IOPENR_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `GPIOAEN` reader - I/O port A clock enable"]
38pub type GPIOAEN_R = crate::BitReader<bool>;
39#[doc = "Field `GPIOAEN` writer - I/O port A clock enable"]
40pub type GPIOAEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, IOPENR_SPEC, bool, O>;
41#[doc = "Field `GPIOBEN` reader - I/O port B clock enable"]
42pub type GPIOBEN_R = crate::BitReader<bool>;
43#[doc = "Field `GPIOBEN` writer - I/O port B clock enable"]
44pub type GPIOBEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, IOPENR_SPEC, bool, O>;
45#[doc = "Field `GPIOCEN` reader - I/O port C clock enable"]
46pub type GPIOCEN_R = crate::BitReader<bool>;
47#[doc = "Field `GPIOCEN` writer - I/O port C clock enable"]
48pub type GPIOCEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, IOPENR_SPEC, bool, O>;
49impl R {
50    #[doc = "Bit 0 - I/O port A clock enable"]
51    #[inline(always)]
52    pub fn gpioaen(&self) -> GPIOAEN_R {
53        GPIOAEN_R::new((self.bits & 1) != 0)
54    }
55    #[doc = "Bit 1 - I/O port B clock enable"]
56    #[inline(always)]
57    pub fn gpioben(&self) -> GPIOBEN_R {
58        GPIOBEN_R::new(((self.bits >> 1) & 1) != 0)
59    }
60    #[doc = "Bit 2 - I/O port C clock enable"]
61    #[inline(always)]
62    pub fn gpiocen(&self) -> GPIOCEN_R {
63        GPIOCEN_R::new(((self.bits >> 2) & 1) != 0)
64    }
65}
66impl W {
67    #[doc = "Bit 0 - I/O port A clock enable"]
68    #[inline(always)]
69    pub fn gpioaen(&mut self) -> GPIOAEN_W<0> {
70        GPIOAEN_W::new(self)
71    }
72    #[doc = "Bit 1 - I/O port B clock enable"]
73    #[inline(always)]
74    pub fn gpioben(&mut self) -> GPIOBEN_W<1> {
75        GPIOBEN_W::new(self)
76    }
77    #[doc = "Bit 2 - I/O port C clock enable"]
78    #[inline(always)]
79    pub fn gpiocen(&mut self) -> GPIOCEN_W<2> {
80        GPIOCEN_W::new(self)
81    }
82    #[doc = "Writes raw bits to the register."]
83    #[inline(always)]
84    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
85        self.0.bits(bits);
86        self
87    }
88}
89#[doc = "GPIO clock enable register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [iopenr](index.html) module"]
90pub struct IOPENR_SPEC;
91impl crate::RegisterSpec for IOPENR_SPEC {
92    type Ux = u32;
93}
94#[doc = "`read()` method returns [iopenr::R](R) reader structure"]
95impl crate::Readable for IOPENR_SPEC {
96    type Reader = R;
97}
98#[doc = "`write(|w| ..)` method takes [iopenr::W](W) writer structure"]
99impl crate::Writable for IOPENR_SPEC {
100    type Writer = W;
101}
102#[doc = "`reset()` method sets IOPENR to value 0"]
103impl crate::Resettable for IOPENR_SPEC {
104    #[inline(always)]
105    fn reset_value() -> Self::Ux {
106        0
107    }
108}
PY32f002bxx_pac/rcc/iopenr.rs

PY32f002bxx_pac/rcc/
iopenr.rs
