PY32c641xx_pac/
tim14.rs

1#[doc = r"Register block"]
2#[repr(C)]
3pub struct RegisterBlock {
4    #[doc = "0x00 - desc CR1"]
5    pub cr1: CR1,
6    _reserved1: [u8; 0x08],
7    #[doc = "0x0c - desc DIER"]
8    pub dier: DIER,
9    #[doc = "0x10 - desc SR"]
10    pub sr: SR,
11    #[doc = "0x14 - desc EGR"]
12    pub egr: EGR,
13    _reserved_4_ccmr1: [u8; 0x04],
14    _reserved5: [u8; 0x04],
15    #[doc = "0x20 - desc CCER"]
16    pub ccer: CCER,
17    #[doc = "0x24 - desc CNT"]
18    pub cnt: CNT,
19    #[doc = "0x28 - desc PSC"]
20    pub psc: PSC,
21    #[doc = "0x2c - desc ARR"]
22    pub arr: ARR,
23    _reserved9: [u8; 0x04],
24    #[doc = "0x34 - desc CCR1"]
25    pub ccr1: CCR1,
26    _reserved10: [u8; 0x18],
27    #[doc = "0x50 - desc OR"]
28    pub or: OR,
29}
30impl RegisterBlock {
31    #[doc = "0x18 - desc CCMR1:INPUT"]
32    #[inline(always)]
33    pub fn ccmr1_input(&self) -> &CCMR1_INPUT {
34        unsafe { &*(((self as *const Self) as *const u8).add(24usize) as *const CCMR1_INPUT) }
35    }
36    #[doc = "0x18 - desc CCMR1:OUTPUT"]
37    #[inline(always)]
38    pub fn ccmr1_output(&self) -> &CCMR1_OUTPUT {
39        unsafe { &*(((self as *const Self) as *const u8).add(24usize) as *const CCMR1_OUTPUT) }
40    }
41}
42#[doc = "CR1 (rw) register accessor: an alias for `Reg<CR1_SPEC>`"]
43pub type CR1 = crate::Reg<cr1::CR1_SPEC>;
44#[doc = "desc CR1"]
45pub mod cr1;
46#[doc = "DIER (rw) register accessor: an alias for `Reg<DIER_SPEC>`"]
47pub type DIER = crate::Reg<dier::DIER_SPEC>;
48#[doc = "desc DIER"]
49pub mod dier;
50#[doc = "SR (rw) register accessor: an alias for `Reg<SR_SPEC>`"]
51pub type SR = crate::Reg<sr::SR_SPEC>;
52#[doc = "desc SR"]
53pub mod sr;
54#[doc = "EGR (w) register accessor: an alias for `Reg<EGR_SPEC>`"]
55pub type EGR = crate::Reg<egr::EGR_SPEC>;
56#[doc = "desc EGR"]
57pub mod egr;
58#[doc = "CCMR1_OUTPUT (rw) register accessor: an alias for `Reg<CCMR1_OUTPUT_SPEC>`"]
59pub type CCMR1_OUTPUT = crate::Reg<ccmr1_output::CCMR1_OUTPUT_SPEC>;
60#[doc = "desc CCMR1:OUTPUT"]
61pub mod ccmr1_output;
62#[doc = "CCMR1_INPUT (rw) register accessor: an alias for `Reg<CCMR1_INPUT_SPEC>`"]
63pub type CCMR1_INPUT = crate::Reg<ccmr1_input::CCMR1_INPUT_SPEC>;
64#[doc = "desc CCMR1:INPUT"]
65pub mod ccmr1_input;
66#[doc = "CCER (rw) register accessor: an alias for `Reg<CCER_SPEC>`"]
67pub type CCER = crate::Reg<ccer::CCER_SPEC>;
68#[doc = "desc CCER"]
69pub mod ccer;
70#[doc = "CNT (rw) register accessor: an alias for `Reg<CNT_SPEC>`"]
71pub type CNT = crate::Reg<cnt::CNT_SPEC>;
72#[doc = "desc CNT"]
73pub mod cnt;
74#[doc = "PSC (rw) register accessor: an alias for `Reg<PSC_SPEC>`"]
75pub type PSC = crate::Reg<psc::PSC_SPEC>;
76#[doc = "desc PSC"]
77pub mod psc;
78#[doc = "ARR (rw) register accessor: an alias for `Reg<ARR_SPEC>`"]
79pub type ARR = crate::Reg<arr::ARR_SPEC>;
80#[doc = "desc ARR"]
81pub mod arr;
82#[doc = "CCR1 (rw) register accessor: an alias for `Reg<CCR1_SPEC>`"]
83pub type CCR1 = crate::Reg<ccr1::CCR1_SPEC>;
84#[doc = "desc CCR1"]
85pub mod ccr1;
86#[doc = "OR (rw) register accessor: an alias for `Reg<OR_SPEC>`"]
87pub type OR = crate::Reg<or::OR_SPEC>;
88#[doc = "desc OR"]
89pub mod or;
PY32c641xx_pac/tim14.rs

PY32c641xx_pac/
tim14.rs
