#[doc = "Register `CR1` reader"]
pub struct R(crate::R<CR1_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CR1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CR1_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CR1_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CR1` writer"]
pub struct W(crate::W<CR1_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CR1_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CR1_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CR1_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `RWU` reader - Receiver wakeup"]
pub type RWU_R = crate::BitReader<bool>;
#[doc = "Field `RWU` writer - Receiver wakeup"]
pub type RWU_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR1_SPEC, bool, O>;
#[doc = "Field `RE` reader - Receiver enable"]
pub type RE_R = crate::BitReader<bool>;
#[doc = "Field `RE` writer - Receiver enable"]
pub type RE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR1_SPEC, bool, O>;
#[doc = "Field `TE` reader - Transmitter enable"]
pub type TE_R = crate::BitReader<bool>;
#[doc = "Field `TE` writer - Transmitter enable"]
pub type TE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR1_SPEC, bool, O>;
#[doc = "Field `IDLEIE` reader - IDLE interrupt enable"]
pub type IDLEIE_R = crate::BitReader<bool>;
#[doc = "Field `IDLEIE` writer - IDLE interrupt enable"]
pub type IDLEIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR1_SPEC, bool, O>;
#[doc = "Field `RXNEIE` reader - RXNE interrupt enable"]
pub type RXNEIE_R = crate::BitReader<bool>;
#[doc = "Field `RXNEIE` writer - RXNE interrupt enable"]
pub type RXNEIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR1_SPEC, bool, O>;
#[doc = "Field `TCIE` reader - Transmission complete interrupt enable"]
pub type TCIE_R = crate::BitReader<bool>;
#[doc = "Field `TCIE` writer - Transmission complete interrupt enable"]
pub type TCIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR1_SPEC, bool, O>;
#[doc = "Field `TXEIE` reader - TXE interrupt enable"]
pub type TXEIE_R = crate::BitReader<bool>;
#[doc = "Field `TXEIE` writer - TXE interrupt enable"]
pub type TXEIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR1_SPEC, bool, O>;
#[doc = "Field `PEIE` reader - PE interrupt enable"]
pub type PEIE_R = crate::BitReader<bool>;
#[doc = "Field `PEIE` writer - PE interrupt enable"]
pub type PEIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR1_SPEC, bool, O>;
#[doc = "Field `PS` reader - Parity selection"]
pub type PS_R = crate::BitReader<bool>;
#[doc = "Field `PS` writer - Parity selection"]
pub type PS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR1_SPEC, bool, O>;
#[doc = "Field `PCE` reader - Parity control enable"]
pub type PCE_R = crate::BitReader<bool>;
#[doc = "Field `PCE` writer - Parity control enable"]
pub type PCE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR1_SPEC, bool, O>;
#[doc = "Field `WAKE` reader - Wakeup method"]
pub type WAKE_R = crate::BitReader<bool>;
#[doc = "Field `WAKE` writer - Wakeup method"]
pub type WAKE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR1_SPEC, bool, O>;
#[doc = "Field `M` reader - Word length"]
pub type M_R = crate::BitReader<bool>;
#[doc = "Field `M` writer - Word length"]
pub type M_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR1_SPEC, bool, O>;
#[doc = "Field `UE` reader - USART enable"]
pub type UE_R = crate::BitReader<bool>;
#[doc = "Field `UE` writer - USART enable"]
pub type UE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR1_SPEC, bool, O>;
impl R {
#[doc = "Bit 1 - Receiver wakeup"]
#[inline(always)]
pub fn rwu(&self) -> RWU_R {
RWU_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Receiver enable"]
#[inline(always)]
pub fn re(&self) -> RE_R {
RE_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Transmitter enable"]
#[inline(always)]
pub fn te(&self) -> TE_R {
TE_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - IDLE interrupt enable"]
#[inline(always)]
pub fn idleie(&self) -> IDLEIE_R {
IDLEIE_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - RXNE interrupt enable"]
#[inline(always)]
pub fn rxneie(&self) -> RXNEIE_R {
RXNEIE_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Transmission complete interrupt enable"]
#[inline(always)]
pub fn tcie(&self) -> TCIE_R {
TCIE_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - TXE interrupt enable"]
#[inline(always)]
pub fn txeie(&self) -> TXEIE_R {
TXEIE_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - PE interrupt enable"]
#[inline(always)]
pub fn peie(&self) -> PEIE_R {
PEIE_R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - Parity selection"]
#[inline(always)]
pub fn ps(&self) -> PS_R {
PS_R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - Parity control enable"]
#[inline(always)]
pub fn pce(&self) -> PCE_R {
PCE_R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - Wakeup method"]
#[inline(always)]
pub fn wake(&self) -> WAKE_R {
WAKE_R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12 - Word length"]
#[inline(always)]
pub fn m(&self) -> M_R {
M_R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13 - USART enable"]
#[inline(always)]
pub fn ue(&self) -> UE_R {
UE_R::new(((self.bits >> 13) & 1) != 0)
}
}
impl W {
#[doc = "Bit 1 - Receiver wakeup"]
#[inline(always)]
pub fn rwu(&mut self) -> RWU_W<1> {
RWU_W::new(self)
}
#[doc = "Bit 2 - Receiver enable"]
#[inline(always)]
pub fn re(&mut self) -> RE_W<2> {
RE_W::new(self)
}
#[doc = "Bit 3 - Transmitter enable"]
#[inline(always)]
pub fn te(&mut self) -> TE_W<3> {
TE_W::new(self)
}
#[doc = "Bit 4 - IDLE interrupt enable"]
#[inline(always)]
pub fn idleie(&mut self) -> IDLEIE_W<4> {
IDLEIE_W::new(self)
}
#[doc = "Bit 5 - RXNE interrupt enable"]
#[inline(always)]
pub fn rxneie(&mut self) -> RXNEIE_W<5> {
RXNEIE_W::new(self)
}
#[doc = "Bit 6 - Transmission complete interrupt enable"]
#[inline(always)]
pub fn tcie(&mut self) -> TCIE_W<6> {
TCIE_W::new(self)
}
#[doc = "Bit 7 - TXE interrupt enable"]
#[inline(always)]
pub fn txeie(&mut self) -> TXEIE_W<7> {
TXEIE_W::new(self)
}
#[doc = "Bit 8 - PE interrupt enable"]
#[inline(always)]
pub fn peie(&mut self) -> PEIE_W<8> {
PEIE_W::new(self)
}
#[doc = "Bit 9 - Parity selection"]
#[inline(always)]
pub fn ps(&mut self) -> PS_W<9> {
PS_W::new(self)
}
#[doc = "Bit 10 - Parity control enable"]
#[inline(always)]
pub fn pce(&mut self) -> PCE_W<10> {
PCE_W::new(self)
}
#[doc = "Bit 11 - Wakeup method"]
#[inline(always)]
pub fn wake(&mut self) -> WAKE_W<11> {
WAKE_W::new(self)
}
#[doc = "Bit 12 - Word length"]
#[inline(always)]
pub fn m(&mut self) -> M_W<12> {
M_W::new(self)
}
#[doc = "Bit 13 - USART enable"]
#[inline(always)]
pub fn ue(&mut self) -> UE_W<13> {
UE_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Control register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr1](index.html) module"]
pub struct CR1_SPEC;
impl crate::RegisterSpec for CR1_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [cr1::R](R) reader structure"]
impl crate::Readable for CR1_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [cr1::W](W) writer structure"]
impl crate::Writable for CR1_SPEC {
type Writer = W;
}
#[doc = "`reset()` method sets CR1 to value 0"]
impl crate::Resettable for CR1_SPEC {
#[inline(always)]
fn reset_value() -> Self::Ux {
0
}
}