#![doc = "Peripheral access API for ALTARISCV microcontrollers (generated using svd2rust v0.36.1 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.36.1/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"]
#![allow(non_camel_case_types)]
#![allow(non_snake_case)]
#![no_std]
#![cfg_attr(docsrs, feature(doc_auto_cfg))]
#[allow(unused_imports)]
use generic::*;
#[doc = r"Common register and bit access and modify traits"]
pub mod generic {
use core::marker;
#[doc = " Generic peripheral accessor"]
pub struct Periph<RB, const A: usize> {
_marker: marker::PhantomData<RB>,
}
unsafe impl<RB, const A: usize> Send for Periph<RB, A> {}
impl<RB, const A: usize> Periph<RB, A> {
#[doc = "Pointer to the register block"]
pub const PTR: *const RB = A as *const _;
#[doc = "Return the pointer to the register block"]
#[inline(always)]
pub const fn ptr() -> *const RB {
Self::PTR
}
#[doc = " Steal an instance of this peripheral"]
#[doc = ""]
#[doc = " # Safety"]
#[doc = ""]
#[doc = " Ensure that the new instance of the peripheral cannot be used in a way"]
#[doc = " that may race with any existing instances, for example by only"]
#[doc = " accessing read-only or write-only registers, or by consuming the"]
#[doc = " original peripheral and using critical sections to coordinate"]
#[doc = " access between multiple new instances."]
#[doc = ""]
#[doc = " Additionally, other software such as HALs may rely on only one"]
#[doc = " peripheral instance existing to ensure memory safety; ensure"]
#[doc = " no stolen instances are passed to such software."]
pub unsafe fn steal() -> Self {
Self {
_marker: marker::PhantomData,
}
}
}
impl<RB, const A: usize> core::ops::Deref for Periph<RB, A> {
type Target = RB;
#[inline(always)]
fn deref(&self) -> &Self::Target {
unsafe { &*Self::PTR }
}
}
#[doc = " Raw register type (`u8`, `u16`, `u32`, ...)"]
pub trait RawReg:
Copy
+ From<bool>
+ core::ops::BitOr<Output = Self>
+ core::ops::BitAnd<Output = Self>
+ core::ops::BitOrAssign
+ core::ops::BitAndAssign
+ core::ops::Not<Output = Self>
+ core::ops::Shl<u8, Output = Self>
{
#[doc = " Mask for bits of width `WI`"]
fn mask<const WI: u8>() -> Self;
#[doc = " `0`"]
const ZERO: Self;
#[doc = " `1`"]
const ONE: Self;
}
macro_rules! raw_reg {
($ U : ty , $ size : literal , $ mask : ident) => {
impl RawReg for $U {
#[inline(always)]
fn mask<const WI: u8>() -> Self {
$mask::<WI>()
}
const ZERO: Self = 0;
const ONE: Self = 1;
}
const fn $mask<const WI: u8>() -> $U {
<$U>::MAX >> ($size - WI)
}
impl FieldSpec for $U {
type Ux = $U;
}
};
}
raw_reg!(u8, 8, mask_u8);
raw_reg!(u16, 16, mask_u16);
raw_reg!(u32, 32, mask_u32);
raw_reg!(u64, 64, mask_u64);
#[doc = " Raw register type"]
pub trait RegisterSpec {
#[doc = " Raw register type (`u8`, `u16`, `u32`, ...)."]
type Ux: RawReg;
}
#[doc = " Raw field type"]
pub trait FieldSpec: Sized {
#[doc = " Raw field type (`u8`, `u16`, `u32`, ...)."]
type Ux: Copy + core::fmt::Debug + PartialEq + From<Self>;
}
#[doc = " Marker for fields with fixed values"]
pub trait IsEnum: FieldSpec {}
#[doc = " Trait implemented by readable registers to enable the `read` method."]
#[doc = ""]
#[doc = " Registers marked with `Writable` can be also be `modify`'ed."]
pub trait Readable: RegisterSpec {}
#[doc = " Trait implemented by writeable registers."]
#[doc = ""]
#[doc = " This enables the `write`, `write_with_zero` and `reset` methods."]
#[doc = ""]
#[doc = " Registers marked with `Readable` can be also be `modify`'ed."]
pub trait Writable: RegisterSpec {
#[doc = " Is it safe to write any bits to register"]
type Safety;
#[doc = " Specifies the register bits that are not changed if you pass `1` and are changed if you pass `0`"]
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = Self::Ux::ZERO;
#[doc = " Specifies the register bits that are not changed if you pass `0` and are changed if you pass `1`"]
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = Self::Ux::ZERO;
}
#[doc = " Reset value of the register."]
#[doc = ""]
#[doc = " This value is the initial value for the `write` method. It can also be directly written to the"]
#[doc = " register by using the `reset` method."]
pub trait Resettable: RegisterSpec {
#[doc = " Reset value of the register."]
const RESET_VALUE: Self::Ux = Self::Ux::ZERO;
#[doc = " Reset value of the register."]
#[inline(always)]
fn reset_value() -> Self::Ux {
Self::RESET_VALUE
}
}
#[doc(hidden)]
pub mod raw {
use super::{marker, BitM, FieldSpec, RegisterSpec, Unsafe, Writable};
pub struct R<REG: RegisterSpec> {
pub(crate) bits: REG::Ux,
pub(super) _reg: marker::PhantomData<REG>,
}
pub struct W<REG: RegisterSpec> {
#[doc = "Writable bits"]
pub(crate) bits: REG::Ux,
pub(super) _reg: marker::PhantomData<REG>,
}
pub struct FieldReader<FI = u8>
where
FI: FieldSpec,
{
pub(crate) bits: FI::Ux,
_reg: marker::PhantomData<FI>,
}
impl<FI: FieldSpec> FieldReader<FI> {
#[doc = " Creates a new instance of the reader."]
#[allow(unused)]
#[inline(always)]
pub(crate) const fn new(bits: FI::Ux) -> Self {
Self {
bits,
_reg: marker::PhantomData,
}
}
}
pub struct BitReader<FI = bool> {
pub(crate) bits: bool,
_reg: marker::PhantomData<FI>,
}
impl<FI> BitReader<FI> {
#[doc = " Creates a new instance of the reader."]
#[allow(unused)]
#[inline(always)]
pub(crate) const fn new(bits: bool) -> Self {
Self {
bits,
_reg: marker::PhantomData,
}
}
}
#[must_use = "after creating `FieldWriter` you need to call field value setting method"]
pub struct FieldWriter<'a, REG, const WI: u8, FI = u8, Safety = Unsafe>
where
REG: Writable + RegisterSpec,
FI: FieldSpec,
{
pub(crate) w: &'a mut W<REG>,
pub(crate) o: u8,
_field: marker::PhantomData<(FI, Safety)>,
}
impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety>
where
REG: Writable + RegisterSpec,
FI: FieldSpec,
{
#[doc = " Creates a new instance of the writer"]
#[allow(unused)]
#[inline(always)]
pub(crate) fn new(w: &'a mut W<REG>, o: u8) -> Self {
Self {
w,
o,
_field: marker::PhantomData,
}
}
}
#[must_use = "after creating `BitWriter` you need to call bit setting method"]
pub struct BitWriter<'a, REG, FI = bool, M = BitM>
where
REG: Writable + RegisterSpec,
bool: From<FI>,
{
pub(crate) w: &'a mut W<REG>,
pub(crate) o: u8,
_field: marker::PhantomData<(FI, M)>,
}
impl<'a, REG, FI, M> BitWriter<'a, REG, FI, M>
where
REG: Writable + RegisterSpec,
bool: From<FI>,
{
#[doc = " Creates a new instance of the writer"]
#[allow(unused)]
#[inline(always)]
pub(crate) fn new(w: &'a mut W<REG>, o: u8) -> Self {
Self {
w,
o,
_field: marker::PhantomData,
}
}
}
}
#[doc = " Register reader."]
#[doc = ""]
#[doc = " Result of the `read` methods of registers. Also used as a closure argument in the `modify`"]
#[doc = " method."]
pub type R<REG> = raw::R<REG>;
impl<REG: RegisterSpec> R<REG> {
#[doc = " Reads raw bits from register."]
#[inline(always)]
pub const fn bits(&self) -> REG::Ux {
self.bits
}
}
impl<REG: RegisterSpec, FI> PartialEq<FI> for R<REG>
where
REG::Ux: PartialEq,
FI: Copy,
REG::Ux: From<FI>,
{
#[inline(always)]
fn eq(&self, other: &FI) -> bool {
self.bits.eq(®::Ux::from(*other))
}
}
#[doc = " Register writer."]
#[doc = ""]
#[doc = " Used as an argument to the closures in the `write` and `modify` methods of the register."]
pub type W<REG> = raw::W<REG>;
impl<REG: Writable> W<REG> {
#[doc = " Writes raw bits to the register."]
#[doc = ""]
#[doc = " # Safety"]
#[doc = ""]
#[doc = " Passing incorrect value can cause undefined behaviour. See reference manual"]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self {
self.bits = bits;
self
}
}
impl<REG> W<REG>
where
REG: Writable<Safety = Safe>,
{
#[doc = " Writes raw bits to the register."]
#[inline(always)]
pub fn set(&mut self, bits: REG::Ux) -> &mut Self {
self.bits = bits;
self
}
}
#[doc = " Field reader."]
#[doc = ""]
#[doc = " Result of the `read` methods of fields."]
pub type FieldReader<FI = u8> = raw::FieldReader<FI>;
#[doc = " Bit-wise field reader"]
pub type BitReader<FI = bool> = raw::BitReader<FI>;
impl<FI: FieldSpec> FieldReader<FI> {
#[doc = " Reads raw bits from field."]
#[inline(always)]
pub const fn bits(&self) -> FI::Ux {
self.bits
}
}
impl<FI: FieldSpec> core::fmt::Debug for FieldReader<FI> {
fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
core::fmt::Debug::fmt(&self.bits, f)
}
}
impl<FI> PartialEq<FI> for FieldReader<FI>
where
FI: FieldSpec + Copy,
{
#[inline(always)]
fn eq(&self, other: &FI) -> bool {
self.bits.eq(&FI::Ux::from(*other))
}
}
impl<FI> PartialEq<FI> for BitReader<FI>
where
FI: Copy,
bool: From<FI>,
{
#[inline(always)]
fn eq(&self, other: &FI) -> bool {
self.bits.eq(&bool::from(*other))
}
}
impl<FI> BitReader<FI> {
#[doc = " Value of the field as raw bits."]
#[inline(always)]
pub const fn bit(&self) -> bool {
self.bits
}
#[doc = " Returns `true` if the bit is clear (0)."]
#[inline(always)]
pub const fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = " Returns `true` if the bit is set (1)."]
#[inline(always)]
pub const fn bit_is_set(&self) -> bool {
self.bit()
}
}
impl<FI> core::fmt::Debug for BitReader<FI> {
fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
core::fmt::Debug::fmt(&self.bits, f)
}
}
#[doc = " Marker for register/field writers which can take any value of specified width"]
pub struct Safe;
#[doc = " You should check that value is allowed to pass to register/field writer marked with this"]
pub struct Unsafe;
#[doc = " Marker for field writers are safe to write in specified inclusive range"]
pub struct Range<const MIN: u64, const MAX: u64>;
#[doc = " Marker for field writers are safe to write in specified inclusive range"]
pub struct RangeFrom<const MIN: u64>;
#[doc = " Marker for field writers are safe to write in specified inclusive range"]
pub struct RangeTo<const MAX: u64>;
#[doc = " Write field Proxy"]
pub type FieldWriter<'a, REG, const WI: u8, FI = u8, Safety = Unsafe> =
raw::FieldWriter<'a, REG, WI, FI, Safety>;
impl<REG, const WI: u8, FI, Safety> FieldWriter<'_, REG, WI, FI, Safety>
where
REG: Writable + RegisterSpec,
FI: FieldSpec,
{
#[doc = " Field width"]
pub const WIDTH: u8 = WI;
#[doc = " Field width"]
#[inline(always)]
pub const fn width(&self) -> u8 {
WI
}
#[doc = " Field offset"]
#[inline(always)]
pub const fn offset(&self) -> u8 {
self.o
}
}
impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety>
where
REG: Writable + RegisterSpec,
FI: FieldSpec,
REG::Ux: From<FI::Ux>,
{
#[doc = " Writes raw bits to the field"]
#[doc = ""]
#[doc = " # Safety"]
#[doc = ""]
#[doc = " Passing incorrect value can cause undefined behaviour. See reference manual"]
#[inline(always)]
pub unsafe fn bits(self, value: FI::Ux) -> &'a mut W<REG> {
self.w.bits &= !(REG::Ux::mask::<WI>() << self.o);
self.w.bits |= (REG::Ux::from(value) & REG::Ux::mask::<WI>()) << self.o;
self.w
}
}
impl<'a, REG, const WI: u8, FI> FieldWriter<'a, REG, WI, FI, Safe>
where
REG: Writable + RegisterSpec,
FI: FieldSpec,
REG::Ux: From<FI::Ux>,
{
#[doc = " Writes raw bits to the field"]
#[inline(always)]
pub fn set(self, value: FI::Ux) -> &'a mut W<REG> {
unsafe { self.bits(value) }
}
}
impl<'a, REG, const WI: u8, FI, const MIN: u64, const MAX: u64>
FieldWriter<'a, REG, WI, FI, Range<MIN, MAX>>
where
REG: Writable + RegisterSpec,
FI: FieldSpec,
REG::Ux: From<FI::Ux>,
u64: From<FI::Ux>,
{
#[doc = " Writes raw bits to the field"]
#[inline(always)]
pub fn set(self, value: FI::Ux) -> &'a mut W<REG> {
{
let value = u64::from(value);
assert!(value >= MIN && value <= MAX);
}
unsafe { self.bits(value) }
}
}
impl<'a, REG, const WI: u8, FI, const MIN: u64> FieldWriter<'a, REG, WI, FI, RangeFrom<MIN>>
where
REG: Writable + RegisterSpec,
FI: FieldSpec,
REG::Ux: From<FI::Ux>,
u64: From<FI::Ux>,
{
#[doc = " Writes raw bits to the field"]
#[inline(always)]
pub fn set(self, value: FI::Ux) -> &'a mut W<REG> {
{
let value = u64::from(value);
assert!(value >= MIN);
}
unsafe { self.bits(value) }
}
}
impl<'a, REG, const WI: u8, FI, const MAX: u64> FieldWriter<'a, REG, WI, FI, RangeTo<MAX>>
where
REG: Writable + RegisterSpec,
FI: FieldSpec,
REG::Ux: From<FI::Ux>,
u64: From<FI::Ux>,
{
#[doc = " Writes raw bits to the field"]
#[inline(always)]
pub fn set(self, value: FI::Ux) -> &'a mut W<REG> {
{
let value = u64::from(value);
assert!(value <= MAX);
}
unsafe { self.bits(value) }
}
}
impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety>
where
REG: Writable + RegisterSpec,
FI: IsEnum,
REG::Ux: From<FI::Ux>,
{
#[doc = " Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: FI) -> &'a mut W<REG> {
unsafe { self.bits(FI::Ux::from(variant)) }
}
}
macro_rules! bit_proxy {
($ writer : ident , $ mwv : ident) => {
#[doc(hidden)]
pub struct $mwv;
#[doc = " Bit-wise write field proxy"]
pub type $writer<'a, REG, FI = bool> = raw::BitWriter<'a, REG, FI, $mwv>;
impl<'a, REG, FI> $writer<'a, REG, FI>
where
REG: Writable + RegisterSpec,
bool: From<FI>,
{
#[doc = " Field width"]
pub const WIDTH: u8 = 1;
#[doc = " Field width"]
#[inline(always)]
pub const fn width(&self) -> u8 {
Self::WIDTH
}
#[doc = " Field offset"]
#[inline(always)]
pub const fn offset(&self) -> u8 {
self.o
}
#[doc = " Writes bit to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W<REG> {
self.w.bits &= !(REG::Ux::ONE << self.o);
self.w.bits |= (REG::Ux::from(value) & REG::Ux::ONE) << self.o;
self.w
}
#[doc = " Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: FI) -> &'a mut W<REG> {
self.bit(bool::from(variant))
}
}
};
}
bit_proxy!(BitWriter, BitM);
bit_proxy!(BitWriter1S, Bit1S);
bit_proxy!(BitWriter0C, Bit0C);
bit_proxy!(BitWriter1C, Bit1C);
bit_proxy!(BitWriter0S, Bit0S);
bit_proxy!(BitWriter1T, Bit1T);
bit_proxy!(BitWriter0T, Bit0T);
impl<'a, REG, FI> BitWriter<'a, REG, FI>
where
REG: Writable + RegisterSpec,
bool: From<FI>,
{
#[doc = " Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W<REG> {
self.w.bits |= REG::Ux::ONE << self.o;
self.w
}
#[doc = " Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W<REG> {
self.w.bits &= !(REG::Ux::ONE << self.o);
self.w
}
}
impl<'a, REG, FI> BitWriter1S<'a, REG, FI>
where
REG: Writable + RegisterSpec,
bool: From<FI>,
{
#[doc = " Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W<REG> {
self.w.bits |= REG::Ux::ONE << self.o;
self.w
}
}
impl<'a, REG, FI> BitWriter0C<'a, REG, FI>
where
REG: Writable + RegisterSpec,
bool: From<FI>,
{
#[doc = " Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W<REG> {
self.w.bits &= !(REG::Ux::ONE << self.o);
self.w
}
}
impl<'a, REG, FI> BitWriter1C<'a, REG, FI>
where
REG: Writable + RegisterSpec,
bool: From<FI>,
{
#[doc = "Clears the field bit by passing one"]
#[inline(always)]
pub fn clear_bit_by_one(self) -> &'a mut W<REG> {
self.w.bits |= REG::Ux::ONE << self.o;
self.w
}
}
impl<'a, REG, FI> BitWriter0S<'a, REG, FI>
where
REG: Writable + RegisterSpec,
bool: From<FI>,
{
#[doc = "Sets the field bit by passing zero"]
#[inline(always)]
pub fn set_bit_by_zero(self) -> &'a mut W<REG> {
self.w.bits &= !(REG::Ux::ONE << self.o);
self.w
}
}
impl<'a, REG, FI> BitWriter1T<'a, REG, FI>
where
REG: Writable + RegisterSpec,
bool: From<FI>,
{
#[doc = "Toggle the field bit by passing one"]
#[inline(always)]
pub fn toggle_bit(self) -> &'a mut W<REG> {
self.w.bits |= REG::Ux::ONE << self.o;
self.w
}
}
impl<'a, REG, FI> BitWriter0T<'a, REG, FI>
where
REG: Writable + RegisterSpec,
bool: From<FI>,
{
#[doc = "Toggle the field bit by passing zero"]
#[inline(always)]
pub fn toggle_bit(self) -> &'a mut W<REG> {
self.w.bits &= !(REG::Ux::ONE << self.o);
self.w
}
}
#[doc = " This structure provides volatile access to registers."]
#[repr(transparent)]
pub struct Reg<REG: RegisterSpec> {
register: vcell::VolatileCell<REG::Ux>,
_marker: marker::PhantomData<REG>,
}
unsafe impl<REG: RegisterSpec> Send for Reg<REG> where REG::Ux: Send {}
impl<REG: RegisterSpec> Reg<REG> {
#[doc = " Returns the underlying memory address of register."]
#[doc = ""]
#[doc = " ```ignore"]
#[doc = " let reg_ptr = periph.reg.as_ptr();"]
#[doc = " ```"]
#[inline(always)]
pub fn as_ptr(&self) -> *mut REG::Ux {
self.register.as_ptr()
}
}
impl<REG: Readable> Reg<REG> {
#[doc = " Reads the contents of a `Readable` register."]
#[doc = ""]
#[doc = " You can read the raw contents of a register by using `bits`:"]
#[doc = " ```ignore"]
#[doc = " let bits = periph.reg.read().bits();"]
#[doc = " ```"]
#[doc = " or get the content of a particular field of a register:"]
#[doc = " ```ignore"]
#[doc = " let reader = periph.reg.read();"]
#[doc = " let bits = reader.field1().bits();"]
#[doc = " let flag = reader.field2().bit_is_set();"]
#[doc = " ```"]
#[inline(always)]
pub fn read(&self) -> R<REG> {
R {
bits: self.register.get(),
_reg: marker::PhantomData,
}
}
}
impl<REG: Resettable + Writable> Reg<REG> {
#[doc = " Writes the reset value to `Writable` register."]
#[doc = ""]
#[doc = " Resets the register to its initial state."]
#[inline(always)]
pub fn reset(&self) {
self.register.set(REG::RESET_VALUE)
}
#[doc = " Writes bits to a `Writable` register."]
#[doc = ""]
#[doc = " You can write raw bits into a register:"]
#[doc = " ```ignore"]
#[doc = " periph.reg.write(|w| unsafe { w.bits(rawbits) });"]
#[doc = " ```"]
#[doc = " or write only the fields you need:"]
#[doc = " ```ignore"]
#[doc = " periph.reg.write(|w| w"]
#[doc = " .field1().bits(newfield1bits)"]
#[doc = " .field2().set_bit()"]
#[doc = " .field3().variant(VARIANT)"]
#[doc = " );"]
#[doc = " ```"]
#[doc = " or an alternative way of saying the same:"]
#[doc = " ```ignore"]
#[doc = " periph.reg.write(|w| {"]
#[doc = " w.field1().bits(newfield1bits);"]
#[doc = " w.field2().set_bit();"]
#[doc = " w.field3().variant(VARIANT)"]
#[doc = " });"]
#[doc = " ```"]
#[doc = " In the latter case, other fields will be set to their reset value."]
#[inline(always)]
pub fn write<F>(&self, f: F) -> REG::Ux
where
F: FnOnce(&mut W<REG>) -> &mut W<REG>,
{
let value = f(&mut W {
bits: REG::RESET_VALUE & !REG::ONE_TO_MODIFY_FIELDS_BITMAP
| REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
_reg: marker::PhantomData,
})
.bits;
self.register.set(value);
value
}
#[doc = " Writes bits to a `Writable` register and produce a value."]
#[doc = ""]
#[doc = " You can write raw bits into a register:"]
#[doc = " ```ignore"]
#[doc = " periph.reg.write_and(|w| unsafe { w.bits(rawbits); });"]
#[doc = " ```"]
#[doc = " or write only the fields you need:"]
#[doc = " ```ignore"]
#[doc = " periph.reg.write_and(|w| {"]
#[doc = " w.field1().bits(newfield1bits)"]
#[doc = " .field2().set_bit()"]
#[doc = " .field3().variant(VARIANT);"]
#[doc = " });"]
#[doc = " ```"]
#[doc = " or an alternative way of saying the same:"]
#[doc = " ```ignore"]
#[doc = " periph.reg.write_and(|w| {"]
#[doc = " w.field1().bits(newfield1bits);"]
#[doc = " w.field2().set_bit();"]
#[doc = " w.field3().variant(VARIANT);"]
#[doc = " });"]
#[doc = " ```"]
#[doc = " In the latter case, other fields will be set to their reset value."]
#[doc = ""]
#[doc = " Values can be returned from the closure:"]
#[doc = " ```ignore"]
#[doc = " let state = periph.reg.write_and(|w| State::set(w.field1()));"]
#[doc = " ```"]
#[inline(always)]
pub fn from_write<F, T>(&self, f: F) -> T
where
F: FnOnce(&mut W<REG>) -> T,
{
let mut writer = W {
bits: REG::RESET_VALUE & !REG::ONE_TO_MODIFY_FIELDS_BITMAP
| REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
_reg: marker::PhantomData,
};
let result = f(&mut writer);
self.register.set(writer.bits);
result
}
}
impl<REG: Writable> Reg<REG> {
#[doc = " Writes 0 to a `Writable` register."]
#[doc = ""]
#[doc = " Similar to `write`, but unused bits will contain 0."]
#[doc = ""]
#[doc = " # Safety"]
#[doc = ""]
#[doc = " Unsafe to use with registers which don't allow to write 0."]
#[inline(always)]
pub unsafe fn write_with_zero<F>(&self, f: F) -> REG::Ux
where
F: FnOnce(&mut W<REG>) -> &mut W<REG>,
{
let value = f(&mut W {
bits: REG::Ux::ZERO,
_reg: marker::PhantomData,
})
.bits;
self.register.set(value);
value
}
#[doc = " Writes 0 to a `Writable` register and produces a value."]
#[doc = ""]
#[doc = " Similar to `write`, but unused bits will contain 0."]
#[doc = ""]
#[doc = " # Safety"]
#[doc = ""]
#[doc = " Unsafe to use with registers which don't allow to write 0."]
#[inline(always)]
pub unsafe fn from_write_with_zero<F, T>(&self, f: F) -> T
where
F: FnOnce(&mut W<REG>) -> T,
{
let mut writer = W {
bits: REG::Ux::ZERO,
_reg: marker::PhantomData,
};
let result = f(&mut writer);
self.register.set(writer.bits);
result
}
}
impl<REG: Readable + Writable> Reg<REG> {
#[doc = " Modifies the contents of the register by reading and then writing it."]
#[doc = ""]
#[doc = " E.g. to do a read-modify-write sequence to change parts of a register:"]
#[doc = " ```ignore"]
#[doc = " periph.reg.modify(|r, w| unsafe { w.bits("]
#[doc = " r.bits() | 3"]
#[doc = " ) });"]
#[doc = " ```"]
#[doc = " or"]
#[doc = " ```ignore"]
#[doc = " periph.reg.modify(|_, w| w"]
#[doc = " .field1().bits(newfield1bits)"]
#[doc = " .field2().set_bit()"]
#[doc = " .field3().variant(VARIANT)"]
#[doc = " );"]
#[doc = " ```"]
#[doc = " or an alternative way of saying the same:"]
#[doc = " ```ignore"]
#[doc = " periph.reg.modify(|_, w| {"]
#[doc = " w.field1().bits(newfield1bits);"]
#[doc = " w.field2().set_bit();"]
#[doc = " w.field3().variant(VARIANT)"]
#[doc = " });"]
#[doc = " ```"]
#[doc = " Other fields will have the value they had before the call to `modify`."]
#[inline(always)]
pub fn modify<F>(&self, f: F) -> REG::Ux
where
for<'w> F: FnOnce(&R<REG>, &'w mut W<REG>) -> &'w mut W<REG>,
{
let bits = self.register.get();
let value = f(
&R {
bits,
_reg: marker::PhantomData,
},
&mut W {
bits: bits & !REG::ONE_TO_MODIFY_FIELDS_BITMAP
| REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
_reg: marker::PhantomData,
},
)
.bits;
self.register.set(value);
value
}
#[doc = " Modifies the contents of the register by reading and then writing it"]
#[doc = " and produces a value."]
#[doc = ""]
#[doc = " E.g. to do a read-modify-write sequence to change parts of a register:"]
#[doc = " ```ignore"]
#[doc = " let bits = periph.reg.modify(|r, w| {"]
#[doc = " let new_bits = r.bits() | 3;"]
#[doc = " unsafe {"]
#[doc = " w.bits(new_bits);"]
#[doc = " }"]
#[doc = ""]
#[doc = " new_bits"]
#[doc = " });"]
#[doc = " ```"]
#[doc = " or"]
#[doc = " ```ignore"]
#[doc = " periph.reg.modify(|_, w| {"]
#[doc = " w.field1().bits(newfield1bits)"]
#[doc = " .field2().set_bit()"]
#[doc = " .field3().variant(VARIANT);"]
#[doc = " });"]
#[doc = " ```"]
#[doc = " or an alternative way of saying the same:"]
#[doc = " ```ignore"]
#[doc = " periph.reg.modify(|_, w| {"]
#[doc = " w.field1().bits(newfield1bits);"]
#[doc = " w.field2().set_bit();"]
#[doc = " w.field3().variant(VARIANT);"]
#[doc = " });"]
#[doc = " ```"]
#[doc = " Other fields will have the value they had before the call to `modify`."]
#[inline(always)]
pub fn from_modify<F, T>(&self, f: F) -> T
where
for<'w> F: FnOnce(&R<REG>, &'w mut W<REG>) -> T,
{
let bits = self.register.get();
let mut writer = W {
bits: bits & !REG::ONE_TO_MODIFY_FIELDS_BITMAP | REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
_reg: marker::PhantomData,
};
let result = f(
&R {
bits,
_reg: marker::PhantomData,
},
&mut writer,
);
self.register.set(writer.bits);
result
}
}
impl<REG: Readable> core::fmt::Debug for crate::generic::Reg<REG>
where
R<REG>: core::fmt::Debug,
{
fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
core::fmt::Debug::fmt(&self.read(), f)
}
}
}
#[cfg(feature = "rt")]
extern "C" {}
#[doc(hidden)]
#[repr(C)]
pub union Vector {
pub _handler: unsafe extern "C" fn(),
pub _reserved: usize,
}
#[cfg(feature = "rt")]
#[doc(hidden)]
#[no_mangle]
pub static __EXTERNAL_INTERRUPTS: [Vector; 0] = [];
#[doc = "Core local interrupt controller"]
pub type Clint = crate::Periph<clint::RegisterBlock, 0x0200_0000>;
impl core::fmt::Debug for Clint {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Clint").finish()
}
}
#[doc = "Core local interrupt controller"]
pub mod clint {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
msip: Msip,
_reserved1: [u8; 0x3ffc],
mtimecmp_0_0: Mtimecmp0_0,
mtimecmp_0_4: Mtimecmp0_4,
_reserved3: [u8; 0x7ff0],
mtime_0: Mtime0,
mtime_4: Mtime4,
}
impl RegisterBlock {
#[doc = "0x00 - MSIP Bits"]
#[inline(always)]
pub const fn msip(&self) -> &Msip {
&self.msip
}
#[doc = "0x4000 - MTIMECMP for hart 0"]
#[inline(always)]
pub const fn mtimecmp_0_0(&self) -> &Mtimecmp0_0 {
&self.mtimecmp_0_0
}
#[doc = "0x4004 - MTIMECMP for hart 0"]
#[inline(always)]
pub const fn mtimecmp_0_4(&self) -> &Mtimecmp0_4 {
&self.mtimecmp_0_4
}
#[doc = "0xbff8 - Timer Register"]
#[inline(always)]
pub const fn mtime_0(&self) -> &Mtime0 {
&self.mtime_0
}
#[doc = "0xbffc - Timer Register"]
#[inline(always)]
pub const fn mtime_4(&self) -> &Mtime4 {
&self.mtime_4
}
}
#[doc = "msip (rw) register accessor: MSIP Bits\n\nYou can [`read`](crate::Reg::read) this register and get [`msip::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`msip::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@msip`] module"]
#[doc(alias = "msip")]
pub type Msip = crate::Reg<msip::MsipSpec>;
#[doc = "MSIP Bits"]
pub mod msip {
#[doc = "Register `msip` reader"]
pub type R = crate::R<MsipSpec>;
#[doc = "Register `msip` writer"]
pub type W = crate::W<MsipSpec>;
#[doc = "Field `msip_0` reader - MSIP bit for Hart 0"]
pub type Msip0R = crate::BitReader;
#[doc = "Field `msip_0` writer - MSIP bit for Hart 0"]
pub type Msip0W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - MSIP bit for Hart 0"]
#[inline(always)]
pub fn msip_0(&self) -> Msip0R {
Msip0R::new((self.bits & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - MSIP bit for Hart 0"]
#[inline(always)]
pub fn msip_0(&mut self) -> Msip0W<MsipSpec> {
Msip0W::new(self, 0)
}
}
#[doc = "MSIP Bits\n\nYou can [`read`](crate::Reg::read) this register and get [`msip::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`msip::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MsipSpec;
impl crate::RegisterSpec for MsipSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`msip::R`](R) reader structure"]
impl crate::Readable for MsipSpec {}
#[doc = "`write(|w| ..)` method takes [`msip::W`](W) writer structure"]
impl crate::Writable for MsipSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets msip to value 0"]
impl crate::Resettable for MsipSpec {}
}
#[doc = "mtimecmp_0_0 (rw) register accessor: MTIMECMP for hart 0\n\nYou can [`read`](crate::Reg::read) this register and get [`mtimecmp_0_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mtimecmp_0_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mtimecmp_0_0`] module"]
#[doc(alias = "mtimecmp_0_0")]
pub type Mtimecmp0_0 = crate::Reg<mtimecmp_0_0::Mtimecmp0_0Spec>;
#[doc = "MTIMECMP for hart 0"]
pub mod mtimecmp_0_0 {
#[doc = "Register `mtimecmp_0_0` reader"]
pub type R = crate::R<Mtimecmp0_0Spec>;
#[doc = "Register `mtimecmp_0_0` writer"]
pub type W = crate::W<Mtimecmp0_0Spec>;
#[doc = "Field `mtimecmp_0_0` reader - mtimecmp_0_0"]
pub type Mtimecmp0_0R = crate::FieldReader;
#[doc = "Field `mtimecmp_0_0` writer - mtimecmp_0_0"]
pub type Mtimecmp0_0W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `mtimecmp_0_1` reader - mtimecmp_0_1"]
pub type Mtimecmp0_1R = crate::FieldReader;
#[doc = "Field `mtimecmp_0_1` writer - mtimecmp_0_1"]
pub type Mtimecmp0_1W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `mtimecmp_0_2` reader - mtimecmp_0_2"]
pub type Mtimecmp0_2R = crate::FieldReader;
#[doc = "Field `mtimecmp_0_2` writer - mtimecmp_0_2"]
pub type Mtimecmp0_2W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `mtimecmp_0_3` reader - mtimecmp_0_3"]
pub type Mtimecmp0_3R = crate::FieldReader;
#[doc = "Field `mtimecmp_0_3` writer - mtimecmp_0_3"]
pub type Mtimecmp0_3W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:7 - mtimecmp_0_0"]
#[inline(always)]
pub fn mtimecmp_0_0(&self) -> Mtimecmp0_0R {
Mtimecmp0_0R::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:15 - mtimecmp_0_1"]
#[inline(always)]
pub fn mtimecmp_0_1(&self) -> Mtimecmp0_1R {
Mtimecmp0_1R::new(((self.bits >> 8) & 0xff) as u8)
}
#[doc = "Bits 16:23 - mtimecmp_0_2"]
#[inline(always)]
pub fn mtimecmp_0_2(&self) -> Mtimecmp0_2R {
Mtimecmp0_2R::new(((self.bits >> 16) & 0xff) as u8)
}
#[doc = "Bits 24:31 - mtimecmp_0_3"]
#[inline(always)]
pub fn mtimecmp_0_3(&self) -> Mtimecmp0_3R {
Mtimecmp0_3R::new(((self.bits >> 24) & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:7 - mtimecmp_0_0"]
#[inline(always)]
pub fn mtimecmp_0_0(&mut self) -> Mtimecmp0_0W<Mtimecmp0_0Spec> {
Mtimecmp0_0W::new(self, 0)
}
#[doc = "Bits 8:15 - mtimecmp_0_1"]
#[inline(always)]
pub fn mtimecmp_0_1(&mut self) -> Mtimecmp0_1W<Mtimecmp0_0Spec> {
Mtimecmp0_1W::new(self, 8)
}
#[doc = "Bits 16:23 - mtimecmp_0_2"]
#[inline(always)]
pub fn mtimecmp_0_2(&mut self) -> Mtimecmp0_2W<Mtimecmp0_0Spec> {
Mtimecmp0_2W::new(self, 16)
}
#[doc = "Bits 24:31 - mtimecmp_0_3"]
#[inline(always)]
pub fn mtimecmp_0_3(&mut self) -> Mtimecmp0_3W<Mtimecmp0_0Spec> {
Mtimecmp0_3W::new(self, 24)
}
}
#[doc = "MTIMECMP for hart 0\n\nYou can [`read`](crate::Reg::read) this register and get [`mtimecmp_0_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mtimecmp_0_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Mtimecmp0_0Spec;
impl crate::RegisterSpec for Mtimecmp0_0Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`mtimecmp_0_0::R`](R) reader structure"]
impl crate::Readable for Mtimecmp0_0Spec {}
#[doc = "`write(|w| ..)` method takes [`mtimecmp_0_0::W`](W) writer structure"]
impl crate::Writable for Mtimecmp0_0Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets mtimecmp_0_0 to value 0"]
impl crate::Resettable for Mtimecmp0_0Spec {}
}
#[doc = "mtimecmp_0_4 (rw) register accessor: MTIMECMP for hart 0\n\nYou can [`read`](crate::Reg::read) this register and get [`mtimecmp_0_4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mtimecmp_0_4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mtimecmp_0_4`] module"]
#[doc(alias = "mtimecmp_0_4")]
pub type Mtimecmp0_4 = crate::Reg<mtimecmp_0_4::Mtimecmp0_4Spec>;
#[doc = "MTIMECMP for hart 0"]
pub mod mtimecmp_0_4 {
#[doc = "Register `mtimecmp_0_4` reader"]
pub type R = crate::R<Mtimecmp0_4Spec>;
#[doc = "Register `mtimecmp_0_4` writer"]
pub type W = crate::W<Mtimecmp0_4Spec>;
#[doc = "Field `mtimecmp_0_4` reader - mtimecmp_0_4"]
pub type Mtimecmp0_4R = crate::FieldReader;
#[doc = "Field `mtimecmp_0_4` writer - mtimecmp_0_4"]
pub type Mtimecmp0_4W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `mtimecmp_0_5` reader - mtimecmp_0_5"]
pub type Mtimecmp0_5R = crate::FieldReader;
#[doc = "Field `mtimecmp_0_5` writer - mtimecmp_0_5"]
pub type Mtimecmp0_5W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `mtimecmp_0_6` reader - mtimecmp_0_6"]
pub type Mtimecmp0_6R = crate::FieldReader;
#[doc = "Field `mtimecmp_0_6` writer - mtimecmp_0_6"]
pub type Mtimecmp0_6W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `mtimecmp_0_7` reader - mtimecmp_0_7"]
pub type Mtimecmp0_7R = crate::FieldReader;
#[doc = "Field `mtimecmp_0_7` writer - mtimecmp_0_7"]
pub type Mtimecmp0_7W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:7 - mtimecmp_0_4"]
#[inline(always)]
pub fn mtimecmp_0_4(&self) -> Mtimecmp0_4R {
Mtimecmp0_4R::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:15 - mtimecmp_0_5"]
#[inline(always)]
pub fn mtimecmp_0_5(&self) -> Mtimecmp0_5R {
Mtimecmp0_5R::new(((self.bits >> 8) & 0xff) as u8)
}
#[doc = "Bits 16:23 - mtimecmp_0_6"]
#[inline(always)]
pub fn mtimecmp_0_6(&self) -> Mtimecmp0_6R {
Mtimecmp0_6R::new(((self.bits >> 16) & 0xff) as u8)
}
#[doc = "Bits 24:31 - mtimecmp_0_7"]
#[inline(always)]
pub fn mtimecmp_0_7(&self) -> Mtimecmp0_7R {
Mtimecmp0_7R::new(((self.bits >> 24) & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:7 - mtimecmp_0_4"]
#[inline(always)]
pub fn mtimecmp_0_4(&mut self) -> Mtimecmp0_4W<Mtimecmp0_4Spec> {
Mtimecmp0_4W::new(self, 0)
}
#[doc = "Bits 8:15 - mtimecmp_0_5"]
#[inline(always)]
pub fn mtimecmp_0_5(&mut self) -> Mtimecmp0_5W<Mtimecmp0_4Spec> {
Mtimecmp0_5W::new(self, 8)
}
#[doc = "Bits 16:23 - mtimecmp_0_6"]
#[inline(always)]
pub fn mtimecmp_0_6(&mut self) -> Mtimecmp0_6W<Mtimecmp0_4Spec> {
Mtimecmp0_6W::new(self, 16)
}
#[doc = "Bits 24:31 - mtimecmp_0_7"]
#[inline(always)]
pub fn mtimecmp_0_7(&mut self) -> Mtimecmp0_7W<Mtimecmp0_4Spec> {
Mtimecmp0_7W::new(self, 24)
}
}
#[doc = "MTIMECMP for hart 0\n\nYou can [`read`](crate::Reg::read) this register and get [`mtimecmp_0_4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mtimecmp_0_4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Mtimecmp0_4Spec;
impl crate::RegisterSpec for Mtimecmp0_4Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`mtimecmp_0_4::R`](R) reader structure"]
impl crate::Readable for Mtimecmp0_4Spec {}
#[doc = "`write(|w| ..)` method takes [`mtimecmp_0_4::W`](W) writer structure"]
impl crate::Writable for Mtimecmp0_4Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets mtimecmp_0_4 to value 0"]
impl crate::Resettable for Mtimecmp0_4Spec {}
}
#[doc = "mtime_0 (rw) register accessor: Timer Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mtime_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mtime_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mtime_0`] module"]
#[doc(alias = "mtime_0")]
pub type Mtime0 = crate::Reg<mtime_0::Mtime0Spec>;
#[doc = "Timer Register"]
pub mod mtime_0 {
#[doc = "Register `mtime_0` reader"]
pub type R = crate::R<Mtime0Spec>;
#[doc = "Register `mtime_0` writer"]
pub type W = crate::W<Mtime0Spec>;
#[doc = "Field `mtime_0` reader - mtime_0"]
pub type Mtime0R = crate::FieldReader;
#[doc = "Field `mtime_0` writer - mtime_0"]
pub type Mtime0W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `mtime_1` reader - mtime_1"]
pub type Mtime1R = crate::FieldReader;
#[doc = "Field `mtime_1` writer - mtime_1"]
pub type Mtime1W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `mtime_2` reader - mtime_2"]
pub type Mtime2R = crate::FieldReader;
#[doc = "Field `mtime_2` writer - mtime_2"]
pub type Mtime2W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `mtime_3` reader - mtime_3"]
pub type Mtime3R = crate::FieldReader;
#[doc = "Field `mtime_3` writer - mtime_3"]
pub type Mtime3W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:7 - mtime_0"]
#[inline(always)]
pub fn mtime_0(&self) -> Mtime0R {
Mtime0R::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:15 - mtime_1"]
#[inline(always)]
pub fn mtime_1(&self) -> Mtime1R {
Mtime1R::new(((self.bits >> 8) & 0xff) as u8)
}
#[doc = "Bits 16:23 - mtime_2"]
#[inline(always)]
pub fn mtime_2(&self) -> Mtime2R {
Mtime2R::new(((self.bits >> 16) & 0xff) as u8)
}
#[doc = "Bits 24:31 - mtime_3"]
#[inline(always)]
pub fn mtime_3(&self) -> Mtime3R {
Mtime3R::new(((self.bits >> 24) & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:7 - mtime_0"]
#[inline(always)]
pub fn mtime_0(&mut self) -> Mtime0W<Mtime0Spec> {
Mtime0W::new(self, 0)
}
#[doc = "Bits 8:15 - mtime_1"]
#[inline(always)]
pub fn mtime_1(&mut self) -> Mtime1W<Mtime0Spec> {
Mtime1W::new(self, 8)
}
#[doc = "Bits 16:23 - mtime_2"]
#[inline(always)]
pub fn mtime_2(&mut self) -> Mtime2W<Mtime0Spec> {
Mtime2W::new(self, 16)
}
#[doc = "Bits 24:31 - mtime_3"]
#[inline(always)]
pub fn mtime_3(&mut self) -> Mtime3W<Mtime0Spec> {
Mtime3W::new(self, 24)
}
}
#[doc = "Timer Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mtime_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mtime_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Mtime0Spec;
impl crate::RegisterSpec for Mtime0Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`mtime_0::R`](R) reader structure"]
impl crate::Readable for Mtime0Spec {}
#[doc = "`write(|w| ..)` method takes [`mtime_0::W`](W) writer structure"]
impl crate::Writable for Mtime0Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets mtime_0 to value 0"]
impl crate::Resettable for Mtime0Spec {}
}
#[doc = "mtime_4 (rw) register accessor: Timer Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mtime_4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mtime_4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mtime_4`] module"]
#[doc(alias = "mtime_4")]
pub type Mtime4 = crate::Reg<mtime_4::Mtime4Spec>;
#[doc = "Timer Register"]
pub mod mtime_4 {
#[doc = "Register `mtime_4` reader"]
pub type R = crate::R<Mtime4Spec>;
#[doc = "Register `mtime_4` writer"]
pub type W = crate::W<Mtime4Spec>;
#[doc = "Field `mtime_4` reader - mtime_4"]
pub type Mtime4R = crate::FieldReader;
#[doc = "Field `mtime_4` writer - mtime_4"]
pub type Mtime4W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `mtime_5` reader - mtime_5"]
pub type Mtime5R = crate::FieldReader;
#[doc = "Field `mtime_5` writer - mtime_5"]
pub type Mtime5W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `mtime_6` reader - mtime_6"]
pub type Mtime6R = crate::FieldReader;
#[doc = "Field `mtime_6` writer - mtime_6"]
pub type Mtime6W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `mtime_7` reader - mtime_7"]
pub type Mtime7R = crate::FieldReader;
#[doc = "Field `mtime_7` writer - mtime_7"]
pub type Mtime7W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:7 - mtime_4"]
#[inline(always)]
pub fn mtime_4(&self) -> Mtime4R {
Mtime4R::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:15 - mtime_5"]
#[inline(always)]
pub fn mtime_5(&self) -> Mtime5R {
Mtime5R::new(((self.bits >> 8) & 0xff) as u8)
}
#[doc = "Bits 16:23 - mtime_6"]
#[inline(always)]
pub fn mtime_6(&self) -> Mtime6R {
Mtime6R::new(((self.bits >> 16) & 0xff) as u8)
}
#[doc = "Bits 24:31 - mtime_7"]
#[inline(always)]
pub fn mtime_7(&self) -> Mtime7R {
Mtime7R::new(((self.bits >> 24) & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:7 - mtime_4"]
#[inline(always)]
pub fn mtime_4(&mut self) -> Mtime4W<Mtime4Spec> {
Mtime4W::new(self, 0)
}
#[doc = "Bits 8:15 - mtime_5"]
#[inline(always)]
pub fn mtime_5(&mut self) -> Mtime5W<Mtime4Spec> {
Mtime5W::new(self, 8)
}
#[doc = "Bits 16:23 - mtime_6"]
#[inline(always)]
pub fn mtime_6(&mut self) -> Mtime6W<Mtime4Spec> {
Mtime6W::new(self, 16)
}
#[doc = "Bits 24:31 - mtime_7"]
#[inline(always)]
pub fn mtime_7(&mut self) -> Mtime7W<Mtime4Spec> {
Mtime7W::new(self, 24)
}
}
#[doc = "Timer Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mtime_4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mtime_4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Mtime4Spec;
impl crate::RegisterSpec for Mtime4Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`mtime_4::R`](R) reader structure"]
impl crate::Readable for Mtime4Spec {}
#[doc = "`write(|w| ..)` method takes [`mtime_4::W`](W) writer structure"]
impl crate::Writable for Mtime4Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets mtime_4 to value 0"]
impl crate::Resettable for Mtime4Spec {}
}
}
#[doc = "Platform local interrupt controller"]
pub type Plic = crate::Periph<plic::RegisterBlock, 0x0c00_0000>;
impl core::fmt::Debug for Plic {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Plic").finish()
}
}
#[doc = "Platform local interrupt controller"]
pub mod plic {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
_reserved0: [u8; 0x04],
flash_priority: FlashPriority,
rtc_priority: RtcPriority,
fcb0_priority: Fcb0Priority,
watchdog0_priority: Watchdog0Priority,
spi0_priority: Spi0Priority,
spi1_priority: Spi1Priority,
gpio0_priority: Gpio0Priority,
gpio1_priority: Gpio1Priority,
gpio2_priority: Gpio2Priority,
gpio3_priority: Gpio3Priority,
gpio4_priority: Gpio4Priority,
gpio5_priority: Gpio5Priority,
gpio6_priority: Gpio6Priority,
gpio7_priority: Gpio7Priority,
gpio8_priority: Gpio8Priority,
gpio9_priority: Gpio9Priority,
timer0_priority: Timer0Priority,
timer1_priority: Timer1Priority,
gptimer0_priority: Gptimer0Priority,
gptimer1_priority: Gptimer1Priority,
gptimer2_priority: Gptimer2Priority,
gptimer3_priority: Gptimer3Priority,
gptimer4_priority: Gptimer4Priority,
uart0_priority: Uart0Priority,
uart1_priority: Uart1Priority,
uart2_priority: Uart2Priority,
uart3_priority: Uart3Priority,
uart4_priority: Uart4Priority,
can0_priority: Can0Priority,
i2c0_priority: I2c0Priority,
i2c1_priority: I2c1Priority,
dmac0_intr_priority: Dmac0IntrPriority,
dmac0_inttc_priority: Dmac0InttcPriority,
dmac0_interr_priority: Dmac0InterrPriority,
usb0_priority: Usb0Priority,
mac0_priority: Mac0Priority,
ext_int0_priority: ExtInt0Priority,
ext_int1_priority: ExtInt1Priority,
ext_int2_priority: ExtInt2Priority,
ext_int3_priority: ExtInt3Priority,
ext_int4_priority: ExtInt4Priority,
ext_int5_priority: ExtInt5Priority,
ext_int6_priority: ExtInt6Priority,
ext_int7_priority: ExtInt7Priority,
_reserved44: [u8; 0x0f4c],
pending_0: Pending0,
pending_1: Pending1,
_reserved46: [u8; 0x0ff8],
enable_0: Enable0,
enable_4: Enable4,
_reserved48: [u8; 0x001f_dff8],
threshold_0: Threshold0,
claim_complete_0: ClaimComplete0,
}
impl RegisterBlock {
#[doc = "0x04 - Acting priority of interrupt FLASH"]
#[inline(always)]
pub const fn flash_priority(&self) -> &FlashPriority {
&self.flash_priority
}
#[doc = "0x08 - Acting priority of interrupt RTC"]
#[inline(always)]
pub const fn rtc_priority(&self) -> &RtcPriority {
&self.rtc_priority
}
#[doc = "0x0c - Acting priority of interrupt FCB0"]
#[inline(always)]
pub const fn fcb0_priority(&self) -> &Fcb0Priority {
&self.fcb0_priority
}
#[doc = "0x10 - Acting priority of interrupt WATCHDOG0"]
#[inline(always)]
pub const fn watchdog0_priority(&self) -> &Watchdog0Priority {
&self.watchdog0_priority
}
#[doc = "0x14 - Acting priority of interrupt SPI0"]
#[inline(always)]
pub const fn spi0_priority(&self) -> &Spi0Priority {
&self.spi0_priority
}
#[doc = "0x18 - Acting priority of interrupt SPI1"]
#[inline(always)]
pub const fn spi1_priority(&self) -> &Spi1Priority {
&self.spi1_priority
}
#[doc = "0x1c - Acting priority of interrupt GPIO0"]
#[inline(always)]
pub const fn gpio0_priority(&self) -> &Gpio0Priority {
&self.gpio0_priority
}
#[doc = "0x20 - Acting priority of interrupt GPIO1"]
#[inline(always)]
pub const fn gpio1_priority(&self) -> &Gpio1Priority {
&self.gpio1_priority
}
#[doc = "0x24 - Acting priority of interrupt GPIO2"]
#[inline(always)]
pub const fn gpio2_priority(&self) -> &Gpio2Priority {
&self.gpio2_priority
}
#[doc = "0x28 - Acting priority of interrupt GPIO3"]
#[inline(always)]
pub const fn gpio3_priority(&self) -> &Gpio3Priority {
&self.gpio3_priority
}
#[doc = "0x2c - Acting priority of interrupt GPIO4"]
#[inline(always)]
pub const fn gpio4_priority(&self) -> &Gpio4Priority {
&self.gpio4_priority
}
#[doc = "0x30 - Acting priority of interrupt GPIO5"]
#[inline(always)]
pub const fn gpio5_priority(&self) -> &Gpio5Priority {
&self.gpio5_priority
}
#[doc = "0x34 - Acting priority of interrupt GPIO6"]
#[inline(always)]
pub const fn gpio6_priority(&self) -> &Gpio6Priority {
&self.gpio6_priority
}
#[doc = "0x38 - Acting priority of interrupt GPIO7"]
#[inline(always)]
pub const fn gpio7_priority(&self) -> &Gpio7Priority {
&self.gpio7_priority
}
#[doc = "0x3c - Acting priority of interrupt GPIO8"]
#[inline(always)]
pub const fn gpio8_priority(&self) -> &Gpio8Priority {
&self.gpio8_priority
}
#[doc = "0x40 - Acting priority of interrupt GPIO9"]
#[inline(always)]
pub const fn gpio9_priority(&self) -> &Gpio9Priority {
&self.gpio9_priority
}
#[doc = "0x44 - Acting priority of interrupt TIMER0"]
#[inline(always)]
pub const fn timer0_priority(&self) -> &Timer0Priority {
&self.timer0_priority
}
#[doc = "0x48 - Acting priority of interrupt TIMER1"]
#[inline(always)]
pub const fn timer1_priority(&self) -> &Timer1Priority {
&self.timer1_priority
}
#[doc = "0x4c - Acting priority of interrupt GPTIMER0"]
#[inline(always)]
pub const fn gptimer0_priority(&self) -> &Gptimer0Priority {
&self.gptimer0_priority
}
#[doc = "0x50 - Acting priority of interrupt GPTIMER1"]
#[inline(always)]
pub const fn gptimer1_priority(&self) -> &Gptimer1Priority {
&self.gptimer1_priority
}
#[doc = "0x54 - Acting priority of interrupt GPTIMER2"]
#[inline(always)]
pub const fn gptimer2_priority(&self) -> &Gptimer2Priority {
&self.gptimer2_priority
}
#[doc = "0x58 - Acting priority of interrupt GPTIMER3"]
#[inline(always)]
pub const fn gptimer3_priority(&self) -> &Gptimer3Priority {
&self.gptimer3_priority
}
#[doc = "0x5c - Acting priority of interrupt GPTIMER4"]
#[inline(always)]
pub const fn gptimer4_priority(&self) -> &Gptimer4Priority {
&self.gptimer4_priority
}
#[doc = "0x60 - Acting priority of interrupt UART0"]
#[inline(always)]
pub const fn uart0_priority(&self) -> &Uart0Priority {
&self.uart0_priority
}
#[doc = "0x64 - Acting priority of interrupt UART1"]
#[inline(always)]
pub const fn uart1_priority(&self) -> &Uart1Priority {
&self.uart1_priority
}
#[doc = "0x68 - Acting priority of interrupt UART2"]
#[inline(always)]
pub const fn uart2_priority(&self) -> &Uart2Priority {
&self.uart2_priority
}
#[doc = "0x6c - Acting priority of interrupt UART3"]
#[inline(always)]
pub const fn uart3_priority(&self) -> &Uart3Priority {
&self.uart3_priority
}
#[doc = "0x70 - Acting priority of interrupt UART4"]
#[inline(always)]
pub const fn uart4_priority(&self) -> &Uart4Priority {
&self.uart4_priority
}
#[doc = "0x74 - Acting priority of interrupt CAN0"]
#[inline(always)]
pub const fn can0_priority(&self) -> &Can0Priority {
&self.can0_priority
}
#[doc = "0x78 - Acting priority of interrupt I2C0"]
#[inline(always)]
pub const fn i2c0_priority(&self) -> &I2c0Priority {
&self.i2c0_priority
}
#[doc = "0x7c - Acting priority of interrupt I2C1"]
#[inline(always)]
pub const fn i2c1_priority(&self) -> &I2c1Priority {
&self.i2c1_priority
}
#[doc = "0x80 - Acting priority of interrupt DMAC0_INTR"]
#[inline(always)]
pub const fn dmac0_intr_priority(&self) -> &Dmac0IntrPriority {
&self.dmac0_intr_priority
}
#[doc = "0x84 - Acting priority of interrupt DMAC0_INTTC"]
#[inline(always)]
pub const fn dmac0_inttc_priority(&self) -> &Dmac0InttcPriority {
&self.dmac0_inttc_priority
}
#[doc = "0x88 - Acting priority of interrupt DMAC0_INTERR"]
#[inline(always)]
pub const fn dmac0_interr_priority(&self) -> &Dmac0InterrPriority {
&self.dmac0_interr_priority
}
#[doc = "0x8c - Acting priority of interrupt USB0"]
#[inline(always)]
pub const fn usb0_priority(&self) -> &Usb0Priority {
&self.usb0_priority
}
#[doc = "0x90 - Acting priority of interrupt MAC0"]
#[inline(always)]
pub const fn mac0_priority(&self) -> &Mac0Priority {
&self.mac0_priority
}
#[doc = "0x94 - Acting priority of interrupt EXT_INT0"]
#[inline(always)]
pub const fn ext_int0_priority(&self) -> &ExtInt0Priority {
&self.ext_int0_priority
}
#[doc = "0x98 - Acting priority of interrupt EXT_INT1"]
#[inline(always)]
pub const fn ext_int1_priority(&self) -> &ExtInt1Priority {
&self.ext_int1_priority
}
#[doc = "0x9c - Acting priority of interrupt EXT_INT2"]
#[inline(always)]
pub const fn ext_int2_priority(&self) -> &ExtInt2Priority {
&self.ext_int2_priority
}
#[doc = "0xa0 - Acting priority of interrupt EXT_INT3"]
#[inline(always)]
pub const fn ext_int3_priority(&self) -> &ExtInt3Priority {
&self.ext_int3_priority
}
#[doc = "0xa4 - Acting priority of interrupt EXT_INT4"]
#[inline(always)]
pub const fn ext_int4_priority(&self) -> &ExtInt4Priority {
&self.ext_int4_priority
}
#[doc = "0xa8 - Acting priority of interrupt EXT_INT5"]
#[inline(always)]
pub const fn ext_int5_priority(&self) -> &ExtInt5Priority {
&self.ext_int5_priority
}
#[doc = "0xac - Acting priority of interrupt EXT_INT6"]
#[inline(always)]
pub const fn ext_int6_priority(&self) -> &ExtInt6Priority {
&self.ext_int6_priority
}
#[doc = "0xb0 - Acting priority of interrupt EXT_INT7"]
#[inline(always)]
pub const fn ext_int7_priority(&self) -> &ExtInt7Priority {
&self.ext_int7_priority
}
#[doc = "0x1000 - Pending bit array"]
#[inline(always)]
pub const fn pending_0(&self) -> &Pending0 {
&self.pending_0
}
#[doc = "0x1004 - Pending bit array"]
#[inline(always)]
pub const fn pending_1(&self) -> &Pending1 {
&self.pending_1
}
#[doc = "0x2000 - Enable bits for each interrupt source for target 0. 1 bit for each interrupt source."]
#[inline(always)]
pub const fn enable_0(&self) -> &Enable0 {
&self.enable_0
}
#[doc = "0x2004 - Enable bits for each interrupt source for target 0. 1 bit for each interrupt source."]
#[inline(always)]
pub const fn enable_4(&self) -> &Enable4 {
&self.enable_4
}
#[doc = "0x200000 - Interrupt claim threshold for target 0. Maximum value is 15."]
#[inline(always)]
pub const fn threshold_0(&self) -> &Threshold0 {
&self.threshold_0
}
#[doc = "0x200004 - Claim/Complete register for Target 0. Reading this register returns the claimed interrupt number and makes it no longer pending.Writing the interrupt number back completes the interrupt."]
#[inline(always)]
pub const fn claim_complete_0(&self) -> &ClaimComplete0 {
&self.claim_complete_0
}
}
#[doc = "FLASH_PRIORITY (rw) register accessor: Acting priority of interrupt FLASH\n\nYou can [`read`](crate::Reg::read) this register and get [`flash_priority::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flash_priority::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flash_priority`] module"]
#[doc(alias = "FLASH_PRIORITY")]
pub type FlashPriority = crate::Reg<flash_priority::FlashPrioritySpec>;
#[doc = "Acting priority of interrupt FLASH"]
pub mod flash_priority {
#[doc = "Register `FLASH_PRIORITY` reader"]
pub type R = crate::R<FlashPrioritySpec>;
#[doc = "Register `FLASH_PRIORITY` writer"]
pub type W = crate::W<FlashPrioritySpec>;
#[doc = "Field `FLASH_PRIORITY` reader - Acting priority of interrupt FLASH"]
pub type FlashPriorityR = crate::FieldReader;
#[doc = "Field `FLASH_PRIORITY` writer - Acting priority of interrupt FLASH"]
pub type FlashPriorityW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
impl R {
#[doc = "Bits 0:3 - Acting priority of interrupt FLASH"]
#[inline(always)]
pub fn flash_priority(&self) -> FlashPriorityR {
FlashPriorityR::new((self.bits & 0x0f) as u8)
}
}
impl W {
#[doc = "Bits 0:3 - Acting priority of interrupt FLASH"]
#[inline(always)]
pub fn flash_priority(&mut self) -> FlashPriorityW<FlashPrioritySpec> {
FlashPriorityW::new(self, 0)
}
}
#[doc = "Acting priority of interrupt FLASH\n\nYou can [`read`](crate::Reg::read) this register and get [`flash_priority::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flash_priority::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FlashPrioritySpec;
impl crate::RegisterSpec for FlashPrioritySpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`flash_priority::R`](R) reader structure"]
impl crate::Readable for FlashPrioritySpec {}
#[doc = "`write(|w| ..)` method takes [`flash_priority::W`](W) writer structure"]
impl crate::Writable for FlashPrioritySpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets FLASH_PRIORITY to value 0"]
impl crate::Resettable for FlashPrioritySpec {}
}
#[doc = "RTC_PRIORITY (rw) register accessor: Acting priority of interrupt RTC\n\nYou can [`read`](crate::Reg::read) this register and get [`rtc_priority::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtc_priority::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtc_priority`] module"]
#[doc(alias = "RTC_PRIORITY")]
pub type RtcPriority = crate::Reg<rtc_priority::RtcPrioritySpec>;
#[doc = "Acting priority of interrupt RTC"]
pub mod rtc_priority {
#[doc = "Register `RTC_PRIORITY` reader"]
pub type R = crate::R<RtcPrioritySpec>;
#[doc = "Register `RTC_PRIORITY` writer"]
pub type W = crate::W<RtcPrioritySpec>;
#[doc = "Field `RTC_PRIORITY` reader - Acting priority of interrupt RTC"]
pub type RtcPriorityR = crate::FieldReader;
#[doc = "Field `RTC_PRIORITY` writer - Acting priority of interrupt RTC"]
pub type RtcPriorityW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
impl R {
#[doc = "Bits 0:3 - Acting priority of interrupt RTC"]
#[inline(always)]
pub fn rtc_priority(&self) -> RtcPriorityR {
RtcPriorityR::new((self.bits & 0x0f) as u8)
}
}
impl W {
#[doc = "Bits 0:3 - Acting priority of interrupt RTC"]
#[inline(always)]
pub fn rtc_priority(&mut self) -> RtcPriorityW<RtcPrioritySpec> {
RtcPriorityW::new(self, 0)
}
}
#[doc = "Acting priority of interrupt RTC\n\nYou can [`read`](crate::Reg::read) this register and get [`rtc_priority::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtc_priority::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RtcPrioritySpec;
impl crate::RegisterSpec for RtcPrioritySpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rtc_priority::R`](R) reader structure"]
impl crate::Readable for RtcPrioritySpec {}
#[doc = "`write(|w| ..)` method takes [`rtc_priority::W`](W) writer structure"]
impl crate::Writable for RtcPrioritySpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets RTC_PRIORITY to value 0"]
impl crate::Resettable for RtcPrioritySpec {}
}
#[doc = "FCB0_PRIORITY (rw) register accessor: Acting priority of interrupt FCB0\n\nYou can [`read`](crate::Reg::read) this register and get [`fcb0_priority::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fcb0_priority::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fcb0_priority`] module"]
#[doc(alias = "FCB0_PRIORITY")]
pub type Fcb0Priority = crate::Reg<fcb0_priority::Fcb0PrioritySpec>;
#[doc = "Acting priority of interrupt FCB0"]
pub mod fcb0_priority {
#[doc = "Register `FCB0_PRIORITY` reader"]
pub type R = crate::R<Fcb0PrioritySpec>;
#[doc = "Register `FCB0_PRIORITY` writer"]
pub type W = crate::W<Fcb0PrioritySpec>;
#[doc = "Field `FCB0_PRIORITY` reader - Acting priority of interrupt FCB0"]
pub type Fcb0PriorityR = crate::FieldReader;
#[doc = "Field `FCB0_PRIORITY` writer - Acting priority of interrupt FCB0"]
pub type Fcb0PriorityW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
impl R {
#[doc = "Bits 0:3 - Acting priority of interrupt FCB0"]
#[inline(always)]
pub fn fcb0_priority(&self) -> Fcb0PriorityR {
Fcb0PriorityR::new((self.bits & 0x0f) as u8)
}
}
impl W {
#[doc = "Bits 0:3 - Acting priority of interrupt FCB0"]
#[inline(always)]
pub fn fcb0_priority(&mut self) -> Fcb0PriorityW<Fcb0PrioritySpec> {
Fcb0PriorityW::new(self, 0)
}
}
#[doc = "Acting priority of interrupt FCB0\n\nYou can [`read`](crate::Reg::read) this register and get [`fcb0_priority::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fcb0_priority::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Fcb0PrioritySpec;
impl crate::RegisterSpec for Fcb0PrioritySpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`fcb0_priority::R`](R) reader structure"]
impl crate::Readable for Fcb0PrioritySpec {}
#[doc = "`write(|w| ..)` method takes [`fcb0_priority::W`](W) writer structure"]
impl crate::Writable for Fcb0PrioritySpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets FCB0_PRIORITY to value 0"]
impl crate::Resettable for Fcb0PrioritySpec {}
}
#[doc = "WATCHDOG0_PRIORITY (rw) register accessor: Acting priority of interrupt WATCHDOG0\n\nYou can [`read`](crate::Reg::read) this register and get [`watchdog0_priority::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`watchdog0_priority::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@watchdog0_priority`] module"]
#[doc(alias = "WATCHDOG0_PRIORITY")]
pub type Watchdog0Priority = crate::Reg<watchdog0_priority::Watchdog0PrioritySpec>;
#[doc = "Acting priority of interrupt WATCHDOG0"]
pub mod watchdog0_priority {
#[doc = "Register `WATCHDOG0_PRIORITY` reader"]
pub type R = crate::R<Watchdog0PrioritySpec>;
#[doc = "Register `WATCHDOG0_PRIORITY` writer"]
pub type W = crate::W<Watchdog0PrioritySpec>;
#[doc = "Field `WATCHDOG0_PRIORITY` reader - Acting priority of interrupt WATCHDOG0"]
pub type Watchdog0PriorityR = crate::FieldReader;
#[doc = "Field `WATCHDOG0_PRIORITY` writer - Acting priority of interrupt WATCHDOG0"]
pub type Watchdog0PriorityW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
impl R {
#[doc = "Bits 0:3 - Acting priority of interrupt WATCHDOG0"]
#[inline(always)]
pub fn watchdog0_priority(&self) -> Watchdog0PriorityR {
Watchdog0PriorityR::new((self.bits & 0x0f) as u8)
}
}
impl W {
#[doc = "Bits 0:3 - Acting priority of interrupt WATCHDOG0"]
#[inline(always)]
pub fn watchdog0_priority(&mut self) -> Watchdog0PriorityW<Watchdog0PrioritySpec> {
Watchdog0PriorityW::new(self, 0)
}
}
#[doc = "Acting priority of interrupt WATCHDOG0\n\nYou can [`read`](crate::Reg::read) this register and get [`watchdog0_priority::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`watchdog0_priority::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Watchdog0PrioritySpec;
impl crate::RegisterSpec for Watchdog0PrioritySpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`watchdog0_priority::R`](R) reader structure"]
impl crate::Readable for Watchdog0PrioritySpec {}
#[doc = "`write(|w| ..)` method takes [`watchdog0_priority::W`](W) writer structure"]
impl crate::Writable for Watchdog0PrioritySpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets WATCHDOG0_PRIORITY to value 0"]
impl crate::Resettable for Watchdog0PrioritySpec {}
}
#[doc = "SPI0_PRIORITY (rw) register accessor: Acting priority of interrupt SPI0\n\nYou can [`read`](crate::Reg::read) this register and get [`spi0_priority::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi0_priority::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi0_priority`] module"]
#[doc(alias = "SPI0_PRIORITY")]
pub type Spi0Priority = crate::Reg<spi0_priority::Spi0PrioritySpec>;
#[doc = "Acting priority of interrupt SPI0"]
pub mod spi0_priority {
#[doc = "Register `SPI0_PRIORITY` reader"]
pub type R = crate::R<Spi0PrioritySpec>;
#[doc = "Register `SPI0_PRIORITY` writer"]
pub type W = crate::W<Spi0PrioritySpec>;
#[doc = "Field `SPI0_PRIORITY` reader - Acting priority of interrupt SPI0"]
pub type Spi0PriorityR = crate::FieldReader;
#[doc = "Field `SPI0_PRIORITY` writer - Acting priority of interrupt SPI0"]
pub type Spi0PriorityW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
impl R {
#[doc = "Bits 0:3 - Acting priority of interrupt SPI0"]
#[inline(always)]
pub fn spi0_priority(&self) -> Spi0PriorityR {
Spi0PriorityR::new((self.bits & 0x0f) as u8)
}
}
impl W {
#[doc = "Bits 0:3 - Acting priority of interrupt SPI0"]
#[inline(always)]
pub fn spi0_priority(&mut self) -> Spi0PriorityW<Spi0PrioritySpec> {
Spi0PriorityW::new(self, 0)
}
}
#[doc = "Acting priority of interrupt SPI0\n\nYou can [`read`](crate::Reg::read) this register and get [`spi0_priority::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi0_priority::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Spi0PrioritySpec;
impl crate::RegisterSpec for Spi0PrioritySpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`spi0_priority::R`](R) reader structure"]
impl crate::Readable for Spi0PrioritySpec {}
#[doc = "`write(|w| ..)` method takes [`spi0_priority::W`](W) writer structure"]
impl crate::Writable for Spi0PrioritySpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets SPI0_PRIORITY to value 0"]
impl crate::Resettable for Spi0PrioritySpec {}
}
#[doc = "SPI1_PRIORITY (rw) register accessor: Acting priority of interrupt SPI1\n\nYou can [`read`](crate::Reg::read) this register and get [`spi1_priority::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi1_priority::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi1_priority`] module"]
#[doc(alias = "SPI1_PRIORITY")]
pub type Spi1Priority = crate::Reg<spi1_priority::Spi1PrioritySpec>;
#[doc = "Acting priority of interrupt SPI1"]
pub mod spi1_priority {
#[doc = "Register `SPI1_PRIORITY` reader"]
pub type R = crate::R<Spi1PrioritySpec>;
#[doc = "Register `SPI1_PRIORITY` writer"]
pub type W = crate::W<Spi1PrioritySpec>;
#[doc = "Field `SPI1_PRIORITY` reader - Acting priority of interrupt SPI1"]
pub type Spi1PriorityR = crate::FieldReader;
#[doc = "Field `SPI1_PRIORITY` writer - Acting priority of interrupt SPI1"]
pub type Spi1PriorityW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
impl R {
#[doc = "Bits 0:3 - Acting priority of interrupt SPI1"]
#[inline(always)]
pub fn spi1_priority(&self) -> Spi1PriorityR {
Spi1PriorityR::new((self.bits & 0x0f) as u8)
}
}
impl W {
#[doc = "Bits 0:3 - Acting priority of interrupt SPI1"]
#[inline(always)]
pub fn spi1_priority(&mut self) -> Spi1PriorityW<Spi1PrioritySpec> {
Spi1PriorityW::new(self, 0)
}
}
#[doc = "Acting priority of interrupt SPI1\n\nYou can [`read`](crate::Reg::read) this register and get [`spi1_priority::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi1_priority::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Spi1PrioritySpec;
impl crate::RegisterSpec for Spi1PrioritySpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`spi1_priority::R`](R) reader structure"]
impl crate::Readable for Spi1PrioritySpec {}
#[doc = "`write(|w| ..)` method takes [`spi1_priority::W`](W) writer structure"]
impl crate::Writable for Spi1PrioritySpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets SPI1_PRIORITY to value 0"]
impl crate::Resettable for Spi1PrioritySpec {}
}
#[doc = "GPIO0_PRIORITY (rw) register accessor: Acting priority of interrupt GPIO0\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio0_priority::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio0_priority::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio0_priority`] module"]
#[doc(alias = "GPIO0_PRIORITY")]
pub type Gpio0Priority = crate::Reg<gpio0_priority::Gpio0PrioritySpec>;
#[doc = "Acting priority of interrupt GPIO0"]
pub mod gpio0_priority {
#[doc = "Register `GPIO0_PRIORITY` reader"]
pub type R = crate::R<Gpio0PrioritySpec>;
#[doc = "Register `GPIO0_PRIORITY` writer"]
pub type W = crate::W<Gpio0PrioritySpec>;
#[doc = "Field `GPIO0_PRIORITY` reader - Acting priority of interrupt GPIO0"]
pub type Gpio0PriorityR = crate::FieldReader;
#[doc = "Field `GPIO0_PRIORITY` writer - Acting priority of interrupt GPIO0"]
pub type Gpio0PriorityW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
impl R {
#[doc = "Bits 0:3 - Acting priority of interrupt GPIO0"]
#[inline(always)]
pub fn gpio0_priority(&self) -> Gpio0PriorityR {
Gpio0PriorityR::new((self.bits & 0x0f) as u8)
}
}
impl W {
#[doc = "Bits 0:3 - Acting priority of interrupt GPIO0"]
#[inline(always)]
pub fn gpio0_priority(&mut self) -> Gpio0PriorityW<Gpio0PrioritySpec> {
Gpio0PriorityW::new(self, 0)
}
}
#[doc = "Acting priority of interrupt GPIO0\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio0_priority::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio0_priority::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Gpio0PrioritySpec;
impl crate::RegisterSpec for Gpio0PrioritySpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`gpio0_priority::R`](R) reader structure"]
impl crate::Readable for Gpio0PrioritySpec {}
#[doc = "`write(|w| ..)` method takes [`gpio0_priority::W`](W) writer structure"]
impl crate::Writable for Gpio0PrioritySpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets GPIO0_PRIORITY to value 0"]
impl crate::Resettable for Gpio0PrioritySpec {}
}
#[doc = "GPIO1_PRIORITY (rw) register accessor: Acting priority of interrupt GPIO1\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio1_priority::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio1_priority::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio1_priority`] module"]
#[doc(alias = "GPIO1_PRIORITY")]
pub type Gpio1Priority = crate::Reg<gpio1_priority::Gpio1PrioritySpec>;
#[doc = "Acting priority of interrupt GPIO1"]
pub mod gpio1_priority {
#[doc = "Register `GPIO1_PRIORITY` reader"]
pub type R = crate::R<Gpio1PrioritySpec>;
#[doc = "Register `GPIO1_PRIORITY` writer"]
pub type W = crate::W<Gpio1PrioritySpec>;
#[doc = "Field `GPIO1_PRIORITY` reader - Acting priority of interrupt GPIO1"]
pub type Gpio1PriorityR = crate::FieldReader;
#[doc = "Field `GPIO1_PRIORITY` writer - Acting priority of interrupt GPIO1"]
pub type Gpio1PriorityW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
impl R {
#[doc = "Bits 0:3 - Acting priority of interrupt GPIO1"]
#[inline(always)]
pub fn gpio1_priority(&self) -> Gpio1PriorityR {
Gpio1PriorityR::new((self.bits & 0x0f) as u8)
}
}
impl W {
#[doc = "Bits 0:3 - Acting priority of interrupt GPIO1"]
#[inline(always)]
pub fn gpio1_priority(&mut self) -> Gpio1PriorityW<Gpio1PrioritySpec> {
Gpio1PriorityW::new(self, 0)
}
}
#[doc = "Acting priority of interrupt GPIO1\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio1_priority::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio1_priority::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Gpio1PrioritySpec;
impl crate::RegisterSpec for Gpio1PrioritySpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`gpio1_priority::R`](R) reader structure"]
impl crate::Readable for Gpio1PrioritySpec {}
#[doc = "`write(|w| ..)` method takes [`gpio1_priority::W`](W) writer structure"]
impl crate::Writable for Gpio1PrioritySpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets GPIO1_PRIORITY to value 0"]
impl crate::Resettable for Gpio1PrioritySpec {}
}
#[doc = "GPIO2_PRIORITY (rw) register accessor: Acting priority of interrupt GPIO2\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio2_priority::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio2_priority::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio2_priority`] module"]
#[doc(alias = "GPIO2_PRIORITY")]
pub type Gpio2Priority = crate::Reg<gpio2_priority::Gpio2PrioritySpec>;
#[doc = "Acting priority of interrupt GPIO2"]
pub mod gpio2_priority {
#[doc = "Register `GPIO2_PRIORITY` reader"]
pub type R = crate::R<Gpio2PrioritySpec>;
#[doc = "Register `GPIO2_PRIORITY` writer"]
pub type W = crate::W<Gpio2PrioritySpec>;
#[doc = "Field `GPIO2_PRIORITY` reader - Acting priority of interrupt GPIO2"]
pub type Gpio2PriorityR = crate::FieldReader;
#[doc = "Field `GPIO2_PRIORITY` writer - Acting priority of interrupt GPIO2"]
pub type Gpio2PriorityW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
impl R {
#[doc = "Bits 0:3 - Acting priority of interrupt GPIO2"]
#[inline(always)]
pub fn gpio2_priority(&self) -> Gpio2PriorityR {
Gpio2PriorityR::new((self.bits & 0x0f) as u8)
}
}
impl W {
#[doc = "Bits 0:3 - Acting priority of interrupt GPIO2"]
#[inline(always)]
pub fn gpio2_priority(&mut self) -> Gpio2PriorityW<Gpio2PrioritySpec> {
Gpio2PriorityW::new(self, 0)
}
}
#[doc = "Acting priority of interrupt GPIO2\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio2_priority::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio2_priority::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Gpio2PrioritySpec;
impl crate::RegisterSpec for Gpio2PrioritySpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`gpio2_priority::R`](R) reader structure"]
impl crate::Readable for Gpio2PrioritySpec {}
#[doc = "`write(|w| ..)` method takes [`gpio2_priority::W`](W) writer structure"]
impl crate::Writable for Gpio2PrioritySpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets GPIO2_PRIORITY to value 0"]
impl crate::Resettable for Gpio2PrioritySpec {}
}
#[doc = "GPIO3_PRIORITY (rw) register accessor: Acting priority of interrupt GPIO3\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio3_priority::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio3_priority::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio3_priority`] module"]
#[doc(alias = "GPIO3_PRIORITY")]
pub type Gpio3Priority = crate::Reg<gpio3_priority::Gpio3PrioritySpec>;
#[doc = "Acting priority of interrupt GPIO3"]
pub mod gpio3_priority {
#[doc = "Register `GPIO3_PRIORITY` reader"]
pub type R = crate::R<Gpio3PrioritySpec>;
#[doc = "Register `GPIO3_PRIORITY` writer"]
pub type W = crate::W<Gpio3PrioritySpec>;
#[doc = "Field `GPIO3_PRIORITY` reader - Acting priority of interrupt GPIO3"]
pub type Gpio3PriorityR = crate::FieldReader;
#[doc = "Field `GPIO3_PRIORITY` writer - Acting priority of interrupt GPIO3"]
pub type Gpio3PriorityW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
impl R {
#[doc = "Bits 0:3 - Acting priority of interrupt GPIO3"]
#[inline(always)]
pub fn gpio3_priority(&self) -> Gpio3PriorityR {
Gpio3PriorityR::new((self.bits & 0x0f) as u8)
}
}
impl W {
#[doc = "Bits 0:3 - Acting priority of interrupt GPIO3"]
#[inline(always)]
pub fn gpio3_priority(&mut self) -> Gpio3PriorityW<Gpio3PrioritySpec> {
Gpio3PriorityW::new(self, 0)
}
}
#[doc = "Acting priority of interrupt GPIO3\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio3_priority::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio3_priority::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Gpio3PrioritySpec;
impl crate::RegisterSpec for Gpio3PrioritySpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`gpio3_priority::R`](R) reader structure"]
impl crate::Readable for Gpio3PrioritySpec {}
#[doc = "`write(|w| ..)` method takes [`gpio3_priority::W`](W) writer structure"]
impl crate::Writable for Gpio3PrioritySpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets GPIO3_PRIORITY to value 0"]
impl crate::Resettable for Gpio3PrioritySpec {}
}
#[doc = "GPIO4_PRIORITY (rw) register accessor: Acting priority of interrupt GPIO4\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio4_priority::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio4_priority::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio4_priority`] module"]
#[doc(alias = "GPIO4_PRIORITY")]
pub type Gpio4Priority = crate::Reg<gpio4_priority::Gpio4PrioritySpec>;
#[doc = "Acting priority of interrupt GPIO4"]
pub mod gpio4_priority {
#[doc = "Register `GPIO4_PRIORITY` reader"]
pub type R = crate::R<Gpio4PrioritySpec>;
#[doc = "Register `GPIO4_PRIORITY` writer"]
pub type W = crate::W<Gpio4PrioritySpec>;
#[doc = "Field `GPIO4_PRIORITY` reader - Acting priority of interrupt GPIO4"]
pub type Gpio4PriorityR = crate::FieldReader;
#[doc = "Field `GPIO4_PRIORITY` writer - Acting priority of interrupt GPIO4"]
pub type Gpio4PriorityW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
impl R {
#[doc = "Bits 0:3 - Acting priority of interrupt GPIO4"]
#[inline(always)]
pub fn gpio4_priority(&self) -> Gpio4PriorityR {
Gpio4PriorityR::new((self.bits & 0x0f) as u8)
}
}
impl W {
#[doc = "Bits 0:3 - Acting priority of interrupt GPIO4"]
#[inline(always)]
pub fn gpio4_priority(&mut self) -> Gpio4PriorityW<Gpio4PrioritySpec> {
Gpio4PriorityW::new(self, 0)
}
}
#[doc = "Acting priority of interrupt GPIO4\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio4_priority::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio4_priority::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Gpio4PrioritySpec;
impl crate::RegisterSpec for Gpio4PrioritySpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`gpio4_priority::R`](R) reader structure"]
impl crate::Readable for Gpio4PrioritySpec {}
#[doc = "`write(|w| ..)` method takes [`gpio4_priority::W`](W) writer structure"]
impl crate::Writable for Gpio4PrioritySpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets GPIO4_PRIORITY to value 0"]
impl crate::Resettable for Gpio4PrioritySpec {}
}
#[doc = "GPIO5_PRIORITY (rw) register accessor: Acting priority of interrupt GPIO5\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio5_priority::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio5_priority::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio5_priority`] module"]
#[doc(alias = "GPIO5_PRIORITY")]
pub type Gpio5Priority = crate::Reg<gpio5_priority::Gpio5PrioritySpec>;
#[doc = "Acting priority of interrupt GPIO5"]
pub mod gpio5_priority {
#[doc = "Register `GPIO5_PRIORITY` reader"]
pub type R = crate::R<Gpio5PrioritySpec>;
#[doc = "Register `GPIO5_PRIORITY` writer"]
pub type W = crate::W<Gpio5PrioritySpec>;
#[doc = "Field `GPIO5_PRIORITY` reader - Acting priority of interrupt GPIO5"]
pub type Gpio5PriorityR = crate::FieldReader;
#[doc = "Field `GPIO5_PRIORITY` writer - Acting priority of interrupt GPIO5"]
pub type Gpio5PriorityW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
impl R {
#[doc = "Bits 0:3 - Acting priority of interrupt GPIO5"]
#[inline(always)]
pub fn gpio5_priority(&self) -> Gpio5PriorityR {
Gpio5PriorityR::new((self.bits & 0x0f) as u8)
}
}
impl W {
#[doc = "Bits 0:3 - Acting priority of interrupt GPIO5"]
#[inline(always)]
pub fn gpio5_priority(&mut self) -> Gpio5PriorityW<Gpio5PrioritySpec> {
Gpio5PriorityW::new(self, 0)
}
}
#[doc = "Acting priority of interrupt GPIO5\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio5_priority::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio5_priority::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Gpio5PrioritySpec;
impl crate::RegisterSpec for Gpio5PrioritySpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`gpio5_priority::R`](R) reader structure"]
impl crate::Readable for Gpio5PrioritySpec {}
#[doc = "`write(|w| ..)` method takes [`gpio5_priority::W`](W) writer structure"]
impl crate::Writable for Gpio5PrioritySpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets GPIO5_PRIORITY to value 0"]
impl crate::Resettable for Gpio5PrioritySpec {}
}
#[doc = "GPIO6_PRIORITY (rw) register accessor: Acting priority of interrupt GPIO6\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio6_priority::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio6_priority::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio6_priority`] module"]
#[doc(alias = "GPIO6_PRIORITY")]
pub type Gpio6Priority = crate::Reg<gpio6_priority::Gpio6PrioritySpec>;
#[doc = "Acting priority of interrupt GPIO6"]
pub mod gpio6_priority {
#[doc = "Register `GPIO6_PRIORITY` reader"]
pub type R = crate::R<Gpio6PrioritySpec>;
#[doc = "Register `GPIO6_PRIORITY` writer"]
pub type W = crate::W<Gpio6PrioritySpec>;
#[doc = "Field `GPIO6_PRIORITY` reader - Acting priority of interrupt GPIO6"]
pub type Gpio6PriorityR = crate::FieldReader;
#[doc = "Field `GPIO6_PRIORITY` writer - Acting priority of interrupt GPIO6"]
pub type Gpio6PriorityW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
impl R {
#[doc = "Bits 0:3 - Acting priority of interrupt GPIO6"]
#[inline(always)]
pub fn gpio6_priority(&self) -> Gpio6PriorityR {
Gpio6PriorityR::new((self.bits & 0x0f) as u8)
}
}
impl W {
#[doc = "Bits 0:3 - Acting priority of interrupt GPIO6"]
#[inline(always)]
pub fn gpio6_priority(&mut self) -> Gpio6PriorityW<Gpio6PrioritySpec> {
Gpio6PriorityW::new(self, 0)
}
}
#[doc = "Acting priority of interrupt GPIO6\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio6_priority::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio6_priority::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Gpio6PrioritySpec;
impl crate::RegisterSpec for Gpio6PrioritySpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`gpio6_priority::R`](R) reader structure"]
impl crate::Readable for Gpio6PrioritySpec {}
#[doc = "`write(|w| ..)` method takes [`gpio6_priority::W`](W) writer structure"]
impl crate::Writable for Gpio6PrioritySpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets GPIO6_PRIORITY to value 0"]
impl crate::Resettable for Gpio6PrioritySpec {}
}
#[doc = "GPIO7_PRIORITY (rw) register accessor: Acting priority of interrupt GPIO7\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio7_priority::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio7_priority::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio7_priority`] module"]
#[doc(alias = "GPIO7_PRIORITY")]
pub type Gpio7Priority = crate::Reg<gpio7_priority::Gpio7PrioritySpec>;
#[doc = "Acting priority of interrupt GPIO7"]
pub mod gpio7_priority {
#[doc = "Register `GPIO7_PRIORITY` reader"]
pub type R = crate::R<Gpio7PrioritySpec>;
#[doc = "Register `GPIO7_PRIORITY` writer"]
pub type W = crate::W<Gpio7PrioritySpec>;
#[doc = "Field `GPIO7_PRIORITY` reader - Acting priority of interrupt GPIO7"]
pub type Gpio7PriorityR = crate::FieldReader;
#[doc = "Field `GPIO7_PRIORITY` writer - Acting priority of interrupt GPIO7"]
pub type Gpio7PriorityW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
impl R {
#[doc = "Bits 0:3 - Acting priority of interrupt GPIO7"]
#[inline(always)]
pub fn gpio7_priority(&self) -> Gpio7PriorityR {
Gpio7PriorityR::new((self.bits & 0x0f) as u8)
}
}
impl W {
#[doc = "Bits 0:3 - Acting priority of interrupt GPIO7"]
#[inline(always)]
pub fn gpio7_priority(&mut self) -> Gpio7PriorityW<Gpio7PrioritySpec> {
Gpio7PriorityW::new(self, 0)
}
}
#[doc = "Acting priority of interrupt GPIO7\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio7_priority::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio7_priority::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Gpio7PrioritySpec;
impl crate::RegisterSpec for Gpio7PrioritySpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`gpio7_priority::R`](R) reader structure"]
impl crate::Readable for Gpio7PrioritySpec {}
#[doc = "`write(|w| ..)` method takes [`gpio7_priority::W`](W) writer structure"]
impl crate::Writable for Gpio7PrioritySpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets GPIO7_PRIORITY to value 0"]
impl crate::Resettable for Gpio7PrioritySpec {}
}
#[doc = "GPIO8_PRIORITY (rw) register accessor: Acting priority of interrupt GPIO8\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio8_priority::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio8_priority::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio8_priority`] module"]
#[doc(alias = "GPIO8_PRIORITY")]
pub type Gpio8Priority = crate::Reg<gpio8_priority::Gpio8PrioritySpec>;
#[doc = "Acting priority of interrupt GPIO8"]
pub mod gpio8_priority {
#[doc = "Register `GPIO8_PRIORITY` reader"]
pub type R = crate::R<Gpio8PrioritySpec>;
#[doc = "Register `GPIO8_PRIORITY` writer"]
pub type W = crate::W<Gpio8PrioritySpec>;
#[doc = "Field `GPIO8_PRIORITY` reader - Acting priority of interrupt GPIO8"]
pub type Gpio8PriorityR = crate::FieldReader;
#[doc = "Field `GPIO8_PRIORITY` writer - Acting priority of interrupt GPIO8"]
pub type Gpio8PriorityW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
impl R {
#[doc = "Bits 0:3 - Acting priority of interrupt GPIO8"]
#[inline(always)]
pub fn gpio8_priority(&self) -> Gpio8PriorityR {
Gpio8PriorityR::new((self.bits & 0x0f) as u8)
}
}
impl W {
#[doc = "Bits 0:3 - Acting priority of interrupt GPIO8"]
#[inline(always)]
pub fn gpio8_priority(&mut self) -> Gpio8PriorityW<Gpio8PrioritySpec> {
Gpio8PriorityW::new(self, 0)
}
}
#[doc = "Acting priority of interrupt GPIO8\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio8_priority::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio8_priority::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Gpio8PrioritySpec;
impl crate::RegisterSpec for Gpio8PrioritySpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`gpio8_priority::R`](R) reader structure"]
impl crate::Readable for Gpio8PrioritySpec {}
#[doc = "`write(|w| ..)` method takes [`gpio8_priority::W`](W) writer structure"]
impl crate::Writable for Gpio8PrioritySpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets GPIO8_PRIORITY to value 0"]
impl crate::Resettable for Gpio8PrioritySpec {}
}
#[doc = "GPIO9_PRIORITY (rw) register accessor: Acting priority of interrupt GPIO9\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio9_priority::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio9_priority::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpio9_priority`] module"]
#[doc(alias = "GPIO9_PRIORITY")]
pub type Gpio9Priority = crate::Reg<gpio9_priority::Gpio9PrioritySpec>;
#[doc = "Acting priority of interrupt GPIO9"]
pub mod gpio9_priority {
#[doc = "Register `GPIO9_PRIORITY` reader"]
pub type R = crate::R<Gpio9PrioritySpec>;
#[doc = "Register `GPIO9_PRIORITY` writer"]
pub type W = crate::W<Gpio9PrioritySpec>;
#[doc = "Field `GPIO9_PRIORITY` reader - Acting priority of interrupt GPIO9"]
pub type Gpio9PriorityR = crate::FieldReader;
#[doc = "Field `GPIO9_PRIORITY` writer - Acting priority of interrupt GPIO9"]
pub type Gpio9PriorityW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
impl R {
#[doc = "Bits 0:3 - Acting priority of interrupt GPIO9"]
#[inline(always)]
pub fn gpio9_priority(&self) -> Gpio9PriorityR {
Gpio9PriorityR::new((self.bits & 0x0f) as u8)
}
}
impl W {
#[doc = "Bits 0:3 - Acting priority of interrupt GPIO9"]
#[inline(always)]
pub fn gpio9_priority(&mut self) -> Gpio9PriorityW<Gpio9PrioritySpec> {
Gpio9PriorityW::new(self, 0)
}
}
#[doc = "Acting priority of interrupt GPIO9\n\nYou can [`read`](crate::Reg::read) this register and get [`gpio9_priority::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio9_priority::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Gpio9PrioritySpec;
impl crate::RegisterSpec for Gpio9PrioritySpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`gpio9_priority::R`](R) reader structure"]
impl crate::Readable for Gpio9PrioritySpec {}
#[doc = "`write(|w| ..)` method takes [`gpio9_priority::W`](W) writer structure"]
impl crate::Writable for Gpio9PrioritySpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets GPIO9_PRIORITY to value 0"]
impl crate::Resettable for Gpio9PrioritySpec {}
}
#[doc = "TIMER0_PRIORITY (rw) register accessor: Acting priority of interrupt TIMER0\n\nYou can [`read`](crate::Reg::read) this register and get [`timer0_priority::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer0_priority::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timer0_priority`] module"]
#[doc(alias = "TIMER0_PRIORITY")]
pub type Timer0Priority = crate::Reg<timer0_priority::Timer0PrioritySpec>;
#[doc = "Acting priority of interrupt TIMER0"]
pub mod timer0_priority {
#[doc = "Register `TIMER0_PRIORITY` reader"]
pub type R = crate::R<Timer0PrioritySpec>;
#[doc = "Register `TIMER0_PRIORITY` writer"]
pub type W = crate::W<Timer0PrioritySpec>;
#[doc = "Field `TIMER0_PRIORITY` reader - Acting priority of interrupt TIMER0"]
pub type Timer0PriorityR = crate::FieldReader;
#[doc = "Field `TIMER0_PRIORITY` writer - Acting priority of interrupt TIMER0"]
pub type Timer0PriorityW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
impl R {
#[doc = "Bits 0:3 - Acting priority of interrupt TIMER0"]
#[inline(always)]
pub fn timer0_priority(&self) -> Timer0PriorityR {
Timer0PriorityR::new((self.bits & 0x0f) as u8)
}
}
impl W {
#[doc = "Bits 0:3 - Acting priority of interrupt TIMER0"]
#[inline(always)]
pub fn timer0_priority(&mut self) -> Timer0PriorityW<Timer0PrioritySpec> {
Timer0PriorityW::new(self, 0)
}
}
#[doc = "Acting priority of interrupt TIMER0\n\nYou can [`read`](crate::Reg::read) this register and get [`timer0_priority::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer0_priority::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Timer0PrioritySpec;
impl crate::RegisterSpec for Timer0PrioritySpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`timer0_priority::R`](R) reader structure"]
impl crate::Readable for Timer0PrioritySpec {}
#[doc = "`write(|w| ..)` method takes [`timer0_priority::W`](W) writer structure"]
impl crate::Writable for Timer0PrioritySpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets TIMER0_PRIORITY to value 0"]
impl crate::Resettable for Timer0PrioritySpec {}
}
#[doc = "TIMER1_PRIORITY (rw) register accessor: Acting priority of interrupt TIMER1\n\nYou can [`read`](crate::Reg::read) this register and get [`timer1_priority::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer1_priority::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timer1_priority`] module"]
#[doc(alias = "TIMER1_PRIORITY")]
pub type Timer1Priority = crate::Reg<timer1_priority::Timer1PrioritySpec>;
#[doc = "Acting priority of interrupt TIMER1"]
pub mod timer1_priority {
#[doc = "Register `TIMER1_PRIORITY` reader"]
pub type R = crate::R<Timer1PrioritySpec>;
#[doc = "Register `TIMER1_PRIORITY` writer"]
pub type W = crate::W<Timer1PrioritySpec>;
#[doc = "Field `TIMER1_PRIORITY` reader - Acting priority of interrupt TIMER1"]
pub type Timer1PriorityR = crate::FieldReader;
#[doc = "Field `TIMER1_PRIORITY` writer - Acting priority of interrupt TIMER1"]
pub type Timer1PriorityW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
impl R {
#[doc = "Bits 0:3 - Acting priority of interrupt TIMER1"]
#[inline(always)]
pub fn timer1_priority(&self) -> Timer1PriorityR {
Timer1PriorityR::new((self.bits & 0x0f) as u8)
}
}
impl W {
#[doc = "Bits 0:3 - Acting priority of interrupt TIMER1"]
#[inline(always)]
pub fn timer1_priority(&mut self) -> Timer1PriorityW<Timer1PrioritySpec> {
Timer1PriorityW::new(self, 0)
}
}
#[doc = "Acting priority of interrupt TIMER1\n\nYou can [`read`](crate::Reg::read) this register and get [`timer1_priority::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer1_priority::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Timer1PrioritySpec;
impl crate::RegisterSpec for Timer1PrioritySpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`timer1_priority::R`](R) reader structure"]
impl crate::Readable for Timer1PrioritySpec {}
#[doc = "`write(|w| ..)` method takes [`timer1_priority::W`](W) writer structure"]
impl crate::Writable for Timer1PrioritySpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets TIMER1_PRIORITY to value 0"]
impl crate::Resettable for Timer1PrioritySpec {}
}
#[doc = "GPTIMER0_PRIORITY (rw) register accessor: Acting priority of interrupt GPTIMER0\n\nYou can [`read`](crate::Reg::read) this register and get [`gptimer0_priority::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gptimer0_priority::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gptimer0_priority`] module"]
#[doc(alias = "GPTIMER0_PRIORITY")]
pub type Gptimer0Priority = crate::Reg<gptimer0_priority::Gptimer0PrioritySpec>;
#[doc = "Acting priority of interrupt GPTIMER0"]
pub mod gptimer0_priority {
#[doc = "Register `GPTIMER0_PRIORITY` reader"]
pub type R = crate::R<Gptimer0PrioritySpec>;
#[doc = "Register `GPTIMER0_PRIORITY` writer"]
pub type W = crate::W<Gptimer0PrioritySpec>;
#[doc = "Field `GPTIMER0_PRIORITY` reader - Acting priority of interrupt GPTIMER0"]
pub type Gptimer0PriorityR = crate::FieldReader;
#[doc = "Field `GPTIMER0_PRIORITY` writer - Acting priority of interrupt GPTIMER0"]
pub type Gptimer0PriorityW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
impl R {
#[doc = "Bits 0:3 - Acting priority of interrupt GPTIMER0"]
#[inline(always)]
pub fn gptimer0_priority(&self) -> Gptimer0PriorityR {
Gptimer0PriorityR::new((self.bits & 0x0f) as u8)
}
}
impl W {
#[doc = "Bits 0:3 - Acting priority of interrupt GPTIMER0"]
#[inline(always)]
pub fn gptimer0_priority(&mut self) -> Gptimer0PriorityW<Gptimer0PrioritySpec> {
Gptimer0PriorityW::new(self, 0)
}
}
#[doc = "Acting priority of interrupt GPTIMER0\n\nYou can [`read`](crate::Reg::read) this register and get [`gptimer0_priority::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gptimer0_priority::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Gptimer0PrioritySpec;
impl crate::RegisterSpec for Gptimer0PrioritySpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`gptimer0_priority::R`](R) reader structure"]
impl crate::Readable for Gptimer0PrioritySpec {}
#[doc = "`write(|w| ..)` method takes [`gptimer0_priority::W`](W) writer structure"]
impl crate::Writable for Gptimer0PrioritySpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets GPTIMER0_PRIORITY to value 0"]
impl crate::Resettable for Gptimer0PrioritySpec {}
}
#[doc = "GPTIMER1_PRIORITY (rw) register accessor: Acting priority of interrupt GPTIMER1\n\nYou can [`read`](crate::Reg::read) this register and get [`gptimer1_priority::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gptimer1_priority::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gptimer1_priority`] module"]
#[doc(alias = "GPTIMER1_PRIORITY")]
pub type Gptimer1Priority = crate::Reg<gptimer1_priority::Gptimer1PrioritySpec>;
#[doc = "Acting priority of interrupt GPTIMER1"]
pub mod gptimer1_priority {
#[doc = "Register `GPTIMER1_PRIORITY` reader"]
pub type R = crate::R<Gptimer1PrioritySpec>;
#[doc = "Register `GPTIMER1_PRIORITY` writer"]
pub type W = crate::W<Gptimer1PrioritySpec>;
#[doc = "Field `GPTIMER1_PRIORITY` reader - Acting priority of interrupt GPTIMER1"]
pub type Gptimer1PriorityR = crate::FieldReader;
#[doc = "Field `GPTIMER1_PRIORITY` writer - Acting priority of interrupt GPTIMER1"]
pub type Gptimer1PriorityW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
impl R {
#[doc = "Bits 0:3 - Acting priority of interrupt GPTIMER1"]
#[inline(always)]
pub fn gptimer1_priority(&self) -> Gptimer1PriorityR {
Gptimer1PriorityR::new((self.bits & 0x0f) as u8)
}
}
impl W {
#[doc = "Bits 0:3 - Acting priority of interrupt GPTIMER1"]
#[inline(always)]
pub fn gptimer1_priority(&mut self) -> Gptimer1PriorityW<Gptimer1PrioritySpec> {
Gptimer1PriorityW::new(self, 0)
}
}
#[doc = "Acting priority of interrupt GPTIMER1\n\nYou can [`read`](crate::Reg::read) this register and get [`gptimer1_priority::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gptimer1_priority::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Gptimer1PrioritySpec;
impl crate::RegisterSpec for Gptimer1PrioritySpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`gptimer1_priority::R`](R) reader structure"]
impl crate::Readable for Gptimer1PrioritySpec {}
#[doc = "`write(|w| ..)` method takes [`gptimer1_priority::W`](W) writer structure"]
impl crate::Writable for Gptimer1PrioritySpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets GPTIMER1_PRIORITY to value 0"]
impl crate::Resettable for Gptimer1PrioritySpec {}
}
#[doc = "GPTIMER2_PRIORITY (rw) register accessor: Acting priority of interrupt GPTIMER2\n\nYou can [`read`](crate::Reg::read) this register and get [`gptimer2_priority::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gptimer2_priority::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gptimer2_priority`] module"]
#[doc(alias = "GPTIMER2_PRIORITY")]
pub type Gptimer2Priority = crate::Reg<gptimer2_priority::Gptimer2PrioritySpec>;
#[doc = "Acting priority of interrupt GPTIMER2"]
pub mod gptimer2_priority {
#[doc = "Register `GPTIMER2_PRIORITY` reader"]
pub type R = crate::R<Gptimer2PrioritySpec>;
#[doc = "Register `GPTIMER2_PRIORITY` writer"]
pub type W = crate::W<Gptimer2PrioritySpec>;
#[doc = "Field `GPTIMER2_PRIORITY` reader - Acting priority of interrupt GPTIMER2"]
pub type Gptimer2PriorityR = crate::FieldReader;
#[doc = "Field `GPTIMER2_PRIORITY` writer - Acting priority of interrupt GPTIMER2"]
pub type Gptimer2PriorityW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
impl R {
#[doc = "Bits 0:3 - Acting priority of interrupt GPTIMER2"]
#[inline(always)]
pub fn gptimer2_priority(&self) -> Gptimer2PriorityR {
Gptimer2PriorityR::new((self.bits & 0x0f) as u8)
}
}
impl W {
#[doc = "Bits 0:3 - Acting priority of interrupt GPTIMER2"]
#[inline(always)]
pub fn gptimer2_priority(&mut self) -> Gptimer2PriorityW<Gptimer2PrioritySpec> {
Gptimer2PriorityW::new(self, 0)
}
}
#[doc = "Acting priority of interrupt GPTIMER2\n\nYou can [`read`](crate::Reg::read) this register and get [`gptimer2_priority::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gptimer2_priority::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Gptimer2PrioritySpec;
impl crate::RegisterSpec for Gptimer2PrioritySpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`gptimer2_priority::R`](R) reader structure"]
impl crate::Readable for Gptimer2PrioritySpec {}
#[doc = "`write(|w| ..)` method takes [`gptimer2_priority::W`](W) writer structure"]
impl crate::Writable for Gptimer2PrioritySpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets GPTIMER2_PRIORITY to value 0"]
impl crate::Resettable for Gptimer2PrioritySpec {}
}
#[doc = "GPTIMER3_PRIORITY (rw) register accessor: Acting priority of interrupt GPTIMER3\n\nYou can [`read`](crate::Reg::read) this register and get [`gptimer3_priority::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gptimer3_priority::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gptimer3_priority`] module"]
#[doc(alias = "GPTIMER3_PRIORITY")]
pub type Gptimer3Priority = crate::Reg<gptimer3_priority::Gptimer3PrioritySpec>;
#[doc = "Acting priority of interrupt GPTIMER3"]
pub mod gptimer3_priority {
#[doc = "Register `GPTIMER3_PRIORITY` reader"]
pub type R = crate::R<Gptimer3PrioritySpec>;
#[doc = "Register `GPTIMER3_PRIORITY` writer"]
pub type W = crate::W<Gptimer3PrioritySpec>;
#[doc = "Field `GPTIMER3_PRIORITY` reader - Acting priority of interrupt GPTIMER3"]
pub type Gptimer3PriorityR = crate::FieldReader;
#[doc = "Field `GPTIMER3_PRIORITY` writer - Acting priority of interrupt GPTIMER3"]
pub type Gptimer3PriorityW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
impl R {
#[doc = "Bits 0:3 - Acting priority of interrupt GPTIMER3"]
#[inline(always)]
pub fn gptimer3_priority(&self) -> Gptimer3PriorityR {
Gptimer3PriorityR::new((self.bits & 0x0f) as u8)
}
}
impl W {
#[doc = "Bits 0:3 - Acting priority of interrupt GPTIMER3"]
#[inline(always)]
pub fn gptimer3_priority(&mut self) -> Gptimer3PriorityW<Gptimer3PrioritySpec> {
Gptimer3PriorityW::new(self, 0)
}
}
#[doc = "Acting priority of interrupt GPTIMER3\n\nYou can [`read`](crate::Reg::read) this register and get [`gptimer3_priority::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gptimer3_priority::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Gptimer3PrioritySpec;
impl crate::RegisterSpec for Gptimer3PrioritySpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`gptimer3_priority::R`](R) reader structure"]
impl crate::Readable for Gptimer3PrioritySpec {}
#[doc = "`write(|w| ..)` method takes [`gptimer3_priority::W`](W) writer structure"]
impl crate::Writable for Gptimer3PrioritySpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets GPTIMER3_PRIORITY to value 0"]
impl crate::Resettable for Gptimer3PrioritySpec {}
}
#[doc = "GPTIMER4_PRIORITY (rw) register accessor: Acting priority of interrupt GPTIMER4\n\nYou can [`read`](crate::Reg::read) this register and get [`gptimer4_priority::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gptimer4_priority::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gptimer4_priority`] module"]
#[doc(alias = "GPTIMER4_PRIORITY")]
pub type Gptimer4Priority = crate::Reg<gptimer4_priority::Gptimer4PrioritySpec>;
#[doc = "Acting priority of interrupt GPTIMER4"]
pub mod gptimer4_priority {
#[doc = "Register `GPTIMER4_PRIORITY` reader"]
pub type R = crate::R<Gptimer4PrioritySpec>;
#[doc = "Register `GPTIMER4_PRIORITY` writer"]
pub type W = crate::W<Gptimer4PrioritySpec>;
#[doc = "Field `GPTIMER4_PRIORITY` reader - Acting priority of interrupt GPTIMER4"]
pub type Gptimer4PriorityR = crate::FieldReader;
#[doc = "Field `GPTIMER4_PRIORITY` writer - Acting priority of interrupt GPTIMER4"]
pub type Gptimer4PriorityW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
impl R {
#[doc = "Bits 0:3 - Acting priority of interrupt GPTIMER4"]
#[inline(always)]
pub fn gptimer4_priority(&self) -> Gptimer4PriorityR {
Gptimer4PriorityR::new((self.bits & 0x0f) as u8)
}
}
impl W {
#[doc = "Bits 0:3 - Acting priority of interrupt GPTIMER4"]
#[inline(always)]
pub fn gptimer4_priority(&mut self) -> Gptimer4PriorityW<Gptimer4PrioritySpec> {
Gptimer4PriorityW::new(self, 0)
}
}
#[doc = "Acting priority of interrupt GPTIMER4\n\nYou can [`read`](crate::Reg::read) this register and get [`gptimer4_priority::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gptimer4_priority::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Gptimer4PrioritySpec;
impl crate::RegisterSpec for Gptimer4PrioritySpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`gptimer4_priority::R`](R) reader structure"]
impl crate::Readable for Gptimer4PrioritySpec {}
#[doc = "`write(|w| ..)` method takes [`gptimer4_priority::W`](W) writer structure"]
impl crate::Writable for Gptimer4PrioritySpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets GPTIMER4_PRIORITY to value 0"]
impl crate::Resettable for Gptimer4PrioritySpec {}
}
#[doc = "UART0_PRIORITY (rw) register accessor: Acting priority of interrupt UART0\n\nYou can [`read`](crate::Reg::read) this register and get [`uart0_priority::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart0_priority::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart0_priority`] module"]
#[doc(alias = "UART0_PRIORITY")]
pub type Uart0Priority = crate::Reg<uart0_priority::Uart0PrioritySpec>;
#[doc = "Acting priority of interrupt UART0"]
pub mod uart0_priority {
#[doc = "Register `UART0_PRIORITY` reader"]
pub type R = crate::R<Uart0PrioritySpec>;
#[doc = "Register `UART0_PRIORITY` writer"]
pub type W = crate::W<Uart0PrioritySpec>;
#[doc = "Field `UART0_PRIORITY` reader - Acting priority of interrupt UART0"]
pub type Uart0PriorityR = crate::FieldReader;
#[doc = "Field `UART0_PRIORITY` writer - Acting priority of interrupt UART0"]
pub type Uart0PriorityW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
impl R {
#[doc = "Bits 0:3 - Acting priority of interrupt UART0"]
#[inline(always)]
pub fn uart0_priority(&self) -> Uart0PriorityR {
Uart0PriorityR::new((self.bits & 0x0f) as u8)
}
}
impl W {
#[doc = "Bits 0:3 - Acting priority of interrupt UART0"]
#[inline(always)]
pub fn uart0_priority(&mut self) -> Uart0PriorityW<Uart0PrioritySpec> {
Uart0PriorityW::new(self, 0)
}
}
#[doc = "Acting priority of interrupt UART0\n\nYou can [`read`](crate::Reg::read) this register and get [`uart0_priority::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart0_priority::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Uart0PrioritySpec;
impl crate::RegisterSpec for Uart0PrioritySpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`uart0_priority::R`](R) reader structure"]
impl crate::Readable for Uart0PrioritySpec {}
#[doc = "`write(|w| ..)` method takes [`uart0_priority::W`](W) writer structure"]
impl crate::Writable for Uart0PrioritySpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UART0_PRIORITY to value 0"]
impl crate::Resettable for Uart0PrioritySpec {}
}
#[doc = "UART1_PRIORITY (rw) register accessor: Acting priority of interrupt UART1\n\nYou can [`read`](crate::Reg::read) this register and get [`uart1_priority::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart1_priority::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart1_priority`] module"]
#[doc(alias = "UART1_PRIORITY")]
pub type Uart1Priority = crate::Reg<uart1_priority::Uart1PrioritySpec>;
#[doc = "Acting priority of interrupt UART1"]
pub mod uart1_priority {
#[doc = "Register `UART1_PRIORITY` reader"]
pub type R = crate::R<Uart1PrioritySpec>;
#[doc = "Register `UART1_PRIORITY` writer"]
pub type W = crate::W<Uart1PrioritySpec>;
#[doc = "Field `UART1_PRIORITY` reader - Acting priority of interrupt UART1"]
pub type Uart1PriorityR = crate::FieldReader;
#[doc = "Field `UART1_PRIORITY` writer - Acting priority of interrupt UART1"]
pub type Uart1PriorityW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
impl R {
#[doc = "Bits 0:3 - Acting priority of interrupt UART1"]
#[inline(always)]
pub fn uart1_priority(&self) -> Uart1PriorityR {
Uart1PriorityR::new((self.bits & 0x0f) as u8)
}
}
impl W {
#[doc = "Bits 0:3 - Acting priority of interrupt UART1"]
#[inline(always)]
pub fn uart1_priority(&mut self) -> Uart1PriorityW<Uart1PrioritySpec> {
Uart1PriorityW::new(self, 0)
}
}
#[doc = "Acting priority of interrupt UART1\n\nYou can [`read`](crate::Reg::read) this register and get [`uart1_priority::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart1_priority::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Uart1PrioritySpec;
impl crate::RegisterSpec for Uart1PrioritySpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`uart1_priority::R`](R) reader structure"]
impl crate::Readable for Uart1PrioritySpec {}
#[doc = "`write(|w| ..)` method takes [`uart1_priority::W`](W) writer structure"]
impl crate::Writable for Uart1PrioritySpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UART1_PRIORITY to value 0"]
impl crate::Resettable for Uart1PrioritySpec {}
}
#[doc = "UART2_PRIORITY (rw) register accessor: Acting priority of interrupt UART2\n\nYou can [`read`](crate::Reg::read) this register and get [`uart2_priority::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart2_priority::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart2_priority`] module"]
#[doc(alias = "UART2_PRIORITY")]
pub type Uart2Priority = crate::Reg<uart2_priority::Uart2PrioritySpec>;
#[doc = "Acting priority of interrupt UART2"]
pub mod uart2_priority {
#[doc = "Register `UART2_PRIORITY` reader"]
pub type R = crate::R<Uart2PrioritySpec>;
#[doc = "Register `UART2_PRIORITY` writer"]
pub type W = crate::W<Uart2PrioritySpec>;
#[doc = "Field `UART2_PRIORITY` reader - Acting priority of interrupt UART2"]
pub type Uart2PriorityR = crate::FieldReader;
#[doc = "Field `UART2_PRIORITY` writer - Acting priority of interrupt UART2"]
pub type Uart2PriorityW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
impl R {
#[doc = "Bits 0:3 - Acting priority of interrupt UART2"]
#[inline(always)]
pub fn uart2_priority(&self) -> Uart2PriorityR {
Uart2PriorityR::new((self.bits & 0x0f) as u8)
}
}
impl W {
#[doc = "Bits 0:3 - Acting priority of interrupt UART2"]
#[inline(always)]
pub fn uart2_priority(&mut self) -> Uart2PriorityW<Uart2PrioritySpec> {
Uart2PriorityW::new(self, 0)
}
}
#[doc = "Acting priority of interrupt UART2\n\nYou can [`read`](crate::Reg::read) this register and get [`uart2_priority::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart2_priority::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Uart2PrioritySpec;
impl crate::RegisterSpec for Uart2PrioritySpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`uart2_priority::R`](R) reader structure"]
impl crate::Readable for Uart2PrioritySpec {}
#[doc = "`write(|w| ..)` method takes [`uart2_priority::W`](W) writer structure"]
impl crate::Writable for Uart2PrioritySpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UART2_PRIORITY to value 0"]
impl crate::Resettable for Uart2PrioritySpec {}
}
#[doc = "UART3_PRIORITY (rw) register accessor: Acting priority of interrupt UART3\n\nYou can [`read`](crate::Reg::read) this register and get [`uart3_priority::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart3_priority::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart3_priority`] module"]
#[doc(alias = "UART3_PRIORITY")]
pub type Uart3Priority = crate::Reg<uart3_priority::Uart3PrioritySpec>;
#[doc = "Acting priority of interrupt UART3"]
pub mod uart3_priority {
#[doc = "Register `UART3_PRIORITY` reader"]
pub type R = crate::R<Uart3PrioritySpec>;
#[doc = "Register `UART3_PRIORITY` writer"]
pub type W = crate::W<Uart3PrioritySpec>;
#[doc = "Field `UART3_PRIORITY` reader - Acting priority of interrupt UART3"]
pub type Uart3PriorityR = crate::FieldReader;
#[doc = "Field `UART3_PRIORITY` writer - Acting priority of interrupt UART3"]
pub type Uart3PriorityW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
impl R {
#[doc = "Bits 0:3 - Acting priority of interrupt UART3"]
#[inline(always)]
pub fn uart3_priority(&self) -> Uart3PriorityR {
Uart3PriorityR::new((self.bits & 0x0f) as u8)
}
}
impl W {
#[doc = "Bits 0:3 - Acting priority of interrupt UART3"]
#[inline(always)]
pub fn uart3_priority(&mut self) -> Uart3PriorityW<Uart3PrioritySpec> {
Uart3PriorityW::new(self, 0)
}
}
#[doc = "Acting priority of interrupt UART3\n\nYou can [`read`](crate::Reg::read) this register and get [`uart3_priority::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart3_priority::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Uart3PrioritySpec;
impl crate::RegisterSpec for Uart3PrioritySpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`uart3_priority::R`](R) reader structure"]
impl crate::Readable for Uart3PrioritySpec {}
#[doc = "`write(|w| ..)` method takes [`uart3_priority::W`](W) writer structure"]
impl crate::Writable for Uart3PrioritySpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UART3_PRIORITY to value 0"]
impl crate::Resettable for Uart3PrioritySpec {}
}
#[doc = "UART4_PRIORITY (rw) register accessor: Acting priority of interrupt UART4\n\nYou can [`read`](crate::Reg::read) this register and get [`uart4_priority::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart4_priority::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart4_priority`] module"]
#[doc(alias = "UART4_PRIORITY")]
pub type Uart4Priority = crate::Reg<uart4_priority::Uart4PrioritySpec>;
#[doc = "Acting priority of interrupt UART4"]
pub mod uart4_priority {
#[doc = "Register `UART4_PRIORITY` reader"]
pub type R = crate::R<Uart4PrioritySpec>;
#[doc = "Register `UART4_PRIORITY` writer"]
pub type W = crate::W<Uart4PrioritySpec>;
#[doc = "Field `UART4_PRIORITY` reader - Acting priority of interrupt UART4"]
pub type Uart4PriorityR = crate::FieldReader;
#[doc = "Field `UART4_PRIORITY` writer - Acting priority of interrupt UART4"]
pub type Uart4PriorityW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
impl R {
#[doc = "Bits 0:3 - Acting priority of interrupt UART4"]
#[inline(always)]
pub fn uart4_priority(&self) -> Uart4PriorityR {
Uart4PriorityR::new((self.bits & 0x0f) as u8)
}
}
impl W {
#[doc = "Bits 0:3 - Acting priority of interrupt UART4"]
#[inline(always)]
pub fn uart4_priority(&mut self) -> Uart4PriorityW<Uart4PrioritySpec> {
Uart4PriorityW::new(self, 0)
}
}
#[doc = "Acting priority of interrupt UART4\n\nYou can [`read`](crate::Reg::read) this register and get [`uart4_priority::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart4_priority::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Uart4PrioritySpec;
impl crate::RegisterSpec for Uart4PrioritySpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`uart4_priority::R`](R) reader structure"]
impl crate::Readable for Uart4PrioritySpec {}
#[doc = "`write(|w| ..)` method takes [`uart4_priority::W`](W) writer structure"]
impl crate::Writable for Uart4PrioritySpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets UART4_PRIORITY to value 0"]
impl crate::Resettable for Uart4PrioritySpec {}
}
#[doc = "CAN0_PRIORITY (rw) register accessor: Acting priority of interrupt CAN0\n\nYou can [`read`](crate::Reg::read) this register and get [`can0_priority::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`can0_priority::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@can0_priority`] module"]
#[doc(alias = "CAN0_PRIORITY")]
pub type Can0Priority = crate::Reg<can0_priority::Can0PrioritySpec>;
#[doc = "Acting priority of interrupt CAN0"]
pub mod can0_priority {
#[doc = "Register `CAN0_PRIORITY` reader"]
pub type R = crate::R<Can0PrioritySpec>;
#[doc = "Register `CAN0_PRIORITY` writer"]
pub type W = crate::W<Can0PrioritySpec>;
#[doc = "Field `CAN0_PRIORITY` reader - Acting priority of interrupt CAN0"]
pub type Can0PriorityR = crate::FieldReader;
#[doc = "Field `CAN0_PRIORITY` writer - Acting priority of interrupt CAN0"]
pub type Can0PriorityW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
impl R {
#[doc = "Bits 0:3 - Acting priority of interrupt CAN0"]
#[inline(always)]
pub fn can0_priority(&self) -> Can0PriorityR {
Can0PriorityR::new((self.bits & 0x0f) as u8)
}
}
impl W {
#[doc = "Bits 0:3 - Acting priority of interrupt CAN0"]
#[inline(always)]
pub fn can0_priority(&mut self) -> Can0PriorityW<Can0PrioritySpec> {
Can0PriorityW::new(self, 0)
}
}
#[doc = "Acting priority of interrupt CAN0\n\nYou can [`read`](crate::Reg::read) this register and get [`can0_priority::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`can0_priority::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Can0PrioritySpec;
impl crate::RegisterSpec for Can0PrioritySpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`can0_priority::R`](R) reader structure"]
impl crate::Readable for Can0PrioritySpec {}
#[doc = "`write(|w| ..)` method takes [`can0_priority::W`](W) writer structure"]
impl crate::Writable for Can0PrioritySpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets CAN0_PRIORITY to value 0"]
impl crate::Resettable for Can0PrioritySpec {}
}
#[doc = "I2C0_PRIORITY (rw) register accessor: Acting priority of interrupt I2C0\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c0_priority::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c0_priority::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c0_priority`] module"]
#[doc(alias = "I2C0_PRIORITY")]
pub type I2c0Priority = crate::Reg<i2c0_priority::I2c0PrioritySpec>;
#[doc = "Acting priority of interrupt I2C0"]
pub mod i2c0_priority {
#[doc = "Register `I2C0_PRIORITY` reader"]
pub type R = crate::R<I2c0PrioritySpec>;
#[doc = "Register `I2C0_PRIORITY` writer"]
pub type W = crate::W<I2c0PrioritySpec>;
#[doc = "Field `I2C0_PRIORITY` reader - Acting priority of interrupt I2C0"]
pub type I2c0PriorityR = crate::FieldReader;
#[doc = "Field `I2C0_PRIORITY` writer - Acting priority of interrupt I2C0"]
pub type I2c0PriorityW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
impl R {
#[doc = "Bits 0:3 - Acting priority of interrupt I2C0"]
#[inline(always)]
pub fn i2c0_priority(&self) -> I2c0PriorityR {
I2c0PriorityR::new((self.bits & 0x0f) as u8)
}
}
impl W {
#[doc = "Bits 0:3 - Acting priority of interrupt I2C0"]
#[inline(always)]
pub fn i2c0_priority(&mut self) -> I2c0PriorityW<I2c0PrioritySpec> {
I2c0PriorityW::new(self, 0)
}
}
#[doc = "Acting priority of interrupt I2C0\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c0_priority::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c0_priority::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct I2c0PrioritySpec;
impl crate::RegisterSpec for I2c0PrioritySpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`i2c0_priority::R`](R) reader structure"]
impl crate::Readable for I2c0PrioritySpec {}
#[doc = "`write(|w| ..)` method takes [`i2c0_priority::W`](W) writer structure"]
impl crate::Writable for I2c0PrioritySpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets I2C0_PRIORITY to value 0"]
impl crate::Resettable for I2c0PrioritySpec {}
}
#[doc = "I2C1_PRIORITY (rw) register accessor: Acting priority of interrupt I2C1\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c1_priority::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c1_priority::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2c1_priority`] module"]
#[doc(alias = "I2C1_PRIORITY")]
pub type I2c1Priority = crate::Reg<i2c1_priority::I2c1PrioritySpec>;
#[doc = "Acting priority of interrupt I2C1"]
pub mod i2c1_priority {
#[doc = "Register `I2C1_PRIORITY` reader"]
pub type R = crate::R<I2c1PrioritySpec>;
#[doc = "Register `I2C1_PRIORITY` writer"]
pub type W = crate::W<I2c1PrioritySpec>;
#[doc = "Field `I2C1_PRIORITY` reader - Acting priority of interrupt I2C1"]
pub type I2c1PriorityR = crate::FieldReader;
#[doc = "Field `I2C1_PRIORITY` writer - Acting priority of interrupt I2C1"]
pub type I2c1PriorityW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
impl R {
#[doc = "Bits 0:3 - Acting priority of interrupt I2C1"]
#[inline(always)]
pub fn i2c1_priority(&self) -> I2c1PriorityR {
I2c1PriorityR::new((self.bits & 0x0f) as u8)
}
}
impl W {
#[doc = "Bits 0:3 - Acting priority of interrupt I2C1"]
#[inline(always)]
pub fn i2c1_priority(&mut self) -> I2c1PriorityW<I2c1PrioritySpec> {
I2c1PriorityW::new(self, 0)
}
}
#[doc = "Acting priority of interrupt I2C1\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c1_priority::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c1_priority::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct I2c1PrioritySpec;
impl crate::RegisterSpec for I2c1PrioritySpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`i2c1_priority::R`](R) reader structure"]
impl crate::Readable for I2c1PrioritySpec {}
#[doc = "`write(|w| ..)` method takes [`i2c1_priority::W`](W) writer structure"]
impl crate::Writable for I2c1PrioritySpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets I2C1_PRIORITY to value 0"]
impl crate::Resettable for I2c1PrioritySpec {}
}
#[doc = "DMAC0_INTR_PRIORITY (rw) register accessor: Acting priority of interrupt DMAC0_INTR\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac0_intr_priority::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac0_intr_priority::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmac0_intr_priority`] module"]
#[doc(alias = "DMAC0_INTR_PRIORITY")]
pub type Dmac0IntrPriority = crate::Reg<dmac0_intr_priority::Dmac0IntrPrioritySpec>;
#[doc = "Acting priority of interrupt DMAC0_INTR"]
pub mod dmac0_intr_priority {
#[doc = "Register `DMAC0_INTR_PRIORITY` reader"]
pub type R = crate::R<Dmac0IntrPrioritySpec>;
#[doc = "Register `DMAC0_INTR_PRIORITY` writer"]
pub type W = crate::W<Dmac0IntrPrioritySpec>;
#[doc = "Field `DMAC0_INTR_PRIORITY` reader - Acting priority of interrupt DMAC0_INTR"]
pub type Dmac0IntrPriorityR = crate::FieldReader;
#[doc = "Field `DMAC0_INTR_PRIORITY` writer - Acting priority of interrupt DMAC0_INTR"]
pub type Dmac0IntrPriorityW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
impl R {
#[doc = "Bits 0:3 - Acting priority of interrupt DMAC0_INTR"]
#[inline(always)]
pub fn dmac0_intr_priority(&self) -> Dmac0IntrPriorityR {
Dmac0IntrPriorityR::new((self.bits & 0x0f) as u8)
}
}
impl W {
#[doc = "Bits 0:3 - Acting priority of interrupt DMAC0_INTR"]
#[inline(always)]
pub fn dmac0_intr_priority(&mut self) -> Dmac0IntrPriorityW<Dmac0IntrPrioritySpec> {
Dmac0IntrPriorityW::new(self, 0)
}
}
#[doc = "Acting priority of interrupt DMAC0_INTR\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac0_intr_priority::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac0_intr_priority::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dmac0IntrPrioritySpec;
impl crate::RegisterSpec for Dmac0IntrPrioritySpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`dmac0_intr_priority::R`](R) reader structure"]
impl crate::Readable for Dmac0IntrPrioritySpec {}
#[doc = "`write(|w| ..)` method takes [`dmac0_intr_priority::W`](W) writer structure"]
impl crate::Writable for Dmac0IntrPrioritySpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets DMAC0_INTR_PRIORITY to value 0"]
impl crate::Resettable for Dmac0IntrPrioritySpec {}
}
#[doc = "DMAC0_INTTC_PRIORITY (rw) register accessor: Acting priority of interrupt DMAC0_INTTC\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac0_inttc_priority::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac0_inttc_priority::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmac0_inttc_priority`] module"]
#[doc(alias = "DMAC0_INTTC_PRIORITY")]
pub type Dmac0InttcPriority = crate::Reg<dmac0_inttc_priority::Dmac0InttcPrioritySpec>;
#[doc = "Acting priority of interrupt DMAC0_INTTC"]
pub mod dmac0_inttc_priority {
#[doc = "Register `DMAC0_INTTC_PRIORITY` reader"]
pub type R = crate::R<Dmac0InttcPrioritySpec>;
#[doc = "Register `DMAC0_INTTC_PRIORITY` writer"]
pub type W = crate::W<Dmac0InttcPrioritySpec>;
#[doc = "Field `DMAC0_INTTC_PRIORITY` reader - Acting priority of interrupt DMAC0_INTTC"]
pub type Dmac0InttcPriorityR = crate::FieldReader;
#[doc = "Field `DMAC0_INTTC_PRIORITY` writer - Acting priority of interrupt DMAC0_INTTC"]
pub type Dmac0InttcPriorityW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
impl R {
#[doc = "Bits 0:3 - Acting priority of interrupt DMAC0_INTTC"]
#[inline(always)]
pub fn dmac0_inttc_priority(&self) -> Dmac0InttcPriorityR {
Dmac0InttcPriorityR::new((self.bits & 0x0f) as u8)
}
}
impl W {
#[doc = "Bits 0:3 - Acting priority of interrupt DMAC0_INTTC"]
#[inline(always)]
pub fn dmac0_inttc_priority(&mut self) -> Dmac0InttcPriorityW<Dmac0InttcPrioritySpec> {
Dmac0InttcPriorityW::new(self, 0)
}
}
#[doc = "Acting priority of interrupt DMAC0_INTTC\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac0_inttc_priority::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac0_inttc_priority::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dmac0InttcPrioritySpec;
impl crate::RegisterSpec for Dmac0InttcPrioritySpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`dmac0_inttc_priority::R`](R) reader structure"]
impl crate::Readable for Dmac0InttcPrioritySpec {}
#[doc = "`write(|w| ..)` method takes [`dmac0_inttc_priority::W`](W) writer structure"]
impl crate::Writable for Dmac0InttcPrioritySpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets DMAC0_INTTC_PRIORITY to value 0"]
impl crate::Resettable for Dmac0InttcPrioritySpec {}
}
#[doc = "DMAC0_INTERR_PRIORITY (rw) register accessor: Acting priority of interrupt DMAC0_INTERR\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac0_interr_priority::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac0_interr_priority::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmac0_interr_priority`] module"]
#[doc(alias = "DMAC0_INTERR_PRIORITY")]
pub type Dmac0InterrPriority = crate::Reg<dmac0_interr_priority::Dmac0InterrPrioritySpec>;
#[doc = "Acting priority of interrupt DMAC0_INTERR"]
pub mod dmac0_interr_priority {
#[doc = "Register `DMAC0_INTERR_PRIORITY` reader"]
pub type R = crate::R<Dmac0InterrPrioritySpec>;
#[doc = "Register `DMAC0_INTERR_PRIORITY` writer"]
pub type W = crate::W<Dmac0InterrPrioritySpec>;
#[doc = "Field `DMAC0_INTERR_PRIORITY` reader - Acting priority of interrupt DMAC0_INTERR"]
pub type Dmac0InterrPriorityR = crate::FieldReader;
#[doc = "Field `DMAC0_INTERR_PRIORITY` writer - Acting priority of interrupt DMAC0_INTERR"]
pub type Dmac0InterrPriorityW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
impl R {
#[doc = "Bits 0:3 - Acting priority of interrupt DMAC0_INTERR"]
#[inline(always)]
pub fn dmac0_interr_priority(&self) -> Dmac0InterrPriorityR {
Dmac0InterrPriorityR::new((self.bits & 0x0f) as u8)
}
}
impl W {
#[doc = "Bits 0:3 - Acting priority of interrupt DMAC0_INTERR"]
#[inline(always)]
pub fn dmac0_interr_priority(
&mut self,
) -> Dmac0InterrPriorityW<Dmac0InterrPrioritySpec> {
Dmac0InterrPriorityW::new(self, 0)
}
}
#[doc = "Acting priority of interrupt DMAC0_INTERR\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac0_interr_priority::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac0_interr_priority::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dmac0InterrPrioritySpec;
impl crate::RegisterSpec for Dmac0InterrPrioritySpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`dmac0_interr_priority::R`](R) reader structure"]
impl crate::Readable for Dmac0InterrPrioritySpec {}
#[doc = "`write(|w| ..)` method takes [`dmac0_interr_priority::W`](W) writer structure"]
impl crate::Writable for Dmac0InterrPrioritySpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets DMAC0_INTERR_PRIORITY to value 0"]
impl crate::Resettable for Dmac0InterrPrioritySpec {}
}
#[doc = "USB0_PRIORITY (rw) register accessor: Acting priority of interrupt USB0\n\nYou can [`read`](crate::Reg::read) this register and get [`usb0_priority::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usb0_priority::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@usb0_priority`] module"]
#[doc(alias = "USB0_PRIORITY")]
pub type Usb0Priority = crate::Reg<usb0_priority::Usb0PrioritySpec>;
#[doc = "Acting priority of interrupt USB0"]
pub mod usb0_priority {
#[doc = "Register `USB0_PRIORITY` reader"]
pub type R = crate::R<Usb0PrioritySpec>;
#[doc = "Register `USB0_PRIORITY` writer"]
pub type W = crate::W<Usb0PrioritySpec>;
#[doc = "Field `USB0_PRIORITY` reader - Acting priority of interrupt USB0"]
pub type Usb0PriorityR = crate::FieldReader;
#[doc = "Field `USB0_PRIORITY` writer - Acting priority of interrupt USB0"]
pub type Usb0PriorityW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
impl R {
#[doc = "Bits 0:3 - Acting priority of interrupt USB0"]
#[inline(always)]
pub fn usb0_priority(&self) -> Usb0PriorityR {
Usb0PriorityR::new((self.bits & 0x0f) as u8)
}
}
impl W {
#[doc = "Bits 0:3 - Acting priority of interrupt USB0"]
#[inline(always)]
pub fn usb0_priority(&mut self) -> Usb0PriorityW<Usb0PrioritySpec> {
Usb0PriorityW::new(self, 0)
}
}
#[doc = "Acting priority of interrupt USB0\n\nYou can [`read`](crate::Reg::read) this register and get [`usb0_priority::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usb0_priority::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Usb0PrioritySpec;
impl crate::RegisterSpec for Usb0PrioritySpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`usb0_priority::R`](R) reader structure"]
impl crate::Readable for Usb0PrioritySpec {}
#[doc = "`write(|w| ..)` method takes [`usb0_priority::W`](W) writer structure"]
impl crate::Writable for Usb0PrioritySpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets USB0_PRIORITY to value 0"]
impl crate::Resettable for Usb0PrioritySpec {}
}
#[doc = "MAC0_PRIORITY (rw) register accessor: Acting priority of interrupt MAC0\n\nYou can [`read`](crate::Reg::read) this register and get [`mac0_priority::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mac0_priority::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mac0_priority`] module"]
#[doc(alias = "MAC0_PRIORITY")]
pub type Mac0Priority = crate::Reg<mac0_priority::Mac0PrioritySpec>;
#[doc = "Acting priority of interrupt MAC0"]
pub mod mac0_priority {
#[doc = "Register `MAC0_PRIORITY` reader"]
pub type R = crate::R<Mac0PrioritySpec>;
#[doc = "Register `MAC0_PRIORITY` writer"]
pub type W = crate::W<Mac0PrioritySpec>;
#[doc = "Field `MAC0_PRIORITY` reader - Acting priority of interrupt MAC0"]
pub type Mac0PriorityR = crate::FieldReader;
#[doc = "Field `MAC0_PRIORITY` writer - Acting priority of interrupt MAC0"]
pub type Mac0PriorityW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
impl R {
#[doc = "Bits 0:3 - Acting priority of interrupt MAC0"]
#[inline(always)]
pub fn mac0_priority(&self) -> Mac0PriorityR {
Mac0PriorityR::new((self.bits & 0x0f) as u8)
}
}
impl W {
#[doc = "Bits 0:3 - Acting priority of interrupt MAC0"]
#[inline(always)]
pub fn mac0_priority(&mut self) -> Mac0PriorityW<Mac0PrioritySpec> {
Mac0PriorityW::new(self, 0)
}
}
#[doc = "Acting priority of interrupt MAC0\n\nYou can [`read`](crate::Reg::read) this register and get [`mac0_priority::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mac0_priority::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Mac0PrioritySpec;
impl crate::RegisterSpec for Mac0PrioritySpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`mac0_priority::R`](R) reader structure"]
impl crate::Readable for Mac0PrioritySpec {}
#[doc = "`write(|w| ..)` method takes [`mac0_priority::W`](W) writer structure"]
impl crate::Writable for Mac0PrioritySpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets MAC0_PRIORITY to value 0"]
impl crate::Resettable for Mac0PrioritySpec {}
}
#[doc = "EXT_INT0_PRIORITY (rw) register accessor: Acting priority of interrupt EXT_INT0\n\nYou can [`read`](crate::Reg::read) this register and get [`ext_int0_priority::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ext_int0_priority::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ext_int0_priority`] module"]
#[doc(alias = "EXT_INT0_PRIORITY")]
pub type ExtInt0Priority = crate::Reg<ext_int0_priority::ExtInt0PrioritySpec>;
#[doc = "Acting priority of interrupt EXT_INT0"]
pub mod ext_int0_priority {
#[doc = "Register `EXT_INT0_PRIORITY` reader"]
pub type R = crate::R<ExtInt0PrioritySpec>;
#[doc = "Register `EXT_INT0_PRIORITY` writer"]
pub type W = crate::W<ExtInt0PrioritySpec>;
#[doc = "Field `EXT_INT0_PRIORITY` reader - Acting priority of interrupt EXT_INT0"]
pub type ExtInt0PriorityR = crate::FieldReader;
#[doc = "Field `EXT_INT0_PRIORITY` writer - Acting priority of interrupt EXT_INT0"]
pub type ExtInt0PriorityW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
impl R {
#[doc = "Bits 0:3 - Acting priority of interrupt EXT_INT0"]
#[inline(always)]
pub fn ext_int0_priority(&self) -> ExtInt0PriorityR {
ExtInt0PriorityR::new((self.bits & 0x0f) as u8)
}
}
impl W {
#[doc = "Bits 0:3 - Acting priority of interrupt EXT_INT0"]
#[inline(always)]
pub fn ext_int0_priority(&mut self) -> ExtInt0PriorityW<ExtInt0PrioritySpec> {
ExtInt0PriorityW::new(self, 0)
}
}
#[doc = "Acting priority of interrupt EXT_INT0\n\nYou can [`read`](crate::Reg::read) this register and get [`ext_int0_priority::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ext_int0_priority::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ExtInt0PrioritySpec;
impl crate::RegisterSpec for ExtInt0PrioritySpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ext_int0_priority::R`](R) reader structure"]
impl crate::Readable for ExtInt0PrioritySpec {}
#[doc = "`write(|w| ..)` method takes [`ext_int0_priority::W`](W) writer structure"]
impl crate::Writable for ExtInt0PrioritySpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets EXT_INT0_PRIORITY to value 0"]
impl crate::Resettable for ExtInt0PrioritySpec {}
}
#[doc = "EXT_INT1_PRIORITY (rw) register accessor: Acting priority of interrupt EXT_INT1\n\nYou can [`read`](crate::Reg::read) this register and get [`ext_int1_priority::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ext_int1_priority::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ext_int1_priority`] module"]
#[doc(alias = "EXT_INT1_PRIORITY")]
pub type ExtInt1Priority = crate::Reg<ext_int1_priority::ExtInt1PrioritySpec>;
#[doc = "Acting priority of interrupt EXT_INT1"]
pub mod ext_int1_priority {
#[doc = "Register `EXT_INT1_PRIORITY` reader"]
pub type R = crate::R<ExtInt1PrioritySpec>;
#[doc = "Register `EXT_INT1_PRIORITY` writer"]
pub type W = crate::W<ExtInt1PrioritySpec>;
#[doc = "Field `EXT_INT1_PRIORITY` reader - Acting priority of interrupt EXT_INT1"]
pub type ExtInt1PriorityR = crate::FieldReader;
#[doc = "Field `EXT_INT1_PRIORITY` writer - Acting priority of interrupt EXT_INT1"]
pub type ExtInt1PriorityW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
impl R {
#[doc = "Bits 0:3 - Acting priority of interrupt EXT_INT1"]
#[inline(always)]
pub fn ext_int1_priority(&self) -> ExtInt1PriorityR {
ExtInt1PriorityR::new((self.bits & 0x0f) as u8)
}
}
impl W {
#[doc = "Bits 0:3 - Acting priority of interrupt EXT_INT1"]
#[inline(always)]
pub fn ext_int1_priority(&mut self) -> ExtInt1PriorityW<ExtInt1PrioritySpec> {
ExtInt1PriorityW::new(self, 0)
}
}
#[doc = "Acting priority of interrupt EXT_INT1\n\nYou can [`read`](crate::Reg::read) this register and get [`ext_int1_priority::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ext_int1_priority::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ExtInt1PrioritySpec;
impl crate::RegisterSpec for ExtInt1PrioritySpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ext_int1_priority::R`](R) reader structure"]
impl crate::Readable for ExtInt1PrioritySpec {}
#[doc = "`write(|w| ..)` method takes [`ext_int1_priority::W`](W) writer structure"]
impl crate::Writable for ExtInt1PrioritySpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets EXT_INT1_PRIORITY to value 0"]
impl crate::Resettable for ExtInt1PrioritySpec {}
}
#[doc = "EXT_INT2_PRIORITY (rw) register accessor: Acting priority of interrupt EXT_INT2\n\nYou can [`read`](crate::Reg::read) this register and get [`ext_int2_priority::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ext_int2_priority::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ext_int2_priority`] module"]
#[doc(alias = "EXT_INT2_PRIORITY")]
pub type ExtInt2Priority = crate::Reg<ext_int2_priority::ExtInt2PrioritySpec>;
#[doc = "Acting priority of interrupt EXT_INT2"]
pub mod ext_int2_priority {
#[doc = "Register `EXT_INT2_PRIORITY` reader"]
pub type R = crate::R<ExtInt2PrioritySpec>;
#[doc = "Register `EXT_INT2_PRIORITY` writer"]
pub type W = crate::W<ExtInt2PrioritySpec>;
#[doc = "Field `EXT_INT2_PRIORITY` reader - Acting priority of interrupt EXT_INT2"]
pub type ExtInt2PriorityR = crate::FieldReader;
#[doc = "Field `EXT_INT2_PRIORITY` writer - Acting priority of interrupt EXT_INT2"]
pub type ExtInt2PriorityW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
impl R {
#[doc = "Bits 0:3 - Acting priority of interrupt EXT_INT2"]
#[inline(always)]
pub fn ext_int2_priority(&self) -> ExtInt2PriorityR {
ExtInt2PriorityR::new((self.bits & 0x0f) as u8)
}
}
impl W {
#[doc = "Bits 0:3 - Acting priority of interrupt EXT_INT2"]
#[inline(always)]
pub fn ext_int2_priority(&mut self) -> ExtInt2PriorityW<ExtInt2PrioritySpec> {
ExtInt2PriorityW::new(self, 0)
}
}
#[doc = "Acting priority of interrupt EXT_INT2\n\nYou can [`read`](crate::Reg::read) this register and get [`ext_int2_priority::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ext_int2_priority::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ExtInt2PrioritySpec;
impl crate::RegisterSpec for ExtInt2PrioritySpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ext_int2_priority::R`](R) reader structure"]
impl crate::Readable for ExtInt2PrioritySpec {}
#[doc = "`write(|w| ..)` method takes [`ext_int2_priority::W`](W) writer structure"]
impl crate::Writable for ExtInt2PrioritySpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets EXT_INT2_PRIORITY to value 0"]
impl crate::Resettable for ExtInt2PrioritySpec {}
}
#[doc = "EXT_INT3_PRIORITY (rw) register accessor: Acting priority of interrupt EXT_INT3\n\nYou can [`read`](crate::Reg::read) this register and get [`ext_int3_priority::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ext_int3_priority::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ext_int3_priority`] module"]
#[doc(alias = "EXT_INT3_PRIORITY")]
pub type ExtInt3Priority = crate::Reg<ext_int3_priority::ExtInt3PrioritySpec>;
#[doc = "Acting priority of interrupt EXT_INT3"]
pub mod ext_int3_priority {
#[doc = "Register `EXT_INT3_PRIORITY` reader"]
pub type R = crate::R<ExtInt3PrioritySpec>;
#[doc = "Register `EXT_INT3_PRIORITY` writer"]
pub type W = crate::W<ExtInt3PrioritySpec>;
#[doc = "Field `EXT_INT3_PRIORITY` reader - Acting priority of interrupt EXT_INT3"]
pub type ExtInt3PriorityR = crate::FieldReader;
#[doc = "Field `EXT_INT3_PRIORITY` writer - Acting priority of interrupt EXT_INT3"]
pub type ExtInt3PriorityW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
impl R {
#[doc = "Bits 0:3 - Acting priority of interrupt EXT_INT3"]
#[inline(always)]
pub fn ext_int3_priority(&self) -> ExtInt3PriorityR {
ExtInt3PriorityR::new((self.bits & 0x0f) as u8)
}
}
impl W {
#[doc = "Bits 0:3 - Acting priority of interrupt EXT_INT3"]
#[inline(always)]
pub fn ext_int3_priority(&mut self) -> ExtInt3PriorityW<ExtInt3PrioritySpec> {
ExtInt3PriorityW::new(self, 0)
}
}
#[doc = "Acting priority of interrupt EXT_INT3\n\nYou can [`read`](crate::Reg::read) this register and get [`ext_int3_priority::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ext_int3_priority::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ExtInt3PrioritySpec;
impl crate::RegisterSpec for ExtInt3PrioritySpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ext_int3_priority::R`](R) reader structure"]
impl crate::Readable for ExtInt3PrioritySpec {}
#[doc = "`write(|w| ..)` method takes [`ext_int3_priority::W`](W) writer structure"]
impl crate::Writable for ExtInt3PrioritySpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets EXT_INT3_PRIORITY to value 0"]
impl crate::Resettable for ExtInt3PrioritySpec {}
}
#[doc = "EXT_INT4_PRIORITY (rw) register accessor: Acting priority of interrupt EXT_INT4\n\nYou can [`read`](crate::Reg::read) this register and get [`ext_int4_priority::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ext_int4_priority::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ext_int4_priority`] module"]
#[doc(alias = "EXT_INT4_PRIORITY")]
pub type ExtInt4Priority = crate::Reg<ext_int4_priority::ExtInt4PrioritySpec>;
#[doc = "Acting priority of interrupt EXT_INT4"]
pub mod ext_int4_priority {
#[doc = "Register `EXT_INT4_PRIORITY` reader"]
pub type R = crate::R<ExtInt4PrioritySpec>;
#[doc = "Register `EXT_INT4_PRIORITY` writer"]
pub type W = crate::W<ExtInt4PrioritySpec>;
#[doc = "Field `EXT_INT4_PRIORITY` reader - Acting priority of interrupt EXT_INT4"]
pub type ExtInt4PriorityR = crate::FieldReader;
#[doc = "Field `EXT_INT4_PRIORITY` writer - Acting priority of interrupt EXT_INT4"]
pub type ExtInt4PriorityW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
impl R {
#[doc = "Bits 0:3 - Acting priority of interrupt EXT_INT4"]
#[inline(always)]
pub fn ext_int4_priority(&self) -> ExtInt4PriorityR {
ExtInt4PriorityR::new((self.bits & 0x0f) as u8)
}
}
impl W {
#[doc = "Bits 0:3 - Acting priority of interrupt EXT_INT4"]
#[inline(always)]
pub fn ext_int4_priority(&mut self) -> ExtInt4PriorityW<ExtInt4PrioritySpec> {
ExtInt4PriorityW::new(self, 0)
}
}
#[doc = "Acting priority of interrupt EXT_INT4\n\nYou can [`read`](crate::Reg::read) this register and get [`ext_int4_priority::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ext_int4_priority::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ExtInt4PrioritySpec;
impl crate::RegisterSpec for ExtInt4PrioritySpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ext_int4_priority::R`](R) reader structure"]
impl crate::Readable for ExtInt4PrioritySpec {}
#[doc = "`write(|w| ..)` method takes [`ext_int4_priority::W`](W) writer structure"]
impl crate::Writable for ExtInt4PrioritySpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets EXT_INT4_PRIORITY to value 0"]
impl crate::Resettable for ExtInt4PrioritySpec {}
}
#[doc = "EXT_INT5_PRIORITY (rw) register accessor: Acting priority of interrupt EXT_INT5\n\nYou can [`read`](crate::Reg::read) this register and get [`ext_int5_priority::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ext_int5_priority::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ext_int5_priority`] module"]
#[doc(alias = "EXT_INT5_PRIORITY")]
pub type ExtInt5Priority = crate::Reg<ext_int5_priority::ExtInt5PrioritySpec>;
#[doc = "Acting priority of interrupt EXT_INT5"]
pub mod ext_int5_priority {
#[doc = "Register `EXT_INT5_PRIORITY` reader"]
pub type R = crate::R<ExtInt5PrioritySpec>;
#[doc = "Register `EXT_INT5_PRIORITY` writer"]
pub type W = crate::W<ExtInt5PrioritySpec>;
#[doc = "Field `EXT_INT5_PRIORITY` reader - Acting priority of interrupt EXT_INT5"]
pub type ExtInt5PriorityR = crate::FieldReader;
#[doc = "Field `EXT_INT5_PRIORITY` writer - Acting priority of interrupt EXT_INT5"]
pub type ExtInt5PriorityW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
impl R {
#[doc = "Bits 0:3 - Acting priority of interrupt EXT_INT5"]
#[inline(always)]
pub fn ext_int5_priority(&self) -> ExtInt5PriorityR {
ExtInt5PriorityR::new((self.bits & 0x0f) as u8)
}
}
impl W {
#[doc = "Bits 0:3 - Acting priority of interrupt EXT_INT5"]
#[inline(always)]
pub fn ext_int5_priority(&mut self) -> ExtInt5PriorityW<ExtInt5PrioritySpec> {
ExtInt5PriorityW::new(self, 0)
}
}
#[doc = "Acting priority of interrupt EXT_INT5\n\nYou can [`read`](crate::Reg::read) this register and get [`ext_int5_priority::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ext_int5_priority::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ExtInt5PrioritySpec;
impl crate::RegisterSpec for ExtInt5PrioritySpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ext_int5_priority::R`](R) reader structure"]
impl crate::Readable for ExtInt5PrioritySpec {}
#[doc = "`write(|w| ..)` method takes [`ext_int5_priority::W`](W) writer structure"]
impl crate::Writable for ExtInt5PrioritySpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets EXT_INT5_PRIORITY to value 0"]
impl crate::Resettable for ExtInt5PrioritySpec {}
}
#[doc = "EXT_INT6_PRIORITY (rw) register accessor: Acting priority of interrupt EXT_INT6\n\nYou can [`read`](crate::Reg::read) this register and get [`ext_int6_priority::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ext_int6_priority::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ext_int6_priority`] module"]
#[doc(alias = "EXT_INT6_PRIORITY")]
pub type ExtInt6Priority = crate::Reg<ext_int6_priority::ExtInt6PrioritySpec>;
#[doc = "Acting priority of interrupt EXT_INT6"]
pub mod ext_int6_priority {
#[doc = "Register `EXT_INT6_PRIORITY` reader"]
pub type R = crate::R<ExtInt6PrioritySpec>;
#[doc = "Register `EXT_INT6_PRIORITY` writer"]
pub type W = crate::W<ExtInt6PrioritySpec>;
#[doc = "Field `EXT_INT6_PRIORITY` reader - Acting priority of interrupt EXT_INT6"]
pub type ExtInt6PriorityR = crate::FieldReader;
#[doc = "Field `EXT_INT6_PRIORITY` writer - Acting priority of interrupt EXT_INT6"]
pub type ExtInt6PriorityW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
impl R {
#[doc = "Bits 0:3 - Acting priority of interrupt EXT_INT6"]
#[inline(always)]
pub fn ext_int6_priority(&self) -> ExtInt6PriorityR {
ExtInt6PriorityR::new((self.bits & 0x0f) as u8)
}
}
impl W {
#[doc = "Bits 0:3 - Acting priority of interrupt EXT_INT6"]
#[inline(always)]
pub fn ext_int6_priority(&mut self) -> ExtInt6PriorityW<ExtInt6PrioritySpec> {
ExtInt6PriorityW::new(self, 0)
}
}
#[doc = "Acting priority of interrupt EXT_INT6\n\nYou can [`read`](crate::Reg::read) this register and get [`ext_int6_priority::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ext_int6_priority::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ExtInt6PrioritySpec;
impl crate::RegisterSpec for ExtInt6PrioritySpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ext_int6_priority::R`](R) reader structure"]
impl crate::Readable for ExtInt6PrioritySpec {}
#[doc = "`write(|w| ..)` method takes [`ext_int6_priority::W`](W) writer structure"]
impl crate::Writable for ExtInt6PrioritySpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets EXT_INT6_PRIORITY to value 0"]
impl crate::Resettable for ExtInt6PrioritySpec {}
}
#[doc = "EXT_INT7_PRIORITY (rw) register accessor: Acting priority of interrupt EXT_INT7\n\nYou can [`read`](crate::Reg::read) this register and get [`ext_int7_priority::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ext_int7_priority::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ext_int7_priority`] module"]
#[doc(alias = "EXT_INT7_PRIORITY")]
pub type ExtInt7Priority = crate::Reg<ext_int7_priority::ExtInt7PrioritySpec>;
#[doc = "Acting priority of interrupt EXT_INT7"]
pub mod ext_int7_priority {
#[doc = "Register `EXT_INT7_PRIORITY` reader"]
pub type R = crate::R<ExtInt7PrioritySpec>;
#[doc = "Register `EXT_INT7_PRIORITY` writer"]
pub type W = crate::W<ExtInt7PrioritySpec>;
#[doc = "Field `EXT_INT7_PRIORITY` reader - Acting priority of interrupt EXT_INT7"]
pub type ExtInt7PriorityR = crate::FieldReader;
#[doc = "Field `EXT_INT7_PRIORITY` writer - Acting priority of interrupt EXT_INT7"]
pub type ExtInt7PriorityW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
impl R {
#[doc = "Bits 0:3 - Acting priority of interrupt EXT_INT7"]
#[inline(always)]
pub fn ext_int7_priority(&self) -> ExtInt7PriorityR {
ExtInt7PriorityR::new((self.bits & 0x0f) as u8)
}
}
impl W {
#[doc = "Bits 0:3 - Acting priority of interrupt EXT_INT7"]
#[inline(always)]
pub fn ext_int7_priority(&mut self) -> ExtInt7PriorityW<ExtInt7PrioritySpec> {
ExtInt7PriorityW::new(self, 0)
}
}
#[doc = "Acting priority of interrupt EXT_INT7\n\nYou can [`read`](crate::Reg::read) this register and get [`ext_int7_priority::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ext_int7_priority::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ExtInt7PrioritySpec;
impl crate::RegisterSpec for ExtInt7PrioritySpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ext_int7_priority::R`](R) reader structure"]
impl crate::Readable for ExtInt7PrioritySpec {}
#[doc = "`write(|w| ..)` method takes [`ext_int7_priority::W`](W) writer structure"]
impl crate::Writable for ExtInt7PrioritySpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets EXT_INT7_PRIORITY to value 0"]
impl crate::Resettable for ExtInt7PrioritySpec {}
}
#[doc = "PENDING_0 (r) register accessor: Pending bit array\n\nYou can [`read`](crate::Reg::read) this register and get [`pending_0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pending_0`] module"]
#[doc(alias = "PENDING_0")]
pub type Pending0 = crate::Reg<pending_0::Pending0Spec>;
#[doc = "Pending bit array"]
pub mod pending_0 {
#[doc = "Register `PENDING_0` reader"]
pub type R = crate::R<Pending0Spec>;
#[doc = "Field `FLASH_PENDING` reader - Pending bit for interrupt FLASH"]
pub type FlashPendingR = crate::BitReader;
#[doc = "Field `RTC_PENDING` reader - Pending bit for interrupt RTC"]
pub type RtcPendingR = crate::BitReader;
#[doc = "Field `FCB0_PENDING` reader - Pending bit for interrupt FCB0"]
pub type Fcb0PendingR = crate::BitReader;
#[doc = "Field `WATCHDOG0_PENDING` reader - Pending bit for interrupt WATCHDOG0"]
pub type Watchdog0PendingR = crate::BitReader;
#[doc = "Field `SPI0_PENDING` reader - Pending bit for interrupt SPI0"]
pub type Spi0PendingR = crate::BitReader;
#[doc = "Field `SPI1_PENDING` reader - Pending bit for interrupt SPI1"]
pub type Spi1PendingR = crate::BitReader;
#[doc = "Field `GPIO0_PENDING` reader - Pending bit for interrupt GPIO0"]
pub type Gpio0PendingR = crate::BitReader;
#[doc = "Field `GPIO1_PENDING` reader - Pending bit for interrupt GPIO1"]
pub type Gpio1PendingR = crate::BitReader;
#[doc = "Field `GPIO2_PENDING` reader - Pending bit for interrupt GPIO2"]
pub type Gpio2PendingR = crate::BitReader;
#[doc = "Field `GPIO3_PENDING` reader - Pending bit for interrupt GPIO3"]
pub type Gpio3PendingR = crate::BitReader;
#[doc = "Field `GPIO4_PENDING` reader - Pending bit for interrupt GPIO4"]
pub type Gpio4PendingR = crate::BitReader;
#[doc = "Field `GPIO5_PENDING` reader - Pending bit for interrupt GPIO5"]
pub type Gpio5PendingR = crate::BitReader;
#[doc = "Field `GPIO6_PENDING` reader - Pending bit for interrupt GPIO6"]
pub type Gpio6PendingR = crate::BitReader;
#[doc = "Field `GPIO7_PENDING` reader - Pending bit for interrupt GPIO7"]
pub type Gpio7PendingR = crate::BitReader;
#[doc = "Field `GPIO8_PENDING` reader - Pending bit for interrupt GPIO8"]
pub type Gpio8PendingR = crate::BitReader;
#[doc = "Field `GPIO9_PENDING` reader - Pending bit for interrupt GPIO9"]
pub type Gpio9PendingR = crate::BitReader;
#[doc = "Field `TIMER0_PENDING` reader - Pending bit for interrupt TIMER0"]
pub type Timer0PendingR = crate::BitReader;
#[doc = "Field `TIMER1_PENDING` reader - Pending bit for interrupt TIMER1"]
pub type Timer1PendingR = crate::BitReader;
#[doc = "Field `GPTIMER0_PENDING` reader - Pending bit for interrupt GPTIMER0"]
pub type Gptimer0PendingR = crate::BitReader;
#[doc = "Field `GPTIMER1_PENDING` reader - Pending bit for interrupt GPTIMER1"]
pub type Gptimer1PendingR = crate::BitReader;
#[doc = "Field `GPTIMER2_PENDING` reader - Pending bit for interrupt GPTIMER2"]
pub type Gptimer2PendingR = crate::BitReader;
#[doc = "Field `GPTIMER3_PENDING` reader - Pending bit for interrupt GPTIMER3"]
pub type Gptimer3PendingR = crate::BitReader;
#[doc = "Field `GPTIMER4_PENDING` reader - Pending bit for interrupt GPTIMER4"]
pub type Gptimer4PendingR = crate::BitReader;
#[doc = "Field `UART0_PENDING` reader - Pending bit for interrupt UART0"]
pub type Uart0PendingR = crate::BitReader;
#[doc = "Field `UART1_PENDING` reader - Pending bit for interrupt UART1"]
pub type Uart1PendingR = crate::BitReader;
#[doc = "Field `UART2_PENDING` reader - Pending bit for interrupt UART2"]
pub type Uart2PendingR = crate::BitReader;
#[doc = "Field `UART3_PENDING` reader - Pending bit for interrupt UART3"]
pub type Uart3PendingR = crate::BitReader;
#[doc = "Field `UART4_PENDING` reader - Pending bit for interrupt UART4"]
pub type Uart4PendingR = crate::BitReader;
#[doc = "Field `CAN0_PENDING` reader - Pending bit for interrupt CAN0"]
pub type Can0PendingR = crate::BitReader;
#[doc = "Field `I2C0_PENDING` reader - Pending bit for interrupt I2C0"]
pub type I2c0PendingR = crate::BitReader;
#[doc = "Field `I2C1_PENDING` reader - Pending bit for interrupt I2C1"]
pub type I2c1PendingR = crate::BitReader;
impl R {
#[doc = "Bit 1 - Pending bit for interrupt FLASH"]
#[inline(always)]
pub fn flash_pending(&self) -> FlashPendingR {
FlashPendingR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Pending bit for interrupt RTC"]
#[inline(always)]
pub fn rtc_pending(&self) -> RtcPendingR {
RtcPendingR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Pending bit for interrupt FCB0"]
#[inline(always)]
pub fn fcb0_pending(&self) -> Fcb0PendingR {
Fcb0PendingR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Pending bit for interrupt WATCHDOG0"]
#[inline(always)]
pub fn watchdog0_pending(&self) -> Watchdog0PendingR {
Watchdog0PendingR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Pending bit for interrupt SPI0"]
#[inline(always)]
pub fn spi0_pending(&self) -> Spi0PendingR {
Spi0PendingR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Pending bit for interrupt SPI1"]
#[inline(always)]
pub fn spi1_pending(&self) -> Spi1PendingR {
Spi1PendingR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Pending bit for interrupt GPIO0"]
#[inline(always)]
pub fn gpio0_pending(&self) -> Gpio0PendingR {
Gpio0PendingR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - Pending bit for interrupt GPIO1"]
#[inline(always)]
pub fn gpio1_pending(&self) -> Gpio1PendingR {
Gpio1PendingR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - Pending bit for interrupt GPIO2"]
#[inline(always)]
pub fn gpio2_pending(&self) -> Gpio2PendingR {
Gpio2PendingR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - Pending bit for interrupt GPIO3"]
#[inline(always)]
pub fn gpio3_pending(&self) -> Gpio3PendingR {
Gpio3PendingR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - Pending bit for interrupt GPIO4"]
#[inline(always)]
pub fn gpio4_pending(&self) -> Gpio4PendingR {
Gpio4PendingR::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12 - Pending bit for interrupt GPIO5"]
#[inline(always)]
pub fn gpio5_pending(&self) -> Gpio5PendingR {
Gpio5PendingR::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13 - Pending bit for interrupt GPIO6"]
#[inline(always)]
pub fn gpio6_pending(&self) -> Gpio6PendingR {
Gpio6PendingR::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - Pending bit for interrupt GPIO7"]
#[inline(always)]
pub fn gpio7_pending(&self) -> Gpio7PendingR {
Gpio7PendingR::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15 - Pending bit for interrupt GPIO8"]
#[inline(always)]
pub fn gpio8_pending(&self) -> Gpio8PendingR {
Gpio8PendingR::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bit 16 - Pending bit for interrupt GPIO9"]
#[inline(always)]
pub fn gpio9_pending(&self) -> Gpio9PendingR {
Gpio9PendingR::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 17 - Pending bit for interrupt TIMER0"]
#[inline(always)]
pub fn timer0_pending(&self) -> Timer0PendingR {
Timer0PendingR::new(((self.bits >> 17) & 1) != 0)
}
#[doc = "Bit 18 - Pending bit for interrupt TIMER1"]
#[inline(always)]
pub fn timer1_pending(&self) -> Timer1PendingR {
Timer1PendingR::new(((self.bits >> 18) & 1) != 0)
}
#[doc = "Bit 19 - Pending bit for interrupt GPTIMER0"]
#[inline(always)]
pub fn gptimer0_pending(&self) -> Gptimer0PendingR {
Gptimer0PendingR::new(((self.bits >> 19) & 1) != 0)
}
#[doc = "Bit 20 - Pending bit for interrupt GPTIMER1"]
#[inline(always)]
pub fn gptimer1_pending(&self) -> Gptimer1PendingR {
Gptimer1PendingR::new(((self.bits >> 20) & 1) != 0)
}
#[doc = "Bit 21 - Pending bit for interrupt GPTIMER2"]
#[inline(always)]
pub fn gptimer2_pending(&self) -> Gptimer2PendingR {
Gptimer2PendingR::new(((self.bits >> 21) & 1) != 0)
}
#[doc = "Bit 22 - Pending bit for interrupt GPTIMER3"]
#[inline(always)]
pub fn gptimer3_pending(&self) -> Gptimer3PendingR {
Gptimer3PendingR::new(((self.bits >> 22) & 1) != 0)
}
#[doc = "Bit 23 - Pending bit for interrupt GPTIMER4"]
#[inline(always)]
pub fn gptimer4_pending(&self) -> Gptimer4PendingR {
Gptimer4PendingR::new(((self.bits >> 23) & 1) != 0)
}
#[doc = "Bit 24 - Pending bit for interrupt UART0"]
#[inline(always)]
pub fn uart0_pending(&self) -> Uart0PendingR {
Uart0PendingR::new(((self.bits >> 24) & 1) != 0)
}
#[doc = "Bit 25 - Pending bit for interrupt UART1"]
#[inline(always)]
pub fn uart1_pending(&self) -> Uart1PendingR {
Uart1PendingR::new(((self.bits >> 25) & 1) != 0)
}
#[doc = "Bit 26 - Pending bit for interrupt UART2"]
#[inline(always)]
pub fn uart2_pending(&self) -> Uart2PendingR {
Uart2PendingR::new(((self.bits >> 26) & 1) != 0)
}
#[doc = "Bit 27 - Pending bit for interrupt UART3"]
#[inline(always)]
pub fn uart3_pending(&self) -> Uart3PendingR {
Uart3PendingR::new(((self.bits >> 27) & 1) != 0)
}
#[doc = "Bit 28 - Pending bit for interrupt UART4"]
#[inline(always)]
pub fn uart4_pending(&self) -> Uart4PendingR {
Uart4PendingR::new(((self.bits >> 28) & 1) != 0)
}
#[doc = "Bit 29 - Pending bit for interrupt CAN0"]
#[inline(always)]
pub fn can0_pending(&self) -> Can0PendingR {
Can0PendingR::new(((self.bits >> 29) & 1) != 0)
}
#[doc = "Bit 30 - Pending bit for interrupt I2C0"]
#[inline(always)]
pub fn i2c0_pending(&self) -> I2c0PendingR {
I2c0PendingR::new(((self.bits >> 30) & 1) != 0)
}
#[doc = "Bit 31 - Pending bit for interrupt I2C1"]
#[inline(always)]
pub fn i2c1_pending(&self) -> I2c1PendingR {
I2c1PendingR::new(((self.bits >> 31) & 1) != 0)
}
}
#[doc = "Pending bit array\n\nYou can [`read`](crate::Reg::read) this register and get [`pending_0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Pending0Spec;
impl crate::RegisterSpec for Pending0Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`pending_0::R`](R) reader structure"]
impl crate::Readable for Pending0Spec {}
#[doc = "`reset()` method sets PENDING_0 to value 0"]
impl crate::Resettable for Pending0Spec {}
}
#[doc = "PENDING_1 (r) register accessor: Pending bit array\n\nYou can [`read`](crate::Reg::read) this register and get [`pending_1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pending_1`] module"]
#[doc(alias = "PENDING_1")]
pub type Pending1 = crate::Reg<pending_1::Pending1Spec>;
#[doc = "Pending bit array"]
pub mod pending_1 {
#[doc = "Register `PENDING_1` reader"]
pub type R = crate::R<Pending1Spec>;
#[doc = "Field `DMAC0_INTR_PENDING` reader - Pending bit for interrupt DMAC0_INTR"]
pub type Dmac0IntrPendingR = crate::BitReader;
#[doc = "Field `DMAC0_INTTC_PENDING` reader - Pending bit for interrupt DMAC0_INTTC"]
pub type Dmac0InttcPendingR = crate::BitReader;
#[doc = "Field `DMAC0_INTERR_PENDING` reader - Pending bit for interrupt DMAC0_INTERR"]
pub type Dmac0InterrPendingR = crate::BitReader;
#[doc = "Field `USB0_PENDING` reader - Pending bit for interrupt USB0"]
pub type Usb0PendingR = crate::BitReader;
#[doc = "Field `MAC0_PENDING` reader - Pending bit for interrupt MAC0"]
pub type Mac0PendingR = crate::BitReader;
#[doc = "Field `EXT_INT0_PENDING` reader - Pending bit for interrupt EXT_INT0"]
pub type ExtInt0PendingR = crate::BitReader;
#[doc = "Field `EXT_INT1_PENDING` reader - Pending bit for interrupt EXT_INT1"]
pub type ExtInt1PendingR = crate::BitReader;
#[doc = "Field `EXT_INT2_PENDING` reader - Pending bit for interrupt EXT_INT2"]
pub type ExtInt2PendingR = crate::BitReader;
#[doc = "Field `EXT_INT3_PENDING` reader - Pending bit for interrupt EXT_INT3"]
pub type ExtInt3PendingR = crate::BitReader;
#[doc = "Field `EXT_INT4_PENDING` reader - Pending bit for interrupt EXT_INT4"]
pub type ExtInt4PendingR = crate::BitReader;
#[doc = "Field `EXT_INT5_PENDING` reader - Pending bit for interrupt EXT_INT5"]
pub type ExtInt5PendingR = crate::BitReader;
#[doc = "Field `EXT_INT6_PENDING` reader - Pending bit for interrupt EXT_INT6"]
pub type ExtInt6PendingR = crate::BitReader;
#[doc = "Field `EXT_INT7_PENDING` reader - Pending bit for interrupt EXT_INT7"]
pub type ExtInt7PendingR = crate::BitReader;
impl R {
#[doc = "Bit 0 - Pending bit for interrupt DMAC0_INTR"]
#[inline(always)]
pub fn dmac0_intr_pending(&self) -> Dmac0IntrPendingR {
Dmac0IntrPendingR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Pending bit for interrupt DMAC0_INTTC"]
#[inline(always)]
pub fn dmac0_inttc_pending(&self) -> Dmac0InttcPendingR {
Dmac0InttcPendingR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Pending bit for interrupt DMAC0_INTERR"]
#[inline(always)]
pub fn dmac0_interr_pending(&self) -> Dmac0InterrPendingR {
Dmac0InterrPendingR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Pending bit for interrupt USB0"]
#[inline(always)]
pub fn usb0_pending(&self) -> Usb0PendingR {
Usb0PendingR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Pending bit for interrupt MAC0"]
#[inline(always)]
pub fn mac0_pending(&self) -> Mac0PendingR {
Mac0PendingR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Pending bit for interrupt EXT_INT0"]
#[inline(always)]
pub fn ext_int0_pending(&self) -> ExtInt0PendingR {
ExtInt0PendingR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Pending bit for interrupt EXT_INT1"]
#[inline(always)]
pub fn ext_int1_pending(&self) -> ExtInt1PendingR {
ExtInt1PendingR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Pending bit for interrupt EXT_INT2"]
#[inline(always)]
pub fn ext_int2_pending(&self) -> ExtInt2PendingR {
ExtInt2PendingR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - Pending bit for interrupt EXT_INT3"]
#[inline(always)]
pub fn ext_int3_pending(&self) -> ExtInt3PendingR {
ExtInt3PendingR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - Pending bit for interrupt EXT_INT4"]
#[inline(always)]
pub fn ext_int4_pending(&self) -> ExtInt4PendingR {
ExtInt4PendingR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - Pending bit for interrupt EXT_INT5"]
#[inline(always)]
pub fn ext_int5_pending(&self) -> ExtInt5PendingR {
ExtInt5PendingR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - Pending bit for interrupt EXT_INT6"]
#[inline(always)]
pub fn ext_int6_pending(&self) -> ExtInt6PendingR {
ExtInt6PendingR::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12 - Pending bit for interrupt EXT_INT7"]
#[inline(always)]
pub fn ext_int7_pending(&self) -> ExtInt7PendingR {
ExtInt7PendingR::new(((self.bits >> 12) & 1) != 0)
}
}
#[doc = "Pending bit array\n\nYou can [`read`](crate::Reg::read) this register and get [`pending_1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Pending1Spec;
impl crate::RegisterSpec for Pending1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`pending_1::R`](R) reader structure"]
impl crate::Readable for Pending1Spec {}
#[doc = "`reset()` method sets PENDING_1 to value 0"]
impl crate::Resettable for Pending1Spec {}
}
#[doc = "ENABLE_0 (rw) register accessor: Enable bits for each interrupt source for target 0. 1 bit for each interrupt source.\n\nYou can [`read`](crate::Reg::read) this register and get [`enable_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`enable_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_0`] module"]
#[doc(alias = "ENABLE_0")]
pub type Enable0 = crate::Reg<enable_0::Enable0Spec>;
#[doc = "Enable bits for each interrupt source for target 0. 1 bit for each interrupt source."]
pub mod enable_0 {
#[doc = "Register `ENABLE_0` reader"]
pub type R = crate::R<Enable0Spec>;
#[doc = "Register `ENABLE_0` writer"]
pub type W = crate::W<Enable0Spec>;
#[doc = "Field `FLASH_ENABLE` reader - Enable bit for interrupt FLASH"]
pub type FlashEnableR = crate::BitReader;
#[doc = "Field `FLASH_ENABLE` writer - Enable bit for interrupt FLASH"]
pub type FlashEnableW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RTC_ENABLE` reader - Enable bit for interrupt RTC"]
pub type RtcEnableR = crate::BitReader;
#[doc = "Field `RTC_ENABLE` writer - Enable bit for interrupt RTC"]
pub type RtcEnableW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `FCB0_ENABLE` reader - Enable bit for interrupt FCB0"]
pub type Fcb0EnableR = crate::BitReader;
#[doc = "Field `FCB0_ENABLE` writer - Enable bit for interrupt FCB0"]
pub type Fcb0EnableW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `WATCHDOG0_ENABLE` reader - Enable bit for interrupt WATCHDOG0"]
pub type Watchdog0EnableR = crate::BitReader;
#[doc = "Field `WATCHDOG0_ENABLE` writer - Enable bit for interrupt WATCHDOG0"]
pub type Watchdog0EnableW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SPI0_ENABLE` reader - Enable bit for interrupt SPI0"]
pub type Spi0EnableR = crate::BitReader;
#[doc = "Field `SPI0_ENABLE` writer - Enable bit for interrupt SPI0"]
pub type Spi0EnableW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SPI1_ENABLE` reader - Enable bit for interrupt SPI1"]
pub type Spi1EnableR = crate::BitReader;
#[doc = "Field `SPI1_ENABLE` writer - Enable bit for interrupt SPI1"]
pub type Spi1EnableW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `GPIO0_ENABLE` reader - Enable bit for interrupt GPIO0"]
pub type Gpio0EnableR = crate::BitReader;
#[doc = "Field `GPIO0_ENABLE` writer - Enable bit for interrupt GPIO0"]
pub type Gpio0EnableW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `GPIO1_ENABLE` reader - Enable bit for interrupt GPIO1"]
pub type Gpio1EnableR = crate::BitReader;
#[doc = "Field `GPIO1_ENABLE` writer - Enable bit for interrupt GPIO1"]
pub type Gpio1EnableW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `GPIO2_ENABLE` reader - Enable bit for interrupt GPIO2"]
pub type Gpio2EnableR = crate::BitReader;
#[doc = "Field `GPIO2_ENABLE` writer - Enable bit for interrupt GPIO2"]
pub type Gpio2EnableW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `GPIO3_ENABLE` reader - Enable bit for interrupt GPIO3"]
pub type Gpio3EnableR = crate::BitReader;
#[doc = "Field `GPIO3_ENABLE` writer - Enable bit for interrupt GPIO3"]
pub type Gpio3EnableW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `GPIO4_ENABLE` reader - Enable bit for interrupt GPIO4"]
pub type Gpio4EnableR = crate::BitReader;
#[doc = "Field `GPIO4_ENABLE` writer - Enable bit for interrupt GPIO4"]
pub type Gpio4EnableW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `GPIO5_ENABLE` reader - Enable bit for interrupt GPIO5"]
pub type Gpio5EnableR = crate::BitReader;
#[doc = "Field `GPIO5_ENABLE` writer - Enable bit for interrupt GPIO5"]
pub type Gpio5EnableW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `GPIO6_ENABLE` reader - Enable bit for interrupt GPIO6"]
pub type Gpio6EnableR = crate::BitReader;
#[doc = "Field `GPIO6_ENABLE` writer - Enable bit for interrupt GPIO6"]
pub type Gpio6EnableW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `GPIO7_ENABLE` reader - Enable bit for interrupt GPIO7"]
pub type Gpio7EnableR = crate::BitReader;
#[doc = "Field `GPIO7_ENABLE` writer - Enable bit for interrupt GPIO7"]
pub type Gpio7EnableW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `GPIO8_ENABLE` reader - Enable bit for interrupt GPIO8"]
pub type Gpio8EnableR = crate::BitReader;
#[doc = "Field `GPIO8_ENABLE` writer - Enable bit for interrupt GPIO8"]
pub type Gpio8EnableW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `GPIO9_ENABLE` reader - Enable bit for interrupt GPIO9"]
pub type Gpio9EnableR = crate::BitReader;
#[doc = "Field `GPIO9_ENABLE` writer - Enable bit for interrupt GPIO9"]
pub type Gpio9EnableW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TIMER0_ENABLE` reader - Enable bit for interrupt TIMER0"]
pub type Timer0EnableR = crate::BitReader;
#[doc = "Field `TIMER0_ENABLE` writer - Enable bit for interrupt TIMER0"]
pub type Timer0EnableW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TIMER1_ENABLE` reader - Enable bit for interrupt TIMER1"]
pub type Timer1EnableR = crate::BitReader;
#[doc = "Field `TIMER1_ENABLE` writer - Enable bit for interrupt TIMER1"]
pub type Timer1EnableW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `GPTIMER0_ENABLE` reader - Enable bit for interrupt GPTIMER0"]
pub type Gptimer0EnableR = crate::BitReader;
#[doc = "Field `GPTIMER0_ENABLE` writer - Enable bit for interrupt GPTIMER0"]
pub type Gptimer0EnableW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `GPTIMER1_ENABLE` reader - Enable bit for interrupt GPTIMER1"]
pub type Gptimer1EnableR = crate::BitReader;
#[doc = "Field `GPTIMER1_ENABLE` writer - Enable bit for interrupt GPTIMER1"]
pub type Gptimer1EnableW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `GPTIMER2_ENABLE` reader - Enable bit for interrupt GPTIMER2"]
pub type Gptimer2EnableR = crate::BitReader;
#[doc = "Field `GPTIMER2_ENABLE` writer - Enable bit for interrupt GPTIMER2"]
pub type Gptimer2EnableW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `GPTIMER3_ENABLE` reader - Enable bit for interrupt GPTIMER3"]
pub type Gptimer3EnableR = crate::BitReader;
#[doc = "Field `GPTIMER3_ENABLE` writer - Enable bit for interrupt GPTIMER3"]
pub type Gptimer3EnableW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `GPTIMER4_ENABLE` reader - Enable bit for interrupt GPTIMER4"]
pub type Gptimer4EnableR = crate::BitReader;
#[doc = "Field `GPTIMER4_ENABLE` writer - Enable bit for interrupt GPTIMER4"]
pub type Gptimer4EnableW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UART0_ENABLE` reader - Enable bit for interrupt UART0"]
pub type Uart0EnableR = crate::BitReader;
#[doc = "Field `UART0_ENABLE` writer - Enable bit for interrupt UART0"]
pub type Uart0EnableW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UART1_ENABLE` reader - Enable bit for interrupt UART1"]
pub type Uart1EnableR = crate::BitReader;
#[doc = "Field `UART1_ENABLE` writer - Enable bit for interrupt UART1"]
pub type Uart1EnableW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UART2_ENABLE` reader - Enable bit for interrupt UART2"]
pub type Uart2EnableR = crate::BitReader;
#[doc = "Field `UART2_ENABLE` writer - Enable bit for interrupt UART2"]
pub type Uart2EnableW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UART3_ENABLE` reader - Enable bit for interrupt UART3"]
pub type Uart3EnableR = crate::BitReader;
#[doc = "Field `UART3_ENABLE` writer - Enable bit for interrupt UART3"]
pub type Uart3EnableW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UART4_ENABLE` reader - Enable bit for interrupt UART4"]
pub type Uart4EnableR = crate::BitReader;
#[doc = "Field `UART4_ENABLE` writer - Enable bit for interrupt UART4"]
pub type Uart4EnableW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CAN0_ENABLE` reader - Enable bit for interrupt CAN0"]
pub type Can0EnableR = crate::BitReader;
#[doc = "Field `CAN0_ENABLE` writer - Enable bit for interrupt CAN0"]
pub type Can0EnableW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `I2C0_ENABLE` reader - Enable bit for interrupt I2C0"]
pub type I2c0EnableR = crate::BitReader;
#[doc = "Field `I2C0_ENABLE` writer - Enable bit for interrupt I2C0"]
pub type I2c0EnableW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `I2C1_ENABLE` reader - Enable bit for interrupt I2C1"]
pub type I2c1EnableR = crate::BitReader;
#[doc = "Field `I2C1_ENABLE` writer - Enable bit for interrupt I2C1"]
pub type I2c1EnableW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 1 - Enable bit for interrupt FLASH"]
#[inline(always)]
pub fn flash_enable(&self) -> FlashEnableR {
FlashEnableR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Enable bit for interrupt RTC"]
#[inline(always)]
pub fn rtc_enable(&self) -> RtcEnableR {
RtcEnableR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Enable bit for interrupt FCB0"]
#[inline(always)]
pub fn fcb0_enable(&self) -> Fcb0EnableR {
Fcb0EnableR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Enable bit for interrupt WATCHDOG0"]
#[inline(always)]
pub fn watchdog0_enable(&self) -> Watchdog0EnableR {
Watchdog0EnableR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Enable bit for interrupt SPI0"]
#[inline(always)]
pub fn spi0_enable(&self) -> Spi0EnableR {
Spi0EnableR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Enable bit for interrupt SPI1"]
#[inline(always)]
pub fn spi1_enable(&self) -> Spi1EnableR {
Spi1EnableR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Enable bit for interrupt GPIO0"]
#[inline(always)]
pub fn gpio0_enable(&self) -> Gpio0EnableR {
Gpio0EnableR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - Enable bit for interrupt GPIO1"]
#[inline(always)]
pub fn gpio1_enable(&self) -> Gpio1EnableR {
Gpio1EnableR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - Enable bit for interrupt GPIO2"]
#[inline(always)]
pub fn gpio2_enable(&self) -> Gpio2EnableR {
Gpio2EnableR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - Enable bit for interrupt GPIO3"]
#[inline(always)]
pub fn gpio3_enable(&self) -> Gpio3EnableR {
Gpio3EnableR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - Enable bit for interrupt GPIO4"]
#[inline(always)]
pub fn gpio4_enable(&self) -> Gpio4EnableR {
Gpio4EnableR::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12 - Enable bit for interrupt GPIO5"]
#[inline(always)]
pub fn gpio5_enable(&self) -> Gpio5EnableR {
Gpio5EnableR::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13 - Enable bit for interrupt GPIO6"]
#[inline(always)]
pub fn gpio6_enable(&self) -> Gpio6EnableR {
Gpio6EnableR::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - Enable bit for interrupt GPIO7"]
#[inline(always)]
pub fn gpio7_enable(&self) -> Gpio7EnableR {
Gpio7EnableR::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15 - Enable bit for interrupt GPIO8"]
#[inline(always)]
pub fn gpio8_enable(&self) -> Gpio8EnableR {
Gpio8EnableR::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bit 16 - Enable bit for interrupt GPIO9"]
#[inline(always)]
pub fn gpio9_enable(&self) -> Gpio9EnableR {
Gpio9EnableR::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 17 - Enable bit for interrupt TIMER0"]
#[inline(always)]
pub fn timer0_enable(&self) -> Timer0EnableR {
Timer0EnableR::new(((self.bits >> 17) & 1) != 0)
}
#[doc = "Bit 18 - Enable bit for interrupt TIMER1"]
#[inline(always)]
pub fn timer1_enable(&self) -> Timer1EnableR {
Timer1EnableR::new(((self.bits >> 18) & 1) != 0)
}
#[doc = "Bit 19 - Enable bit for interrupt GPTIMER0"]
#[inline(always)]
pub fn gptimer0_enable(&self) -> Gptimer0EnableR {
Gptimer0EnableR::new(((self.bits >> 19) & 1) != 0)
}
#[doc = "Bit 20 - Enable bit for interrupt GPTIMER1"]
#[inline(always)]
pub fn gptimer1_enable(&self) -> Gptimer1EnableR {
Gptimer1EnableR::new(((self.bits >> 20) & 1) != 0)
}
#[doc = "Bit 21 - Enable bit for interrupt GPTIMER2"]
#[inline(always)]
pub fn gptimer2_enable(&self) -> Gptimer2EnableR {
Gptimer2EnableR::new(((self.bits >> 21) & 1) != 0)
}
#[doc = "Bit 22 - Enable bit for interrupt GPTIMER3"]
#[inline(always)]
pub fn gptimer3_enable(&self) -> Gptimer3EnableR {
Gptimer3EnableR::new(((self.bits >> 22) & 1) != 0)
}
#[doc = "Bit 23 - Enable bit for interrupt GPTIMER4"]
#[inline(always)]
pub fn gptimer4_enable(&self) -> Gptimer4EnableR {
Gptimer4EnableR::new(((self.bits >> 23) & 1) != 0)
}
#[doc = "Bit 24 - Enable bit for interrupt UART0"]
#[inline(always)]
pub fn uart0_enable(&self) -> Uart0EnableR {
Uart0EnableR::new(((self.bits >> 24) & 1) != 0)
}
#[doc = "Bit 25 - Enable bit for interrupt UART1"]
#[inline(always)]
pub fn uart1_enable(&self) -> Uart1EnableR {
Uart1EnableR::new(((self.bits >> 25) & 1) != 0)
}
#[doc = "Bit 26 - Enable bit for interrupt UART2"]
#[inline(always)]
pub fn uart2_enable(&self) -> Uart2EnableR {
Uart2EnableR::new(((self.bits >> 26) & 1) != 0)
}
#[doc = "Bit 27 - Enable bit for interrupt UART3"]
#[inline(always)]
pub fn uart3_enable(&self) -> Uart3EnableR {
Uart3EnableR::new(((self.bits >> 27) & 1) != 0)
}
#[doc = "Bit 28 - Enable bit for interrupt UART4"]
#[inline(always)]
pub fn uart4_enable(&self) -> Uart4EnableR {
Uart4EnableR::new(((self.bits >> 28) & 1) != 0)
}
#[doc = "Bit 29 - Enable bit for interrupt CAN0"]
#[inline(always)]
pub fn can0_enable(&self) -> Can0EnableR {
Can0EnableR::new(((self.bits >> 29) & 1) != 0)
}
#[doc = "Bit 30 - Enable bit for interrupt I2C0"]
#[inline(always)]
pub fn i2c0_enable(&self) -> I2c0EnableR {
I2c0EnableR::new(((self.bits >> 30) & 1) != 0)
}
#[doc = "Bit 31 - Enable bit for interrupt I2C1"]
#[inline(always)]
pub fn i2c1_enable(&self) -> I2c1EnableR {
I2c1EnableR::new(((self.bits >> 31) & 1) != 0)
}
}
impl W {
#[doc = "Bit 1 - Enable bit for interrupt FLASH"]
#[inline(always)]
pub fn flash_enable(&mut self) -> FlashEnableW<Enable0Spec> {
FlashEnableW::new(self, 1)
}
#[doc = "Bit 2 - Enable bit for interrupt RTC"]
#[inline(always)]
pub fn rtc_enable(&mut self) -> RtcEnableW<Enable0Spec> {
RtcEnableW::new(self, 2)
}
#[doc = "Bit 3 - Enable bit for interrupt FCB0"]
#[inline(always)]
pub fn fcb0_enable(&mut self) -> Fcb0EnableW<Enable0Spec> {
Fcb0EnableW::new(self, 3)
}
#[doc = "Bit 4 - Enable bit for interrupt WATCHDOG0"]
#[inline(always)]
pub fn watchdog0_enable(&mut self) -> Watchdog0EnableW<Enable0Spec> {
Watchdog0EnableW::new(self, 4)
}
#[doc = "Bit 5 - Enable bit for interrupt SPI0"]
#[inline(always)]
pub fn spi0_enable(&mut self) -> Spi0EnableW<Enable0Spec> {
Spi0EnableW::new(self, 5)
}
#[doc = "Bit 6 - Enable bit for interrupt SPI1"]
#[inline(always)]
pub fn spi1_enable(&mut self) -> Spi1EnableW<Enable0Spec> {
Spi1EnableW::new(self, 6)
}
#[doc = "Bit 7 - Enable bit for interrupt GPIO0"]
#[inline(always)]
pub fn gpio0_enable(&mut self) -> Gpio0EnableW<Enable0Spec> {
Gpio0EnableW::new(self, 7)
}
#[doc = "Bit 8 - Enable bit for interrupt GPIO1"]
#[inline(always)]
pub fn gpio1_enable(&mut self) -> Gpio1EnableW<Enable0Spec> {
Gpio1EnableW::new(self, 8)
}
#[doc = "Bit 9 - Enable bit for interrupt GPIO2"]
#[inline(always)]
pub fn gpio2_enable(&mut self) -> Gpio2EnableW<Enable0Spec> {
Gpio2EnableW::new(self, 9)
}
#[doc = "Bit 10 - Enable bit for interrupt GPIO3"]
#[inline(always)]
pub fn gpio3_enable(&mut self) -> Gpio3EnableW<Enable0Spec> {
Gpio3EnableW::new(self, 10)
}
#[doc = "Bit 11 - Enable bit for interrupt GPIO4"]
#[inline(always)]
pub fn gpio4_enable(&mut self) -> Gpio4EnableW<Enable0Spec> {
Gpio4EnableW::new(self, 11)
}
#[doc = "Bit 12 - Enable bit for interrupt GPIO5"]
#[inline(always)]
pub fn gpio5_enable(&mut self) -> Gpio5EnableW<Enable0Spec> {
Gpio5EnableW::new(self, 12)
}
#[doc = "Bit 13 - Enable bit for interrupt GPIO6"]
#[inline(always)]
pub fn gpio6_enable(&mut self) -> Gpio6EnableW<Enable0Spec> {
Gpio6EnableW::new(self, 13)
}
#[doc = "Bit 14 - Enable bit for interrupt GPIO7"]
#[inline(always)]
pub fn gpio7_enable(&mut self) -> Gpio7EnableW<Enable0Spec> {
Gpio7EnableW::new(self, 14)
}
#[doc = "Bit 15 - Enable bit for interrupt GPIO8"]
#[inline(always)]
pub fn gpio8_enable(&mut self) -> Gpio8EnableW<Enable0Spec> {
Gpio8EnableW::new(self, 15)
}
#[doc = "Bit 16 - Enable bit for interrupt GPIO9"]
#[inline(always)]
pub fn gpio9_enable(&mut self) -> Gpio9EnableW<Enable0Spec> {
Gpio9EnableW::new(self, 16)
}
#[doc = "Bit 17 - Enable bit for interrupt TIMER0"]
#[inline(always)]
pub fn timer0_enable(&mut self) -> Timer0EnableW<Enable0Spec> {
Timer0EnableW::new(self, 17)
}
#[doc = "Bit 18 - Enable bit for interrupt TIMER1"]
#[inline(always)]
pub fn timer1_enable(&mut self) -> Timer1EnableW<Enable0Spec> {
Timer1EnableW::new(self, 18)
}
#[doc = "Bit 19 - Enable bit for interrupt GPTIMER0"]
#[inline(always)]
pub fn gptimer0_enable(&mut self) -> Gptimer0EnableW<Enable0Spec> {
Gptimer0EnableW::new(self, 19)
}
#[doc = "Bit 20 - Enable bit for interrupt GPTIMER1"]
#[inline(always)]
pub fn gptimer1_enable(&mut self) -> Gptimer1EnableW<Enable0Spec> {
Gptimer1EnableW::new(self, 20)
}
#[doc = "Bit 21 - Enable bit for interrupt GPTIMER2"]
#[inline(always)]
pub fn gptimer2_enable(&mut self) -> Gptimer2EnableW<Enable0Spec> {
Gptimer2EnableW::new(self, 21)
}
#[doc = "Bit 22 - Enable bit for interrupt GPTIMER3"]
#[inline(always)]
pub fn gptimer3_enable(&mut self) -> Gptimer3EnableW<Enable0Spec> {
Gptimer3EnableW::new(self, 22)
}
#[doc = "Bit 23 - Enable bit for interrupt GPTIMER4"]
#[inline(always)]
pub fn gptimer4_enable(&mut self) -> Gptimer4EnableW<Enable0Spec> {
Gptimer4EnableW::new(self, 23)
}
#[doc = "Bit 24 - Enable bit for interrupt UART0"]
#[inline(always)]
pub fn uart0_enable(&mut self) -> Uart0EnableW<Enable0Spec> {
Uart0EnableW::new(self, 24)
}
#[doc = "Bit 25 - Enable bit for interrupt UART1"]
#[inline(always)]
pub fn uart1_enable(&mut self) -> Uart1EnableW<Enable0Spec> {
Uart1EnableW::new(self, 25)
}
#[doc = "Bit 26 - Enable bit for interrupt UART2"]
#[inline(always)]
pub fn uart2_enable(&mut self) -> Uart2EnableW<Enable0Spec> {
Uart2EnableW::new(self, 26)
}
#[doc = "Bit 27 - Enable bit for interrupt UART3"]
#[inline(always)]
pub fn uart3_enable(&mut self) -> Uart3EnableW<Enable0Spec> {
Uart3EnableW::new(self, 27)
}
#[doc = "Bit 28 - Enable bit for interrupt UART4"]
#[inline(always)]
pub fn uart4_enable(&mut self) -> Uart4EnableW<Enable0Spec> {
Uart4EnableW::new(self, 28)
}
#[doc = "Bit 29 - Enable bit for interrupt CAN0"]
#[inline(always)]
pub fn can0_enable(&mut self) -> Can0EnableW<Enable0Spec> {
Can0EnableW::new(self, 29)
}
#[doc = "Bit 30 - Enable bit for interrupt I2C0"]
#[inline(always)]
pub fn i2c0_enable(&mut self) -> I2c0EnableW<Enable0Spec> {
I2c0EnableW::new(self, 30)
}
#[doc = "Bit 31 - Enable bit for interrupt I2C1"]
#[inline(always)]
pub fn i2c1_enable(&mut self) -> I2c1EnableW<Enable0Spec> {
I2c1EnableW::new(self, 31)
}
}
#[doc = "Enable bits for each interrupt source for target 0. 1 bit for each interrupt source.\n\nYou can [`read`](crate::Reg::read) this register and get [`enable_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`enable_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Enable0Spec;
impl crate::RegisterSpec for Enable0Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`enable_0::R`](R) reader structure"]
impl crate::Readable for Enable0Spec {}
#[doc = "`write(|w| ..)` method takes [`enable_0::W`](W) writer structure"]
impl crate::Writable for Enable0Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ENABLE_0 to value 0"]
impl crate::Resettable for Enable0Spec {}
}
#[doc = "ENABLE_4 (rw) register accessor: Enable bits for each interrupt source for target 0. 1 bit for each interrupt source.\n\nYou can [`read`](crate::Reg::read) this register and get [`enable_4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`enable_4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable_4`] module"]
#[doc(alias = "ENABLE_4")]
pub type Enable4 = crate::Reg<enable_4::Enable4Spec>;
#[doc = "Enable bits for each interrupt source for target 0. 1 bit for each interrupt source."]
pub mod enable_4 {
#[doc = "Register `ENABLE_4` reader"]
pub type R = crate::R<Enable4Spec>;
#[doc = "Register `ENABLE_4` writer"]
pub type W = crate::W<Enable4Spec>;
#[doc = "Field `DMAC0_INTR_ENABLE` reader - Enable bit for interrupt DMAC0_INTR"]
pub type Dmac0IntrEnableR = crate::BitReader;
#[doc = "Field `DMAC0_INTR_ENABLE` writer - Enable bit for interrupt DMAC0_INTR"]
pub type Dmac0IntrEnableW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DMAC0_INTTC_ENABLE` reader - Enable bit for interrupt DMAC0_INTTC"]
pub type Dmac0InttcEnableR = crate::BitReader;
#[doc = "Field `DMAC0_INTTC_ENABLE` writer - Enable bit for interrupt DMAC0_INTTC"]
pub type Dmac0InttcEnableW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DMAC0_INTERR_ENABLE` reader - Enable bit for interrupt DMAC0_INTERR"]
pub type Dmac0InterrEnableR = crate::BitReader;
#[doc = "Field `DMAC0_INTERR_ENABLE` writer - Enable bit for interrupt DMAC0_INTERR"]
pub type Dmac0InterrEnableW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `USB0_ENABLE` reader - Enable bit for interrupt USB0"]
pub type Usb0EnableR = crate::BitReader;
#[doc = "Field `USB0_ENABLE` writer - Enable bit for interrupt USB0"]
pub type Usb0EnableW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MAC0_ENABLE` reader - Enable bit for interrupt MAC0"]
pub type Mac0EnableR = crate::BitReader;
#[doc = "Field `MAC0_ENABLE` writer - Enable bit for interrupt MAC0"]
pub type Mac0EnableW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EXT_INT0_ENABLE` reader - Enable bit for interrupt EXT_INT0"]
pub type ExtInt0EnableR = crate::BitReader;
#[doc = "Field `EXT_INT0_ENABLE` writer - Enable bit for interrupt EXT_INT0"]
pub type ExtInt0EnableW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EXT_INT1_ENABLE` reader - Enable bit for interrupt EXT_INT1"]
pub type ExtInt1EnableR = crate::BitReader;
#[doc = "Field `EXT_INT1_ENABLE` writer - Enable bit for interrupt EXT_INT1"]
pub type ExtInt1EnableW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EXT_INT2_ENABLE` reader - Enable bit for interrupt EXT_INT2"]
pub type ExtInt2EnableR = crate::BitReader;
#[doc = "Field `EXT_INT2_ENABLE` writer - Enable bit for interrupt EXT_INT2"]
pub type ExtInt2EnableW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EXT_INT3_ENABLE` reader - Enable bit for interrupt EXT_INT3"]
pub type ExtInt3EnableR = crate::BitReader;
#[doc = "Field `EXT_INT3_ENABLE` writer - Enable bit for interrupt EXT_INT3"]
pub type ExtInt3EnableW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EXT_INT4_ENABLE` reader - Enable bit for interrupt EXT_INT4"]
pub type ExtInt4EnableR = crate::BitReader;
#[doc = "Field `EXT_INT4_ENABLE` writer - Enable bit for interrupt EXT_INT4"]
pub type ExtInt4EnableW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EXT_INT5_ENABLE` reader - Enable bit for interrupt EXT_INT5"]
pub type ExtInt5EnableR = crate::BitReader;
#[doc = "Field `EXT_INT5_ENABLE` writer - Enable bit for interrupt EXT_INT5"]
pub type ExtInt5EnableW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EXT_INT6_ENABLE` reader - Enable bit for interrupt EXT_INT6"]
pub type ExtInt6EnableR = crate::BitReader;
#[doc = "Field `EXT_INT6_ENABLE` writer - Enable bit for interrupt EXT_INT6"]
pub type ExtInt6EnableW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EXT_INT7_ENABLE` reader - Enable bit for interrupt EXT_INT7"]
pub type ExtInt7EnableR = crate::BitReader;
#[doc = "Field `EXT_INT7_ENABLE` writer - Enable bit for interrupt EXT_INT7"]
pub type ExtInt7EnableW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - Enable bit for interrupt DMAC0_INTR"]
#[inline(always)]
pub fn dmac0_intr_enable(&self) -> Dmac0IntrEnableR {
Dmac0IntrEnableR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Enable bit for interrupt DMAC0_INTTC"]
#[inline(always)]
pub fn dmac0_inttc_enable(&self) -> Dmac0InttcEnableR {
Dmac0InttcEnableR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Enable bit for interrupt DMAC0_INTERR"]
#[inline(always)]
pub fn dmac0_interr_enable(&self) -> Dmac0InterrEnableR {
Dmac0InterrEnableR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Enable bit for interrupt USB0"]
#[inline(always)]
pub fn usb0_enable(&self) -> Usb0EnableR {
Usb0EnableR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Enable bit for interrupt MAC0"]
#[inline(always)]
pub fn mac0_enable(&self) -> Mac0EnableR {
Mac0EnableR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Enable bit for interrupt EXT_INT0"]
#[inline(always)]
pub fn ext_int0_enable(&self) -> ExtInt0EnableR {
ExtInt0EnableR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Enable bit for interrupt EXT_INT1"]
#[inline(always)]
pub fn ext_int1_enable(&self) -> ExtInt1EnableR {
ExtInt1EnableR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Enable bit for interrupt EXT_INT2"]
#[inline(always)]
pub fn ext_int2_enable(&self) -> ExtInt2EnableR {
ExtInt2EnableR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - Enable bit for interrupt EXT_INT3"]
#[inline(always)]
pub fn ext_int3_enable(&self) -> ExtInt3EnableR {
ExtInt3EnableR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - Enable bit for interrupt EXT_INT4"]
#[inline(always)]
pub fn ext_int4_enable(&self) -> ExtInt4EnableR {
ExtInt4EnableR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - Enable bit for interrupt EXT_INT5"]
#[inline(always)]
pub fn ext_int5_enable(&self) -> ExtInt5EnableR {
ExtInt5EnableR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - Enable bit for interrupt EXT_INT6"]
#[inline(always)]
pub fn ext_int6_enable(&self) -> ExtInt6EnableR {
ExtInt6EnableR::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12 - Enable bit for interrupt EXT_INT7"]
#[inline(always)]
pub fn ext_int7_enable(&self) -> ExtInt7EnableR {
ExtInt7EnableR::new(((self.bits >> 12) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Enable bit for interrupt DMAC0_INTR"]
#[inline(always)]
pub fn dmac0_intr_enable(&mut self) -> Dmac0IntrEnableW<Enable4Spec> {
Dmac0IntrEnableW::new(self, 0)
}
#[doc = "Bit 1 - Enable bit for interrupt DMAC0_INTTC"]
#[inline(always)]
pub fn dmac0_inttc_enable(&mut self) -> Dmac0InttcEnableW<Enable4Spec> {
Dmac0InttcEnableW::new(self, 1)
}
#[doc = "Bit 2 - Enable bit for interrupt DMAC0_INTERR"]
#[inline(always)]
pub fn dmac0_interr_enable(&mut self) -> Dmac0InterrEnableW<Enable4Spec> {
Dmac0InterrEnableW::new(self, 2)
}
#[doc = "Bit 3 - Enable bit for interrupt USB0"]
#[inline(always)]
pub fn usb0_enable(&mut self) -> Usb0EnableW<Enable4Spec> {
Usb0EnableW::new(self, 3)
}
#[doc = "Bit 4 - Enable bit for interrupt MAC0"]
#[inline(always)]
pub fn mac0_enable(&mut self) -> Mac0EnableW<Enable4Spec> {
Mac0EnableW::new(self, 4)
}
#[doc = "Bit 5 - Enable bit for interrupt EXT_INT0"]
#[inline(always)]
pub fn ext_int0_enable(&mut self) -> ExtInt0EnableW<Enable4Spec> {
ExtInt0EnableW::new(self, 5)
}
#[doc = "Bit 6 - Enable bit for interrupt EXT_INT1"]
#[inline(always)]
pub fn ext_int1_enable(&mut self) -> ExtInt1EnableW<Enable4Spec> {
ExtInt1EnableW::new(self, 6)
}
#[doc = "Bit 7 - Enable bit for interrupt EXT_INT2"]
#[inline(always)]
pub fn ext_int2_enable(&mut self) -> ExtInt2EnableW<Enable4Spec> {
ExtInt2EnableW::new(self, 7)
}
#[doc = "Bit 8 - Enable bit for interrupt EXT_INT3"]
#[inline(always)]
pub fn ext_int3_enable(&mut self) -> ExtInt3EnableW<Enable4Spec> {
ExtInt3EnableW::new(self, 8)
}
#[doc = "Bit 9 - Enable bit for interrupt EXT_INT4"]
#[inline(always)]
pub fn ext_int4_enable(&mut self) -> ExtInt4EnableW<Enable4Spec> {
ExtInt4EnableW::new(self, 9)
}
#[doc = "Bit 10 - Enable bit for interrupt EXT_INT5"]
#[inline(always)]
pub fn ext_int5_enable(&mut self) -> ExtInt5EnableW<Enable4Spec> {
ExtInt5EnableW::new(self, 10)
}
#[doc = "Bit 11 - Enable bit for interrupt EXT_INT6"]
#[inline(always)]
pub fn ext_int6_enable(&mut self) -> ExtInt6EnableW<Enable4Spec> {
ExtInt6EnableW::new(self, 11)
}
#[doc = "Bit 12 - Enable bit for interrupt EXT_INT7"]
#[inline(always)]
pub fn ext_int7_enable(&mut self) -> ExtInt7EnableW<Enable4Spec> {
ExtInt7EnableW::new(self, 12)
}
}
#[doc = "Enable bits for each interrupt source for target 0. 1 bit for each interrupt source.\n\nYou can [`read`](crate::Reg::read) this register and get [`enable_4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`enable_4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Enable4Spec;
impl crate::RegisterSpec for Enable4Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`enable_4::R`](R) reader structure"]
impl crate::Readable for Enable4Spec {}
#[doc = "`write(|w| ..)` method takes [`enable_4::W`](W) writer structure"]
impl crate::Writable for Enable4Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ENABLE_4 to value 0"]
impl crate::Resettable for Enable4Spec {}
}
#[doc = "THRESHOLD_0 (rw) register accessor: Interrupt claim threshold for target 0. Maximum value is 15.\n\nYou can [`read`](crate::Reg::read) this register and get [`threshold_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`threshold_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@threshold_0`] module"]
#[doc(alias = "THRESHOLD_0")]
pub type Threshold0 = crate::Reg<threshold_0::Threshold0Spec>;
#[doc = "Interrupt claim threshold for target 0. Maximum value is 15."]
pub mod threshold_0 {
#[doc = "Register `THRESHOLD_0` reader"]
pub type R = crate::R<Threshold0Spec>;
#[doc = "Register `THRESHOLD_0` writer"]
pub type W = crate::W<Threshold0Spec>;
#[doc = "Field `THRESHOLD_0` reader - Interrupt claim threshold for target 0. Maximum value is 15."]
pub type Threshold0R = crate::FieldReader;
#[doc = "Field `THRESHOLD_0` writer - Interrupt claim threshold for target 0. Maximum value is 15."]
pub type Threshold0W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
impl R {
#[doc = "Bits 0:3 - Interrupt claim threshold for target 0. Maximum value is 15."]
#[inline(always)]
pub fn threshold_0(&self) -> Threshold0R {
Threshold0R::new((self.bits & 0x0f) as u8)
}
}
impl W {
#[doc = "Bits 0:3 - Interrupt claim threshold for target 0. Maximum value is 15."]
#[inline(always)]
pub fn threshold_0(&mut self) -> Threshold0W<Threshold0Spec> {
Threshold0W::new(self, 0)
}
}
#[doc = "Interrupt claim threshold for target 0. Maximum value is 15.\n\nYou can [`read`](crate::Reg::read) this register and get [`threshold_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`threshold_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Threshold0Spec;
impl crate::RegisterSpec for Threshold0Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`threshold_0::R`](R) reader structure"]
impl crate::Readable for Threshold0Spec {}
#[doc = "`write(|w| ..)` method takes [`threshold_0::W`](W) writer structure"]
impl crate::Writable for Threshold0Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets THRESHOLD_0 to value 0"]
impl crate::Resettable for Threshold0Spec {}
}
#[doc = "CLAIM_COMPLETE_0 (rw) register accessor: Claim/Complete register for Target 0. Reading this register returns the claimed interrupt number and makes it no longer pending.Writing the interrupt number back completes the interrupt.\n\nYou can [`read`](crate::Reg::read) this register and get [`claim_complete_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`claim_complete_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@claim_complete_0`] module"]
#[doc(alias = "CLAIM_COMPLETE_0")]
pub type ClaimComplete0 = crate::Reg<claim_complete_0::ClaimComplete0Spec>;
#[doc = "Claim/Complete register for Target 0. Reading this register returns the claimed interrupt number and makes it no longer pending.Writing the interrupt number back completes the interrupt."]
pub mod claim_complete_0 {
#[doc = "Register `CLAIM_COMPLETE_0` reader"]
pub type R = crate::R<ClaimComplete0Spec>;
#[doc = "Register `CLAIM_COMPLETE_0` writer"]
pub type W = crate::W<ClaimComplete0Spec>;
#[doc = "Field `CLAIM_COMPLETE_0` reader - Claim/Complete register for Target 0. Reading this register returns the claimed interrupt number and makes it no longer pending.Writing the interrupt number back completes the interrupt."]
pub type ClaimComplete0R = crate::FieldReader<u32>;
#[doc = "Field `CLAIM_COMPLETE_0` writer - Claim/Complete register for Target 0. Reading this register returns the claimed interrupt number and makes it no longer pending.Writing the interrupt number back completes the interrupt."]
pub type ClaimComplete0W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - Claim/Complete register for Target 0. Reading this register returns the claimed interrupt number and makes it no longer pending.Writing the interrupt number back completes the interrupt."]
#[inline(always)]
pub fn claim_complete_0(&self) -> ClaimComplete0R {
ClaimComplete0R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - Claim/Complete register for Target 0. Reading this register returns the claimed interrupt number and makes it no longer pending.Writing the interrupt number back completes the interrupt."]
#[inline(always)]
pub fn claim_complete_0(&mut self) -> ClaimComplete0W<ClaimComplete0Spec> {
ClaimComplete0W::new(self, 0)
}
}
#[doc = "Claim/Complete register for Target 0. Reading this register returns the claimed interrupt number and makes it no longer pending.Writing the interrupt number back completes the interrupt.\n\nYou can [`read`](crate::Reg::read) this register and get [`claim_complete_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`claim_complete_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ClaimComplete0Spec;
impl crate::RegisterSpec for ClaimComplete0Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`claim_complete_0::R`](R) reader structure"]
impl crate::Readable for ClaimComplete0Spec {}
#[doc = "`write(|w| ..)` method takes [`claim_complete_0::W`](W) writer structure"]
impl crate::Writable for ClaimComplete0Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets CLAIM_COMPLETE_0 to value 0"]
impl crate::Resettable for ClaimComplete0Spec {}
}
}
#[doc = "Real time clock"]
pub type Rtc = crate::Periph<rtc::RegisterBlock, 0x4000_0000>;
impl core::fmt::Debug for Rtc {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Rtc").finish()
}
}
#[doc = "Real time clock"]
pub mod rtc {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
rtc_crh: RtcCrh,
rtc_crl: RtcCrl,
rtc_prlh: RtcPrlh,
rtc_prll: RtcPrll,
rtc_divh: RtcDivh,
rtc_divl: RtcDivl,
rtc_cnth: RtcCnth,
rtc_cntl: RtcCntl,
rtc_alrh: RtcAlrh,
rtc_alrl: RtcAlrl,
rtc_rcyc: RtcRcyc,
_reserved11: [u8; 0x04],
rcc_bdcr: RccBdcr,
rcc_bdrst: RccBdrst,
iwdg_ctrl: IwdgCtrl,
_reserved14: [u8; 0x04],
bkp_rtccr: BkpRtccr,
bkp_dr0: BkpDr0,
bkp_dr1: BkpDr1,
bkp_dr2: BkpDr2,
bkp_dr3: BkpDr3,
bkp_dr4: BkpDr4,
bkp_dr5: BkpDr5,
bkp_dr6: BkpDr6,
bkp_dr7: BkpDr7,
bkp_dr8: BkpDr8,
bkp_dr9: BkpDr9,
bkp_dr10: BkpDr10,
bkp_dr11: BkpDr11,
bkp_dr12: BkpDr12,
bkp_dr13: BkpDr13,
bkp_dr14: BkpDr14,
bkp_dr15: BkpDr15,
}
impl RegisterBlock {
#[doc = "0x00 - RTC CRH"]
#[inline(always)]
pub const fn rtc_crh(&self) -> &RtcCrh {
&self.rtc_crh
}
#[doc = "0x04 - RTC CRL"]
#[inline(always)]
pub const fn rtc_crl(&self) -> &RtcCrl {
&self.rtc_crl
}
#[doc = "0x08 - RTC prescaler load register high"]
#[inline(always)]
pub const fn rtc_prlh(&self) -> &RtcPrlh {
&self.rtc_prlh
}
#[doc = "0x0c - RTC prescaler load register low"]
#[inline(always)]
pub const fn rtc_prll(&self) -> &RtcPrll {
&self.rtc_prll
}
#[doc = "0x10 - RTC prescaler divider register high"]
#[inline(always)]
pub const fn rtc_divh(&self) -> &RtcDivh {
&self.rtc_divh
}
#[doc = "0x14 - RTC prescaler divider register low"]
#[inline(always)]
pub const fn rtc_divl(&self) -> &RtcDivl {
&self.rtc_divl
}
#[doc = "0x18 - RTC counter register high"]
#[inline(always)]
pub const fn rtc_cnth(&self) -> &RtcCnth {
&self.rtc_cnth
}
#[doc = "0x1c - RTC counter register low"]
#[inline(always)]
pub const fn rtc_cntl(&self) -> &RtcCntl {
&self.rtc_cntl
}
#[doc = "0x20 - RTC alarm register high"]
#[inline(always)]
pub const fn rtc_alrh(&self) -> &RtcAlrh {
&self.rtc_alrh
}
#[doc = "0x24 - RTC alarm register low"]
#[inline(always)]
pub const fn rtc_alrl(&self) -> &RtcAlrl {
&self.rtc_alrl
}
#[doc = "0x28 - Read minimum cycle"]
#[inline(always)]
pub const fn rtc_rcyc(&self) -> &RtcRcyc {
&self.rtc_rcyc
}
#[doc = "0x30 - Backup domain control register"]
#[inline(always)]
pub const fn rcc_bdcr(&self) -> &RccBdcr {
&self.rcc_bdcr
}
#[doc = "0x32 - Backup domain software reset"]
#[inline(always)]
pub const fn rcc_bdrst(&self) -> &RccBdrst {
&self.rcc_bdrst
}
#[doc = "0x34 - Independent watchdog control"]
#[inline(always)]
pub const fn iwdg_ctrl(&self) -> &IwdgCtrl {
&self.iwdg_ctrl
}
#[doc = "0x3c - RTC clock calibration register"]
#[inline(always)]
pub const fn bkp_rtccr(&self) -> &BkpRtccr {
&self.bkp_rtccr
}
#[doc = "0x40 - Backup data register 0"]
#[inline(always)]
pub const fn bkp_dr0(&self) -> &BkpDr0 {
&self.bkp_dr0
}
#[doc = "0x44 - Backup data register 1"]
#[inline(always)]
pub const fn bkp_dr1(&self) -> &BkpDr1 {
&self.bkp_dr1
}
#[doc = "0x48 - Backup data register 2"]
#[inline(always)]
pub const fn bkp_dr2(&self) -> &BkpDr2 {
&self.bkp_dr2
}
#[doc = "0x4c - Backup data register 3"]
#[inline(always)]
pub const fn bkp_dr3(&self) -> &BkpDr3 {
&self.bkp_dr3
}
#[doc = "0x50 - Backup data register 4"]
#[inline(always)]
pub const fn bkp_dr4(&self) -> &BkpDr4 {
&self.bkp_dr4
}
#[doc = "0x54 - Backup data register 5"]
#[inline(always)]
pub const fn bkp_dr5(&self) -> &BkpDr5 {
&self.bkp_dr5
}
#[doc = "0x58 - Backup data register 6"]
#[inline(always)]
pub const fn bkp_dr6(&self) -> &BkpDr6 {
&self.bkp_dr6
}
#[doc = "0x5c - Backup data register 7"]
#[inline(always)]
pub const fn bkp_dr7(&self) -> &BkpDr7 {
&self.bkp_dr7
}
#[doc = "0x60 - Backup data register 8"]
#[inline(always)]
pub const fn bkp_dr8(&self) -> &BkpDr8 {
&self.bkp_dr8
}
#[doc = "0x64 - Backup data register 9"]
#[inline(always)]
pub const fn bkp_dr9(&self) -> &BkpDr9 {
&self.bkp_dr9
}
#[doc = "0x68 - Backup data register 10"]
#[inline(always)]
pub const fn bkp_dr10(&self) -> &BkpDr10 {
&self.bkp_dr10
}
#[doc = "0x6c - Backup data register 11"]
#[inline(always)]
pub const fn bkp_dr11(&self) -> &BkpDr11 {
&self.bkp_dr11
}
#[doc = "0x70 - Backup data register 12"]
#[inline(always)]
pub const fn bkp_dr12(&self) -> &BkpDr12 {
&self.bkp_dr12
}
#[doc = "0x74 - Backup data register 13"]
#[inline(always)]
pub const fn bkp_dr13(&self) -> &BkpDr13 {
&self.bkp_dr13
}
#[doc = "0x78 - Backup data register 14"]
#[inline(always)]
pub const fn bkp_dr14(&self) -> &BkpDr14 {
&self.bkp_dr14
}
#[doc = "0x7c - Backup data register 15"]
#[inline(always)]
pub const fn bkp_dr15(&self) -> &BkpDr15 {
&self.bkp_dr15
}
}
#[doc = "RTC_CRH (rw) register accessor: RTC CRH\n\nYou can [`read`](crate::Reg::read) this register and get [`rtc_crh::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtc_crh::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtc_crh`] module"]
#[doc(alias = "RTC_CRH")]
pub type RtcCrh = crate::Reg<rtc_crh::RtcCrhSpec>;
#[doc = "RTC CRH"]
pub mod rtc_crh {
#[doc = "Register `RTC_CRH` reader"]
pub type R = crate::R<RtcCrhSpec>;
#[doc = "Register `RTC_CRH` writer"]
pub type W = crate::W<RtcCrhSpec>;
#[doc = "Field `SECIE` reader - Second interrupt enable"]
pub type SecieR = crate::BitReader;
#[doc = "Field `SECIE` writer - Second interrupt enable"]
pub type SecieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ALRIE` reader - Alarm interrupt enable"]
pub type AlrieR = crate::BitReader;
#[doc = "Field `ALRIE` writer - Alarm interrupt enable"]
pub type AlrieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OWIE` reader - Overflow interrupt enable"]
pub type OwieR = crate::BitReader;
#[doc = "Field `OWIE` writer - Overflow interrupt enable"]
pub type OwieW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - Second interrupt enable"]
#[inline(always)]
pub fn secie(&self) -> SecieR {
SecieR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Alarm interrupt enable"]
#[inline(always)]
pub fn alrie(&self) -> AlrieR {
AlrieR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Overflow interrupt enable"]
#[inline(always)]
pub fn owie(&self) -> OwieR {
OwieR::new(((self.bits >> 2) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Second interrupt enable"]
#[inline(always)]
pub fn secie(&mut self) -> SecieW<RtcCrhSpec> {
SecieW::new(self, 0)
}
#[doc = "Bit 1 - Alarm interrupt enable"]
#[inline(always)]
pub fn alrie(&mut self) -> AlrieW<RtcCrhSpec> {
AlrieW::new(self, 1)
}
#[doc = "Bit 2 - Overflow interrupt enable"]
#[inline(always)]
pub fn owie(&mut self) -> OwieW<RtcCrhSpec> {
OwieW::new(self, 2)
}
}
#[doc = "RTC CRH\n\nYou can [`read`](crate::Reg::read) this register and get [`rtc_crh::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtc_crh::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RtcCrhSpec;
impl crate::RegisterSpec for RtcCrhSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rtc_crh::R`](R) reader structure"]
impl crate::Readable for RtcCrhSpec {}
#[doc = "`write(|w| ..)` method takes [`rtc_crh::W`](W) writer structure"]
impl crate::Writable for RtcCrhSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets RTC_CRH to value 0"]
impl crate::Resettable for RtcCrhSpec {}
}
#[doc = "RTC_CRL (rw) register accessor: RTC CRL\n\nYou can [`read`](crate::Reg::read) this register and get [`rtc_crl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtc_crl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtc_crl`] module"]
#[doc(alias = "RTC_CRL")]
pub type RtcCrl = crate::Reg<rtc_crl::RtcCrlSpec>;
#[doc = "RTC CRL"]
pub mod rtc_crl {
#[doc = "Register `RTC_CRL` reader"]
pub type R = crate::R<RtcCrlSpec>;
#[doc = "Register `RTC_CRL` writer"]
pub type W = crate::W<RtcCrlSpec>;
#[doc = "Field `SECF` reader - Second flag"]
pub type SecfR = crate::BitReader;
#[doc = "Field `SECF` writer - Second flag"]
pub type SecfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ALRF` reader - Alarm flag"]
pub type AlrfR = crate::BitReader;
#[doc = "Field `ALRF` writer - Alarm flag"]
pub type AlrfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OWF` reader - Overflow flag"]
pub type OwfR = crate::BitReader;
#[doc = "Field `OWF` writer - Overflow flag"]
pub type OwfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RSF` reader - Registers synchronized flag"]
pub type RsfR = crate::BitReader;
#[doc = "Field `RSF` writer - Registers synchronized flag"]
pub type RsfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CNF` reader - Configuration flag"]
pub type CnfR = crate::BitReader;
#[doc = "Field `CNF` writer - Configuration flag"]
pub type CnfW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RTOFF` reader - RTC operation OFF"]
pub type RtoffR = crate::BitReader;
impl R {
#[doc = "Bit 0 - Second flag"]
#[inline(always)]
pub fn secf(&self) -> SecfR {
SecfR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Alarm flag"]
#[inline(always)]
pub fn alrf(&self) -> AlrfR {
AlrfR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Overflow flag"]
#[inline(always)]
pub fn owf(&self) -> OwfR {
OwfR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Registers synchronized flag"]
#[inline(always)]
pub fn rsf(&self) -> RsfR {
RsfR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Configuration flag"]
#[inline(always)]
pub fn cnf(&self) -> CnfR {
CnfR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - RTC operation OFF"]
#[inline(always)]
pub fn rtoff(&self) -> RtoffR {
RtoffR::new(((self.bits >> 5) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Second flag"]
#[inline(always)]
pub fn secf(&mut self) -> SecfW<RtcCrlSpec> {
SecfW::new(self, 0)
}
#[doc = "Bit 1 - Alarm flag"]
#[inline(always)]
pub fn alrf(&mut self) -> AlrfW<RtcCrlSpec> {
AlrfW::new(self, 1)
}
#[doc = "Bit 2 - Overflow flag"]
#[inline(always)]
pub fn owf(&mut self) -> OwfW<RtcCrlSpec> {
OwfW::new(self, 2)
}
#[doc = "Bit 3 - Registers synchronized flag"]
#[inline(always)]
pub fn rsf(&mut self) -> RsfW<RtcCrlSpec> {
RsfW::new(self, 3)
}
#[doc = "Bit 4 - Configuration flag"]
#[inline(always)]
pub fn cnf(&mut self) -> CnfW<RtcCrlSpec> {
CnfW::new(self, 4)
}
}
#[doc = "RTC CRL\n\nYou can [`read`](crate::Reg::read) this register and get [`rtc_crl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtc_crl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RtcCrlSpec;
impl crate::RegisterSpec for RtcCrlSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rtc_crl::R`](R) reader structure"]
impl crate::Readable for RtcCrlSpec {}
#[doc = "`write(|w| ..)` method takes [`rtc_crl::W`](W) writer structure"]
impl crate::Writable for RtcCrlSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets RTC_CRL to value 0"]
impl crate::Resettable for RtcCrlSpec {}
}
#[doc = "RTC_PRLH (rw) register accessor: RTC prescaler load register high\n\nYou can [`read`](crate::Reg::read) this register and get [`rtc_prlh::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtc_prlh::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtc_prlh`] module"]
#[doc(alias = "RTC_PRLH")]
pub type RtcPrlh = crate::Reg<rtc_prlh::RtcPrlhSpec>;
#[doc = "RTC prescaler load register high"]
pub mod rtc_prlh {
#[doc = "Register `RTC_PRLH` reader"]
pub type R = crate::R<RtcPrlhSpec>;
#[doc = "Register `RTC_PRLH` writer"]
pub type W = crate::W<RtcPrlhSpec>;
#[doc = "Field `RTC_PRLH` reader - RTC prescaler load register high"]
pub type RtcPrlhR = crate::FieldReader;
#[doc = "Field `RTC_PRLH` writer - RTC prescaler load register high"]
pub type RtcPrlhW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
impl R {
#[doc = "Bits 0:3 - RTC prescaler load register high"]
#[inline(always)]
pub fn rtc_prlh(&self) -> RtcPrlhR {
RtcPrlhR::new((self.bits & 0x0f) as u8)
}
}
impl W {
#[doc = "Bits 0:3 - RTC prescaler load register high"]
#[inline(always)]
pub fn rtc_prlh(&mut self) -> RtcPrlhW<RtcPrlhSpec> {
RtcPrlhW::new(self, 0)
}
}
#[doc = "RTC prescaler load register high\n\nYou can [`read`](crate::Reg::read) this register and get [`rtc_prlh::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtc_prlh::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RtcPrlhSpec;
impl crate::RegisterSpec for RtcPrlhSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rtc_prlh::R`](R) reader structure"]
impl crate::Readable for RtcPrlhSpec {}
#[doc = "`write(|w| ..)` method takes [`rtc_prlh::W`](W) writer structure"]
impl crate::Writable for RtcPrlhSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets RTC_PRLH to value 0"]
impl crate::Resettable for RtcPrlhSpec {}
}
#[doc = "RTC_PRLL (rw) register accessor: RTC prescaler load register low\n\nYou can [`read`](crate::Reg::read) this register and get [`rtc_prll::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtc_prll::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtc_prll`] module"]
#[doc(alias = "RTC_PRLL")]
pub type RtcPrll = crate::Reg<rtc_prll::RtcPrllSpec>;
#[doc = "RTC prescaler load register low"]
pub mod rtc_prll {
#[doc = "Register `RTC_PRLL` reader"]
pub type R = crate::R<RtcPrllSpec>;
#[doc = "Register `RTC_PRLL` writer"]
pub type W = crate::W<RtcPrllSpec>;
#[doc = "Field `RTC_PRLL` reader - RTC prescaler load register low"]
pub type RtcPrllR = crate::FieldReader<u16>;
#[doc = "Field `RTC_PRLL` writer - RTC prescaler load register low"]
pub type RtcPrllW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - RTC prescaler load register low"]
#[inline(always)]
pub fn rtc_prll(&self) -> RtcPrllR {
RtcPrllR::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15 - RTC prescaler load register low"]
#[inline(always)]
pub fn rtc_prll(&mut self) -> RtcPrllW<RtcPrllSpec> {
RtcPrllW::new(self, 0)
}
}
#[doc = "RTC prescaler load register low\n\nYou can [`read`](crate::Reg::read) this register and get [`rtc_prll::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtc_prll::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RtcPrllSpec;
impl crate::RegisterSpec for RtcPrllSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rtc_prll::R`](R) reader structure"]
impl crate::Readable for RtcPrllSpec {}
#[doc = "`write(|w| ..)` method takes [`rtc_prll::W`](W) writer structure"]
impl crate::Writable for RtcPrllSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets RTC_PRLL to value 0"]
impl crate::Resettable for RtcPrllSpec {}
}
#[doc = "RTC_DIVH (rw) register accessor: RTC prescaler divider register high\n\nYou can [`read`](crate::Reg::read) this register and get [`rtc_divh::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtc_divh::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtc_divh`] module"]
#[doc(alias = "RTC_DIVH")]
pub type RtcDivh = crate::Reg<rtc_divh::RtcDivhSpec>;
#[doc = "RTC prescaler divider register high"]
pub mod rtc_divh {
#[doc = "Register `RTC_DIVH` reader"]
pub type R = crate::R<RtcDivhSpec>;
#[doc = "Register `RTC_DIVH` writer"]
pub type W = crate::W<RtcDivhSpec>;
#[doc = "Field `RTC_DIVH` reader - RTC prescaler divider register high"]
pub type RtcDivhR = crate::FieldReader;
#[doc = "Field `RTC_DIVH` writer - RTC prescaler divider register high"]
pub type RtcDivhW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
impl R {
#[doc = "Bits 0:3 - RTC prescaler divider register high"]
#[inline(always)]
pub fn rtc_divh(&self) -> RtcDivhR {
RtcDivhR::new((self.bits & 0x0f) as u8)
}
}
impl W {
#[doc = "Bits 0:3 - RTC prescaler divider register high"]
#[inline(always)]
pub fn rtc_divh(&mut self) -> RtcDivhW<RtcDivhSpec> {
RtcDivhW::new(self, 0)
}
}
#[doc = "RTC prescaler divider register high\n\nYou can [`read`](crate::Reg::read) this register and get [`rtc_divh::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtc_divh::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RtcDivhSpec;
impl crate::RegisterSpec for RtcDivhSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rtc_divh::R`](R) reader structure"]
impl crate::Readable for RtcDivhSpec {}
#[doc = "`write(|w| ..)` method takes [`rtc_divh::W`](W) writer structure"]
impl crate::Writable for RtcDivhSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets RTC_DIVH to value 0"]
impl crate::Resettable for RtcDivhSpec {}
}
#[doc = "RTC_DIVL (rw) register accessor: RTC prescaler divider register low\n\nYou can [`read`](crate::Reg::read) this register and get [`rtc_divl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtc_divl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtc_divl`] module"]
#[doc(alias = "RTC_DIVL")]
pub type RtcDivl = crate::Reg<rtc_divl::RtcDivlSpec>;
#[doc = "RTC prescaler divider register low"]
pub mod rtc_divl {
#[doc = "Register `RTC_DIVL` reader"]
pub type R = crate::R<RtcDivlSpec>;
#[doc = "Register `RTC_DIVL` writer"]
pub type W = crate::W<RtcDivlSpec>;
#[doc = "Field `RTC_DIVL` reader - RTC prescaler divider register low"]
pub type RtcDivlR = crate::FieldReader<u16>;
#[doc = "Field `RTC_DIVL` writer - RTC prescaler divider register low"]
pub type RtcDivlW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - RTC prescaler divider register low"]
#[inline(always)]
pub fn rtc_divl(&self) -> RtcDivlR {
RtcDivlR::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15 - RTC prescaler divider register low"]
#[inline(always)]
pub fn rtc_divl(&mut self) -> RtcDivlW<RtcDivlSpec> {
RtcDivlW::new(self, 0)
}
}
#[doc = "RTC prescaler divider register low\n\nYou can [`read`](crate::Reg::read) this register and get [`rtc_divl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtc_divl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RtcDivlSpec;
impl crate::RegisterSpec for RtcDivlSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rtc_divl::R`](R) reader structure"]
impl crate::Readable for RtcDivlSpec {}
#[doc = "`write(|w| ..)` method takes [`rtc_divl::W`](W) writer structure"]
impl crate::Writable for RtcDivlSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets RTC_DIVL to value 0"]
impl crate::Resettable for RtcDivlSpec {}
}
#[doc = "RTC_CNTH (rw) register accessor: RTC counter register high\n\nYou can [`read`](crate::Reg::read) this register and get [`rtc_cnth::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtc_cnth::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtc_cnth`] module"]
#[doc(alias = "RTC_CNTH")]
pub type RtcCnth = crate::Reg<rtc_cnth::RtcCnthSpec>;
#[doc = "RTC counter register high"]
pub mod rtc_cnth {
#[doc = "Register `RTC_CNTH` reader"]
pub type R = crate::R<RtcCnthSpec>;
#[doc = "Register `RTC_CNTH` writer"]
pub type W = crate::W<RtcCnthSpec>;
#[doc = "Field `RTC_CNTH` reader - RTC counter register high"]
pub type RtcCnthR = crate::FieldReader<u16>;
#[doc = "Field `RTC_CNTH` writer - RTC counter register high"]
pub type RtcCnthW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - RTC counter register high"]
#[inline(always)]
pub fn rtc_cnth(&self) -> RtcCnthR {
RtcCnthR::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15 - RTC counter register high"]
#[inline(always)]
pub fn rtc_cnth(&mut self) -> RtcCnthW<RtcCnthSpec> {
RtcCnthW::new(self, 0)
}
}
#[doc = "RTC counter register high\n\nYou can [`read`](crate::Reg::read) this register and get [`rtc_cnth::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtc_cnth::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RtcCnthSpec;
impl crate::RegisterSpec for RtcCnthSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rtc_cnth::R`](R) reader structure"]
impl crate::Readable for RtcCnthSpec {}
#[doc = "`write(|w| ..)` method takes [`rtc_cnth::W`](W) writer structure"]
impl crate::Writable for RtcCnthSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets RTC_CNTH to value 0"]
impl crate::Resettable for RtcCnthSpec {}
}
#[doc = "RTC_CNTL (rw) register accessor: RTC counter register low\n\nYou can [`read`](crate::Reg::read) this register and get [`rtc_cntl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtc_cntl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtc_cntl`] module"]
#[doc(alias = "RTC_CNTL")]
pub type RtcCntl = crate::Reg<rtc_cntl::RtcCntlSpec>;
#[doc = "RTC counter register low"]
pub mod rtc_cntl {
#[doc = "Register `RTC_CNTL` reader"]
pub type R = crate::R<RtcCntlSpec>;
#[doc = "Register `RTC_CNTL` writer"]
pub type W = crate::W<RtcCntlSpec>;
#[doc = "Field `RTC_CNTL` reader - RTC counter register low"]
pub type RtcCntlR = crate::FieldReader<u16>;
#[doc = "Field `RTC_CNTL` writer - RTC counter register low"]
pub type RtcCntlW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - RTC counter register low"]
#[inline(always)]
pub fn rtc_cntl(&self) -> RtcCntlR {
RtcCntlR::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15 - RTC counter register low"]
#[inline(always)]
pub fn rtc_cntl(&mut self) -> RtcCntlW<RtcCntlSpec> {
RtcCntlW::new(self, 0)
}
}
#[doc = "RTC counter register low\n\nYou can [`read`](crate::Reg::read) this register and get [`rtc_cntl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtc_cntl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RtcCntlSpec;
impl crate::RegisterSpec for RtcCntlSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rtc_cntl::R`](R) reader structure"]
impl crate::Readable for RtcCntlSpec {}
#[doc = "`write(|w| ..)` method takes [`rtc_cntl::W`](W) writer structure"]
impl crate::Writable for RtcCntlSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets RTC_CNTL to value 0"]
impl crate::Resettable for RtcCntlSpec {}
}
#[doc = "RTC_ALRH (rw) register accessor: RTC alarm register high\n\nYou can [`read`](crate::Reg::read) this register and get [`rtc_alrh::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtc_alrh::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtc_alrh`] module"]
#[doc(alias = "RTC_ALRH")]
pub type RtcAlrh = crate::Reg<rtc_alrh::RtcAlrhSpec>;
#[doc = "RTC alarm register high"]
pub mod rtc_alrh {
#[doc = "Register `RTC_ALRH` reader"]
pub type R = crate::R<RtcAlrhSpec>;
#[doc = "Register `RTC_ALRH` writer"]
pub type W = crate::W<RtcAlrhSpec>;
#[doc = "Field `RTC_ALRH` reader - RTC alarm register high"]
pub type RtcAlrhR = crate::FieldReader<u16>;
#[doc = "Field `RTC_ALRH` writer - RTC alarm register high"]
pub type RtcAlrhW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - RTC alarm register high"]
#[inline(always)]
pub fn rtc_alrh(&self) -> RtcAlrhR {
RtcAlrhR::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15 - RTC alarm register high"]
#[inline(always)]
pub fn rtc_alrh(&mut self) -> RtcAlrhW<RtcAlrhSpec> {
RtcAlrhW::new(self, 0)
}
}
#[doc = "RTC alarm register high\n\nYou can [`read`](crate::Reg::read) this register and get [`rtc_alrh::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtc_alrh::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RtcAlrhSpec;
impl crate::RegisterSpec for RtcAlrhSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rtc_alrh::R`](R) reader structure"]
impl crate::Readable for RtcAlrhSpec {}
#[doc = "`write(|w| ..)` method takes [`rtc_alrh::W`](W) writer structure"]
impl crate::Writable for RtcAlrhSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets RTC_ALRH to value 0"]
impl crate::Resettable for RtcAlrhSpec {}
}
#[doc = "RTC_ALRL (rw) register accessor: RTC alarm register low\n\nYou can [`read`](crate::Reg::read) this register and get [`rtc_alrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtc_alrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtc_alrl`] module"]
#[doc(alias = "RTC_ALRL")]
pub type RtcAlrl = crate::Reg<rtc_alrl::RtcAlrlSpec>;
#[doc = "RTC alarm register low"]
pub mod rtc_alrl {
#[doc = "Register `RTC_ALRL` reader"]
pub type R = crate::R<RtcAlrlSpec>;
#[doc = "Register `RTC_ALRL` writer"]
pub type W = crate::W<RtcAlrlSpec>;
#[doc = "Field `RTC_ALRL` reader - RTC alarm register low"]
pub type RtcAlrlR = crate::FieldReader<u16>;
#[doc = "Field `RTC_ALRL` writer - RTC alarm register low"]
pub type RtcAlrlW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - RTC alarm register low"]
#[inline(always)]
pub fn rtc_alrl(&self) -> RtcAlrlR {
RtcAlrlR::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15 - RTC alarm register low"]
#[inline(always)]
pub fn rtc_alrl(&mut self) -> RtcAlrlW<RtcAlrlSpec> {
RtcAlrlW::new(self, 0)
}
}
#[doc = "RTC alarm register low\n\nYou can [`read`](crate::Reg::read) this register and get [`rtc_alrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtc_alrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RtcAlrlSpec;
impl crate::RegisterSpec for RtcAlrlSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rtc_alrl::R`](R) reader structure"]
impl crate::Readable for RtcAlrlSpec {}
#[doc = "`write(|w| ..)` method takes [`rtc_alrl::W`](W) writer structure"]
impl crate::Writable for RtcAlrlSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets RTC_ALRL to value 0"]
impl crate::Resettable for RtcAlrlSpec {}
}
#[doc = "RTC_RCYC (rw) register accessor: Read minimum cycle\n\nYou can [`read`](crate::Reg::read) this register and get [`rtc_rcyc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtc_rcyc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtc_rcyc`] module"]
#[doc(alias = "RTC_RCYC")]
pub type RtcRcyc = crate::Reg<rtc_rcyc::RtcRcycSpec>;
#[doc = "Read minimum cycle"]
pub mod rtc_rcyc {
#[doc = "Register `RTC_RCYC` reader"]
pub type R = crate::R<RtcRcycSpec>;
#[doc = "Register `RTC_RCYC` writer"]
pub type W = crate::W<RtcRcycSpec>;
#[doc = "Field `RTC_RCYC` reader - Read minimum cycle"]
pub type RtcRcycR = crate::FieldReader;
#[doc = "Field `RTC_RCYC` writer - Read minimum cycle"]
pub type RtcRcycW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
impl R {
#[doc = "Bits 0:3 - Read minimum cycle"]
#[inline(always)]
pub fn rtc_rcyc(&self) -> RtcRcycR {
RtcRcycR::new((self.bits & 0x0f) as u8)
}
}
impl W {
#[doc = "Bits 0:3 - Read minimum cycle"]
#[inline(always)]
pub fn rtc_rcyc(&mut self) -> RtcRcycW<RtcRcycSpec> {
RtcRcycW::new(self, 0)
}
}
#[doc = "Read minimum cycle\n\nYou can [`read`](crate::Reg::read) this register and get [`rtc_rcyc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtc_rcyc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RtcRcycSpec;
impl crate::RegisterSpec for RtcRcycSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rtc_rcyc::R`](R) reader structure"]
impl crate::Readable for RtcRcycSpec {}
#[doc = "`write(|w| ..)` method takes [`rtc_rcyc::W`](W) writer structure"]
impl crate::Writable for RtcRcycSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets RTC_RCYC to value 0"]
impl crate::Resettable for RtcRcycSpec {}
}
#[doc = "RCC_BDCR (rw) register accessor: Backup domain control register\n\nYou can [`read`](crate::Reg::read) this register and get [`rcc_bdcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rcc_bdcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rcc_bdcr`] module"]
#[doc(alias = "RCC_BDCR")]
pub type RccBdcr = crate::Reg<rcc_bdcr::RccBdcrSpec>;
#[doc = "Backup domain control register"]
pub mod rcc_bdcr {
#[doc = "Register `RCC_BDCR` reader"]
pub type R = crate::R<RccBdcrSpec>;
#[doc = "Register `RCC_BDCR` writer"]
pub type W = crate::W<RccBdcrSpec>;
#[doc = "Field `LSEON` reader - Low speed external oscillator enable"]
pub type LseonR = crate::BitReader;
#[doc = "Field `LSEON` writer - Low speed external oscillator enable"]
pub type LseonW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `LSERDY` reader - Low speed external oscillator ready"]
pub type LserdyR = crate::BitReader;
#[doc = "Field `LSERDY` writer - Low speed external oscillator ready"]
pub type LserdyW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `LSEBYP` reader - Low speed external oscillator ready bypass"]
pub type LsebypR = crate::BitReader;
#[doc = "Field `LSEBYP` writer - Low speed external oscillator ready bypass"]
pub type LsebypW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "RTC source selection\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Rtcsel {
#[doc = "0: No clock"]
Noclock = 0,
#[doc = "1: LSE"]
Lse = 1,
#[doc = "2: LSI"]
Lsi = 2,
#[doc = "3: External"]
External = 3,
}
impl From<Rtcsel> for u8 {
#[inline(always)]
fn from(variant: Rtcsel) -> Self {
variant as _
}
}
impl crate::FieldSpec for Rtcsel {
type Ux = u8;
}
impl crate::IsEnum for Rtcsel {}
#[doc = "Field `RTCSEL` reader - RTC source selection"]
pub type RtcselR = crate::FieldReader<Rtcsel>;
impl RtcselR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Rtcsel {
match self.bits {
0 => Rtcsel::Noclock,
1 => Rtcsel::Lse,
2 => Rtcsel::Lsi,
3 => Rtcsel::External,
_ => unreachable!(),
}
}
#[doc = "No clock"]
#[inline(always)]
pub fn is_noclock(&self) -> bool {
*self == Rtcsel::Noclock
}
#[doc = "LSE"]
#[inline(always)]
pub fn is_lse(&self) -> bool {
*self == Rtcsel::Lse
}
#[doc = "LSI"]
#[inline(always)]
pub fn is_lsi(&self) -> bool {
*self == Rtcsel::Lsi
}
#[doc = "External"]
#[inline(always)]
pub fn is_external(&self) -> bool {
*self == Rtcsel::External
}
}
#[doc = "Field `RTCSEL` writer - RTC source selection"]
pub type RtcselW<'a, REG> = crate::FieldWriter<'a, REG, 2, Rtcsel, crate::Safe>;
impl<'a, REG> RtcselW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "No clock"]
#[inline(always)]
pub fn noclock(self) -> &'a mut crate::W<REG> {
self.variant(Rtcsel::Noclock)
}
#[doc = "LSE"]
#[inline(always)]
pub fn lse(self) -> &'a mut crate::W<REG> {
self.variant(Rtcsel::Lse)
}
#[doc = "LSI"]
#[inline(always)]
pub fn lsi(self) -> &'a mut crate::W<REG> {
self.variant(Rtcsel::Lsi)
}
#[doc = "External"]
#[inline(always)]
pub fn external(self) -> &'a mut crate::W<REG> {
self.variant(Rtcsel::External)
}
}
#[doc = "Field `RTCEN` reader - RTC enable"]
pub type RtcenR = crate::BitReader;
#[doc = "Field `RTCEN` writer - RTC enable"]
pub type RtcenW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - Low speed external oscillator enable"]
#[inline(always)]
pub fn lseon(&self) -> LseonR {
LseonR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Low speed external oscillator ready"]
#[inline(always)]
pub fn lserdy(&self) -> LserdyR {
LserdyR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Low speed external oscillator ready bypass"]
#[inline(always)]
pub fn lsebyp(&self) -> LsebypR {
LsebypR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bits 8:9 - RTC source selection"]
#[inline(always)]
pub fn rtcsel(&self) -> RtcselR {
RtcselR::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bit 15 - RTC enable"]
#[inline(always)]
pub fn rtcen(&self) -> RtcenR {
RtcenR::new(((self.bits >> 15) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Low speed external oscillator enable"]
#[inline(always)]
pub fn lseon(&mut self) -> LseonW<RccBdcrSpec> {
LseonW::new(self, 0)
}
#[doc = "Bit 1 - Low speed external oscillator ready"]
#[inline(always)]
pub fn lserdy(&mut self) -> LserdyW<RccBdcrSpec> {
LserdyW::new(self, 1)
}
#[doc = "Bit 2 - Low speed external oscillator ready bypass"]
#[inline(always)]
pub fn lsebyp(&mut self) -> LsebypW<RccBdcrSpec> {
LsebypW::new(self, 2)
}
#[doc = "Bits 8:9 - RTC source selection"]
#[inline(always)]
pub fn rtcsel(&mut self) -> RtcselW<RccBdcrSpec> {
RtcselW::new(self, 8)
}
#[doc = "Bit 15 - RTC enable"]
#[inline(always)]
pub fn rtcen(&mut self) -> RtcenW<RccBdcrSpec> {
RtcenW::new(self, 15)
}
}
#[doc = "Backup domain control register\n\nYou can [`read`](crate::Reg::read) this register and get [`rcc_bdcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rcc_bdcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RccBdcrSpec;
impl crate::RegisterSpec for RccBdcrSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`rcc_bdcr::R`](R) reader structure"]
impl crate::Readable for RccBdcrSpec {}
#[doc = "`write(|w| ..)` method takes [`rcc_bdcr::W`](W) writer structure"]
impl crate::Writable for RccBdcrSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets RCC_BDCR to value 0"]
impl crate::Resettable for RccBdcrSpec {}
}
#[doc = "RCC_BDRST (rw) register accessor: Backup domain software reset\n\nYou can [`read`](crate::Reg::read) this register and get [`rcc_bdrst::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rcc_bdrst::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rcc_bdrst`] module"]
#[doc(alias = "RCC_BDRST")]
pub type RccBdrst = crate::Reg<rcc_bdrst::RccBdrstSpec>;
#[doc = "Backup domain software reset"]
pub mod rcc_bdrst {
#[doc = "Register `RCC_BDRST` reader"]
pub type R = crate::R<RccBdrstSpec>;
#[doc = "Register `RCC_BDRST` writer"]
pub type W = crate::W<RccBdrstSpec>;
#[doc = "Field `RCC_BDRST` reader - Backup domain software reset"]
pub type RccBdrstR = crate::BitReader;
#[doc = "Field `RCC_BDRST` writer - Backup domain software reset"]
pub type RccBdrstW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - Backup domain software reset"]
#[inline(always)]
pub fn rcc_bdrst(&self) -> RccBdrstR {
RccBdrstR::new((self.bits & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Backup domain software reset"]
#[inline(always)]
pub fn rcc_bdrst(&mut self) -> RccBdrstW<RccBdrstSpec> {
RccBdrstW::new(self, 0)
}
}
#[doc = "Backup domain software reset\n\nYou can [`read`](crate::Reg::read) this register and get [`rcc_bdrst::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rcc_bdrst::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RccBdrstSpec;
impl crate::RegisterSpec for RccBdrstSpec {
type Ux = u16;
}
#[doc = "`read()` method returns [`rcc_bdrst::R`](R) reader structure"]
impl crate::Readable for RccBdrstSpec {}
#[doc = "`write(|w| ..)` method takes [`rcc_bdrst::W`](W) writer structure"]
impl crate::Writable for RccBdrstSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets RCC_BDRST to value 0"]
impl crate::Resettable for RccBdrstSpec {}
}
#[doc = "IWDG_CTRL (rw) register accessor: Independent watchdog control\n\nYou can [`read`](crate::Reg::read) this register and get [`iwdg_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iwdg_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iwdg_ctrl`] module"]
#[doc(alias = "IWDG_CTRL")]
pub type IwdgCtrl = crate::Reg<iwdg_ctrl::IwdgCtrlSpec>;
#[doc = "Independent watchdog control"]
pub mod iwdg_ctrl {
#[doc = "Register `IWDG_CTRL` reader"]
pub type R = crate::R<IwdgCtrlSpec>;
#[doc = "Register `IWDG_CTRL` writer"]
pub type W = crate::W<IwdgCtrlSpec>;
#[doc = "Prescaler register\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Pr {
#[doc = "0: Div 2"]
Div2 = 0,
#[doc = "1: Div 4"]
Div4 = 1,
#[doc = "2: Div 8"]
Div8 = 2,
#[doc = "3: Div 16"]
Div16 = 3,
#[doc = "4: Div 32"]
Div32 = 4,
#[doc = "5: Div 64"]
Div64 = 5,
#[doc = "6: Div 128"]
Div128 = 6,
#[doc = "7: Div 256"]
Div256 = 7,
}
impl From<Pr> for u8 {
#[inline(always)]
fn from(variant: Pr) -> Self {
variant as _
}
}
impl crate::FieldSpec for Pr {
type Ux = u8;
}
impl crate::IsEnum for Pr {}
#[doc = "Field `PR` reader - Prescaler register"]
pub type PrR = crate::FieldReader<Pr>;
impl PrR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Pr {
match self.bits {
0 => Pr::Div2,
1 => Pr::Div4,
2 => Pr::Div8,
3 => Pr::Div16,
4 => Pr::Div32,
5 => Pr::Div64,
6 => Pr::Div128,
7 => Pr::Div256,
_ => unreachable!(),
}
}
#[doc = "Div 2"]
#[inline(always)]
pub fn is_div2(&self) -> bool {
*self == Pr::Div2
}
#[doc = "Div 4"]
#[inline(always)]
pub fn is_div4(&self) -> bool {
*self == Pr::Div4
}
#[doc = "Div 8"]
#[inline(always)]
pub fn is_div8(&self) -> bool {
*self == Pr::Div8
}
#[doc = "Div 16"]
#[inline(always)]
pub fn is_div16(&self) -> bool {
*self == Pr::Div16
}
#[doc = "Div 32"]
#[inline(always)]
pub fn is_div32(&self) -> bool {
*self == Pr::Div32
}
#[doc = "Div 64"]
#[inline(always)]
pub fn is_div64(&self) -> bool {
*self == Pr::Div64
}
#[doc = "Div 128"]
#[inline(always)]
pub fn is_div128(&self) -> bool {
*self == Pr::Div128
}
#[doc = "Div 256"]
#[inline(always)]
pub fn is_div256(&self) -> bool {
*self == Pr::Div256
}
}
#[doc = "Field `PR` writer - Prescaler register"]
pub type PrW<'a, REG> = crate::FieldWriter<'a, REG, 3, Pr, crate::Safe>;
impl<'a, REG> PrW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Div 2"]
#[inline(always)]
pub fn div2(self) -> &'a mut crate::W<REG> {
self.variant(Pr::Div2)
}
#[doc = "Div 4"]
#[inline(always)]
pub fn div4(self) -> &'a mut crate::W<REG> {
self.variant(Pr::Div4)
}
#[doc = "Div 8"]
#[inline(always)]
pub fn div8(self) -> &'a mut crate::W<REG> {
self.variant(Pr::Div8)
}
#[doc = "Div 16"]
#[inline(always)]
pub fn div16(self) -> &'a mut crate::W<REG> {
self.variant(Pr::Div16)
}
#[doc = "Div 32"]
#[inline(always)]
pub fn div32(self) -> &'a mut crate::W<REG> {
self.variant(Pr::Div32)
}
#[doc = "Div 64"]
#[inline(always)]
pub fn div64(self) -> &'a mut crate::W<REG> {
self.variant(Pr::Div64)
}
#[doc = "Div 128"]
#[inline(always)]
pub fn div128(self) -> &'a mut crate::W<REG> {
self.variant(Pr::Div128)
}
#[doc = "Div 256"]
#[inline(always)]
pub fn div256(self) -> &'a mut crate::W<REG> {
self.variant(Pr::Div256)
}
}
#[doc = "Field `STOP_FREEZE` reader - Freeze IWDG clock in stop mode"]
pub type StopFreezeR = crate::BitReader;
#[doc = "Field `STOP_FREEZE` writer - Freeze IWDG clock in stop mode"]
pub type StopFreezeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `STDBY_FREEZE` reader - Freeze IWDG clock in standby mode"]
pub type StdbyFreezeR = crate::BitReader;
#[doc = "Field `STDBY_FREEZE` writer - Freeze IWDG clock in standby mode"]
pub type StdbyFreezeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "IWDG clock source selection in non-standby mode\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Clksel {
#[doc = "0: LSI"]
Lsi = 0,
#[doc = "1: LSE"]
Lse = 1,
}
impl From<Clksel> for bool {
#[inline(always)]
fn from(variant: Clksel) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `CLKSEL` reader - IWDG clock source selection in non-standby mode"]
pub type ClkselR = crate::BitReader<Clksel>;
impl ClkselR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Clksel {
match self.bits {
false => Clksel::Lsi,
true => Clksel::Lse,
}
}
#[doc = "LSI"]
#[inline(always)]
pub fn is_lsi(&self) -> bool {
*self == Clksel::Lsi
}
#[doc = "LSE"]
#[inline(always)]
pub fn is_lse(&self) -> bool {
*self == Clksel::Lse
}
}
#[doc = "Field `CLKSEL` writer - IWDG clock source selection in non-standby mode"]
pub type ClkselW<'a, REG> = crate::BitWriter<'a, REG, Clksel>;
impl<'a, REG> ClkselW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "LSI"]
#[inline(always)]
pub fn lsi(self) -> &'a mut crate::W<REG> {
self.variant(Clksel::Lsi)
}
#[doc = "LSE"]
#[inline(always)]
pub fn lse(self) -> &'a mut crate::W<REG> {
self.variant(Clksel::Lse)
}
}
#[doc = "Field `IWDG_EN` reader - IWDG enable"]
pub type IwdgEnR = crate::BitReader;
#[doc = "Field `IWDG_EN` writer - IWDG enable"]
pub type IwdgEnW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:2 - Prescaler register"]
#[inline(always)]
pub fn pr(&self) -> PrR {
PrR::new((self.bits & 7) as u8)
}
#[doc = "Bit 4 - Freeze IWDG clock in stop mode"]
#[inline(always)]
pub fn stop_freeze(&self) -> StopFreezeR {
StopFreezeR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Freeze IWDG clock in standby mode"]
#[inline(always)]
pub fn stdby_freeze(&self) -> StdbyFreezeR {
StdbyFreezeR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - IWDG clock source selection in non-standby mode"]
#[inline(always)]
pub fn clksel(&self) -> ClkselR {
ClkselR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 8 - IWDG enable"]
#[inline(always)]
pub fn iwdg_en(&self) -> IwdgEnR {
IwdgEnR::new(((self.bits >> 8) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:2 - Prescaler register"]
#[inline(always)]
pub fn pr(&mut self) -> PrW<IwdgCtrlSpec> {
PrW::new(self, 0)
}
#[doc = "Bit 4 - Freeze IWDG clock in stop mode"]
#[inline(always)]
pub fn stop_freeze(&mut self) -> StopFreezeW<IwdgCtrlSpec> {
StopFreezeW::new(self, 4)
}
#[doc = "Bit 5 - Freeze IWDG clock in standby mode"]
#[inline(always)]
pub fn stdby_freeze(&mut self) -> StdbyFreezeW<IwdgCtrlSpec> {
StdbyFreezeW::new(self, 5)
}
#[doc = "Bit 6 - IWDG clock source selection in non-standby mode"]
#[inline(always)]
pub fn clksel(&mut self) -> ClkselW<IwdgCtrlSpec> {
ClkselW::new(self, 6)
}
#[doc = "Bit 8 - IWDG enable"]
#[inline(always)]
pub fn iwdg_en(&mut self) -> IwdgEnW<IwdgCtrlSpec> {
IwdgEnW::new(self, 8)
}
}
#[doc = "Independent watchdog control\n\nYou can [`read`](crate::Reg::read) this register and get [`iwdg_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iwdg_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IwdgCtrlSpec;
impl crate::RegisterSpec for IwdgCtrlSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`iwdg_ctrl::R`](R) reader structure"]
impl crate::Readable for IwdgCtrlSpec {}
#[doc = "`write(|w| ..)` method takes [`iwdg_ctrl::W`](W) writer structure"]
impl crate::Writable for IwdgCtrlSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets IWDG_CTRL to value 0"]
impl crate::Resettable for IwdgCtrlSpec {}
}
#[doc = "BKP_RTCCR (rw) register accessor: RTC clock calibration register\n\nYou can [`read`](crate::Reg::read) this register and get [`bkp_rtccr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bkp_rtccr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bkp_rtccr`] module"]
#[doc(alias = "BKP_RTCCR")]
pub type BkpRtccr = crate::Reg<bkp_rtccr::BkpRtccrSpec>;
#[doc = "RTC clock calibration register"]
pub mod bkp_rtccr {
#[doc = "Register `BKP_RTCCR` reader"]
pub type R = crate::R<BkpRtccrSpec>;
#[doc = "Register `BKP_RTCCR` writer"]
pub type W = crate::W<BkpRtccrSpec>;
#[doc = "Field `CAL` reader - RTC calibration value"]
pub type CalR = crate::FieldReader;
#[doc = "Field `CAL` writer - RTC calibration value"]
pub type CalW<'a, REG> = crate::FieldWriter<'a, REG, 7>;
#[doc = "Field `CCO` reader - Calibration clock output"]
pub type CcoR = crate::BitReader;
#[doc = "Field `CCO` writer - Calibration clock output"]
pub type CcoW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ASOE` reader - Alarm or second output enable"]
pub type AsoeR = crate::BitReader;
#[doc = "Field `ASOE` writer - Alarm or second output enable"]
pub type AsoeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Alarm or second output selection\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Asos {
#[doc = "0: Alarm output"]
Alarmoutput = 0,
#[doc = "1: Second output"]
Secondoutput = 1,
}
impl From<Asos> for bool {
#[inline(always)]
fn from(variant: Asos) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `ASOS` reader - Alarm or second output selection"]
pub type AsosR = crate::BitReader<Asos>;
impl AsosR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Asos {
match self.bits {
false => Asos::Alarmoutput,
true => Asos::Secondoutput,
}
}
#[doc = "Alarm output"]
#[inline(always)]
pub fn is_alarmoutput(&self) -> bool {
*self == Asos::Alarmoutput
}
#[doc = "Second output"]
#[inline(always)]
pub fn is_secondoutput(&self) -> bool {
*self == Asos::Secondoutput
}
}
#[doc = "Field `ASOS` writer - Alarm or second output selection"]
pub type AsosW<'a, REG> = crate::BitWriter<'a, REG, Asos>;
impl<'a, REG> AsosW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Alarm output"]
#[inline(always)]
pub fn alarmoutput(self) -> &'a mut crate::W<REG> {
self.variant(Asos::Alarmoutput)
}
#[doc = "Second output"]
#[inline(always)]
pub fn secondoutput(self) -> &'a mut crate::W<REG> {
self.variant(Asos::Secondoutput)
}
}
impl R {
#[doc = "Bits 0:6 - RTC calibration value"]
#[inline(always)]
pub fn cal(&self) -> CalR {
CalR::new((self.bits & 0x7f) as u8)
}
#[doc = "Bit 7 - Calibration clock output"]
#[inline(always)]
pub fn cco(&self) -> CcoR {
CcoR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - Alarm or second output enable"]
#[inline(always)]
pub fn asoe(&self) -> AsoeR {
AsoeR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - Alarm or second output selection"]
#[inline(always)]
pub fn asos(&self) -> AsosR {
AsosR::new(((self.bits >> 9) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:6 - RTC calibration value"]
#[inline(always)]
pub fn cal(&mut self) -> CalW<BkpRtccrSpec> {
CalW::new(self, 0)
}
#[doc = "Bit 7 - Calibration clock output"]
#[inline(always)]
pub fn cco(&mut self) -> CcoW<BkpRtccrSpec> {
CcoW::new(self, 7)
}
#[doc = "Bit 8 - Alarm or second output enable"]
#[inline(always)]
pub fn asoe(&mut self) -> AsoeW<BkpRtccrSpec> {
AsoeW::new(self, 8)
}
#[doc = "Bit 9 - Alarm or second output selection"]
#[inline(always)]
pub fn asos(&mut self) -> AsosW<BkpRtccrSpec> {
AsosW::new(self, 9)
}
}
#[doc = "RTC clock calibration register\n\nYou can [`read`](crate::Reg::read) this register and get [`bkp_rtccr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bkp_rtccr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct BkpRtccrSpec;
impl crate::RegisterSpec for BkpRtccrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`bkp_rtccr::R`](R) reader structure"]
impl crate::Readable for BkpRtccrSpec {}
#[doc = "`write(|w| ..)` method takes [`bkp_rtccr::W`](W) writer structure"]
impl crate::Writable for BkpRtccrSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets BKP_RTCCR to value 0"]
impl crate::Resettable for BkpRtccrSpec {}
}
#[doc = "BKP_DR0 (rw) register accessor: Backup data register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`bkp_dr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bkp_dr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bkp_dr0`] module"]
#[doc(alias = "BKP_DR0")]
pub type BkpDr0 = crate::Reg<bkp_dr0::BkpDr0Spec>;
#[doc = "Backup data register 0"]
pub mod bkp_dr0 {
#[doc = "Register `BKP_DR0` reader"]
pub type R = crate::R<BkpDr0Spec>;
#[doc = "Register `BKP_DR0` writer"]
pub type W = crate::W<BkpDr0Spec>;
#[doc = "Field `BKP_DR0` reader - Backup data register 0"]
pub type BkpDr0R = crate::FieldReader<u16>;
#[doc = "Field `BKP_DR0` writer - Backup data register 0"]
pub type BkpDr0W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - Backup data register 0"]
#[inline(always)]
pub fn bkp_dr0(&self) -> BkpDr0R {
BkpDr0R::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15 - Backup data register 0"]
#[inline(always)]
pub fn bkp_dr0(&mut self) -> BkpDr0W<BkpDr0Spec> {
BkpDr0W::new(self, 0)
}
}
#[doc = "Backup data register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`bkp_dr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bkp_dr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct BkpDr0Spec;
impl crate::RegisterSpec for BkpDr0Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`bkp_dr0::R`](R) reader structure"]
impl crate::Readable for BkpDr0Spec {}
#[doc = "`write(|w| ..)` method takes [`bkp_dr0::W`](W) writer structure"]
impl crate::Writable for BkpDr0Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets BKP_DR0 to value 0"]
impl crate::Resettable for BkpDr0Spec {}
}
#[doc = "BKP_DR1 (rw) register accessor: Backup data register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`bkp_dr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bkp_dr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bkp_dr1`] module"]
#[doc(alias = "BKP_DR1")]
pub type BkpDr1 = crate::Reg<bkp_dr1::BkpDr1Spec>;
#[doc = "Backup data register 1"]
pub mod bkp_dr1 {
#[doc = "Register `BKP_DR1` reader"]
pub type R = crate::R<BkpDr1Spec>;
#[doc = "Register `BKP_DR1` writer"]
pub type W = crate::W<BkpDr1Spec>;
#[doc = "Field `BKP_DR1` reader - Backup data register 1"]
pub type BkpDr1R = crate::FieldReader<u16>;
#[doc = "Field `BKP_DR1` writer - Backup data register 1"]
pub type BkpDr1W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - Backup data register 1"]
#[inline(always)]
pub fn bkp_dr1(&self) -> BkpDr1R {
BkpDr1R::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15 - Backup data register 1"]
#[inline(always)]
pub fn bkp_dr1(&mut self) -> BkpDr1W<BkpDr1Spec> {
BkpDr1W::new(self, 0)
}
}
#[doc = "Backup data register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`bkp_dr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bkp_dr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct BkpDr1Spec;
impl crate::RegisterSpec for BkpDr1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`bkp_dr1::R`](R) reader structure"]
impl crate::Readable for BkpDr1Spec {}
#[doc = "`write(|w| ..)` method takes [`bkp_dr1::W`](W) writer structure"]
impl crate::Writable for BkpDr1Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets BKP_DR1 to value 0"]
impl crate::Resettable for BkpDr1Spec {}
}
#[doc = "BKP_DR2 (rw) register accessor: Backup data register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`bkp_dr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bkp_dr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bkp_dr2`] module"]
#[doc(alias = "BKP_DR2")]
pub type BkpDr2 = crate::Reg<bkp_dr2::BkpDr2Spec>;
#[doc = "Backup data register 2"]
pub mod bkp_dr2 {
#[doc = "Register `BKP_DR2` reader"]
pub type R = crate::R<BkpDr2Spec>;
#[doc = "Register `BKP_DR2` writer"]
pub type W = crate::W<BkpDr2Spec>;
#[doc = "Field `BKP_DR2` reader - Backup data register 2"]
pub type BkpDr2R = crate::FieldReader<u16>;
#[doc = "Field `BKP_DR2` writer - Backup data register 2"]
pub type BkpDr2W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - Backup data register 2"]
#[inline(always)]
pub fn bkp_dr2(&self) -> BkpDr2R {
BkpDr2R::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15 - Backup data register 2"]
#[inline(always)]
pub fn bkp_dr2(&mut self) -> BkpDr2W<BkpDr2Spec> {
BkpDr2W::new(self, 0)
}
}
#[doc = "Backup data register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`bkp_dr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bkp_dr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct BkpDr2Spec;
impl crate::RegisterSpec for BkpDr2Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`bkp_dr2::R`](R) reader structure"]
impl crate::Readable for BkpDr2Spec {}
#[doc = "`write(|w| ..)` method takes [`bkp_dr2::W`](W) writer structure"]
impl crate::Writable for BkpDr2Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets BKP_DR2 to value 0"]
impl crate::Resettable for BkpDr2Spec {}
}
#[doc = "BKP_DR3 (rw) register accessor: Backup data register 3\n\nYou can [`read`](crate::Reg::read) this register and get [`bkp_dr3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bkp_dr3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bkp_dr3`] module"]
#[doc(alias = "BKP_DR3")]
pub type BkpDr3 = crate::Reg<bkp_dr3::BkpDr3Spec>;
#[doc = "Backup data register 3"]
pub mod bkp_dr3 {
#[doc = "Register `BKP_DR3` reader"]
pub type R = crate::R<BkpDr3Spec>;
#[doc = "Register `BKP_DR3` writer"]
pub type W = crate::W<BkpDr3Spec>;
#[doc = "Field `BKP_DR3` reader - Backup data register 3"]
pub type BkpDr3R = crate::FieldReader<u16>;
#[doc = "Field `BKP_DR3` writer - Backup data register 3"]
pub type BkpDr3W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - Backup data register 3"]
#[inline(always)]
pub fn bkp_dr3(&self) -> BkpDr3R {
BkpDr3R::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15 - Backup data register 3"]
#[inline(always)]
pub fn bkp_dr3(&mut self) -> BkpDr3W<BkpDr3Spec> {
BkpDr3W::new(self, 0)
}
}
#[doc = "Backup data register 3\n\nYou can [`read`](crate::Reg::read) this register and get [`bkp_dr3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bkp_dr3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct BkpDr3Spec;
impl crate::RegisterSpec for BkpDr3Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`bkp_dr3::R`](R) reader structure"]
impl crate::Readable for BkpDr3Spec {}
#[doc = "`write(|w| ..)` method takes [`bkp_dr3::W`](W) writer structure"]
impl crate::Writable for BkpDr3Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets BKP_DR3 to value 0"]
impl crate::Resettable for BkpDr3Spec {}
}
#[doc = "BKP_DR4 (rw) register accessor: Backup data register 4\n\nYou can [`read`](crate::Reg::read) this register and get [`bkp_dr4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bkp_dr4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bkp_dr4`] module"]
#[doc(alias = "BKP_DR4")]
pub type BkpDr4 = crate::Reg<bkp_dr4::BkpDr4Spec>;
#[doc = "Backup data register 4"]
pub mod bkp_dr4 {
#[doc = "Register `BKP_DR4` reader"]
pub type R = crate::R<BkpDr4Spec>;
#[doc = "Register `BKP_DR4` writer"]
pub type W = crate::W<BkpDr4Spec>;
#[doc = "Field `BKP_DR4` reader - Backup data register 4"]
pub type BkpDr4R = crate::FieldReader<u16>;
#[doc = "Field `BKP_DR4` writer - Backup data register 4"]
pub type BkpDr4W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - Backup data register 4"]
#[inline(always)]
pub fn bkp_dr4(&self) -> BkpDr4R {
BkpDr4R::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15 - Backup data register 4"]
#[inline(always)]
pub fn bkp_dr4(&mut self) -> BkpDr4W<BkpDr4Spec> {
BkpDr4W::new(self, 0)
}
}
#[doc = "Backup data register 4\n\nYou can [`read`](crate::Reg::read) this register and get [`bkp_dr4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bkp_dr4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct BkpDr4Spec;
impl crate::RegisterSpec for BkpDr4Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`bkp_dr4::R`](R) reader structure"]
impl crate::Readable for BkpDr4Spec {}
#[doc = "`write(|w| ..)` method takes [`bkp_dr4::W`](W) writer structure"]
impl crate::Writable for BkpDr4Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets BKP_DR4 to value 0"]
impl crate::Resettable for BkpDr4Spec {}
}
#[doc = "BKP_DR5 (rw) register accessor: Backup data register 5\n\nYou can [`read`](crate::Reg::read) this register and get [`bkp_dr5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bkp_dr5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bkp_dr5`] module"]
#[doc(alias = "BKP_DR5")]
pub type BkpDr5 = crate::Reg<bkp_dr5::BkpDr5Spec>;
#[doc = "Backup data register 5"]
pub mod bkp_dr5 {
#[doc = "Register `BKP_DR5` reader"]
pub type R = crate::R<BkpDr5Spec>;
#[doc = "Register `BKP_DR5` writer"]
pub type W = crate::W<BkpDr5Spec>;
#[doc = "Field `BKP_DR5` reader - Backup data register 5"]
pub type BkpDr5R = crate::FieldReader<u16>;
#[doc = "Field `BKP_DR5` writer - Backup data register 5"]
pub type BkpDr5W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - Backup data register 5"]
#[inline(always)]
pub fn bkp_dr5(&self) -> BkpDr5R {
BkpDr5R::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15 - Backup data register 5"]
#[inline(always)]
pub fn bkp_dr5(&mut self) -> BkpDr5W<BkpDr5Spec> {
BkpDr5W::new(self, 0)
}
}
#[doc = "Backup data register 5\n\nYou can [`read`](crate::Reg::read) this register and get [`bkp_dr5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bkp_dr5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct BkpDr5Spec;
impl crate::RegisterSpec for BkpDr5Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`bkp_dr5::R`](R) reader structure"]
impl crate::Readable for BkpDr5Spec {}
#[doc = "`write(|w| ..)` method takes [`bkp_dr5::W`](W) writer structure"]
impl crate::Writable for BkpDr5Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets BKP_DR5 to value 0"]
impl crate::Resettable for BkpDr5Spec {}
}
#[doc = "BKP_DR6 (rw) register accessor: Backup data register 6\n\nYou can [`read`](crate::Reg::read) this register and get [`bkp_dr6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bkp_dr6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bkp_dr6`] module"]
#[doc(alias = "BKP_DR6")]
pub type BkpDr6 = crate::Reg<bkp_dr6::BkpDr6Spec>;
#[doc = "Backup data register 6"]
pub mod bkp_dr6 {
#[doc = "Register `BKP_DR6` reader"]
pub type R = crate::R<BkpDr6Spec>;
#[doc = "Register `BKP_DR6` writer"]
pub type W = crate::W<BkpDr6Spec>;
#[doc = "Field `BKP_DR6` reader - Backup data register 6"]
pub type BkpDr6R = crate::FieldReader<u16>;
#[doc = "Field `BKP_DR6` writer - Backup data register 6"]
pub type BkpDr6W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - Backup data register 6"]
#[inline(always)]
pub fn bkp_dr6(&self) -> BkpDr6R {
BkpDr6R::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15 - Backup data register 6"]
#[inline(always)]
pub fn bkp_dr6(&mut self) -> BkpDr6W<BkpDr6Spec> {
BkpDr6W::new(self, 0)
}
}
#[doc = "Backup data register 6\n\nYou can [`read`](crate::Reg::read) this register and get [`bkp_dr6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bkp_dr6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct BkpDr6Spec;
impl crate::RegisterSpec for BkpDr6Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`bkp_dr6::R`](R) reader structure"]
impl crate::Readable for BkpDr6Spec {}
#[doc = "`write(|w| ..)` method takes [`bkp_dr6::W`](W) writer structure"]
impl crate::Writable for BkpDr6Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets BKP_DR6 to value 0"]
impl crate::Resettable for BkpDr6Spec {}
}
#[doc = "BKP_DR7 (rw) register accessor: Backup data register 7\n\nYou can [`read`](crate::Reg::read) this register and get [`bkp_dr7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bkp_dr7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bkp_dr7`] module"]
#[doc(alias = "BKP_DR7")]
pub type BkpDr7 = crate::Reg<bkp_dr7::BkpDr7Spec>;
#[doc = "Backup data register 7"]
pub mod bkp_dr7 {
#[doc = "Register `BKP_DR7` reader"]
pub type R = crate::R<BkpDr7Spec>;
#[doc = "Register `BKP_DR7` writer"]
pub type W = crate::W<BkpDr7Spec>;
#[doc = "Field `BKP_DR7` reader - Backup data register 7"]
pub type BkpDr7R = crate::FieldReader<u16>;
#[doc = "Field `BKP_DR7` writer - Backup data register 7"]
pub type BkpDr7W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - Backup data register 7"]
#[inline(always)]
pub fn bkp_dr7(&self) -> BkpDr7R {
BkpDr7R::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15 - Backup data register 7"]
#[inline(always)]
pub fn bkp_dr7(&mut self) -> BkpDr7W<BkpDr7Spec> {
BkpDr7W::new(self, 0)
}
}
#[doc = "Backup data register 7\n\nYou can [`read`](crate::Reg::read) this register and get [`bkp_dr7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bkp_dr7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct BkpDr7Spec;
impl crate::RegisterSpec for BkpDr7Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`bkp_dr7::R`](R) reader structure"]
impl crate::Readable for BkpDr7Spec {}
#[doc = "`write(|w| ..)` method takes [`bkp_dr7::W`](W) writer structure"]
impl crate::Writable for BkpDr7Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets BKP_DR7 to value 0"]
impl crate::Resettable for BkpDr7Spec {}
}
#[doc = "BKP_DR8 (rw) register accessor: Backup data register 8\n\nYou can [`read`](crate::Reg::read) this register and get [`bkp_dr8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bkp_dr8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bkp_dr8`] module"]
#[doc(alias = "BKP_DR8")]
pub type BkpDr8 = crate::Reg<bkp_dr8::BkpDr8Spec>;
#[doc = "Backup data register 8"]
pub mod bkp_dr8 {
#[doc = "Register `BKP_DR8` reader"]
pub type R = crate::R<BkpDr8Spec>;
#[doc = "Register `BKP_DR8` writer"]
pub type W = crate::W<BkpDr8Spec>;
#[doc = "Field `BKP_DR8` reader - Backup data register 8"]
pub type BkpDr8R = crate::FieldReader<u16>;
#[doc = "Field `BKP_DR8` writer - Backup data register 8"]
pub type BkpDr8W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - Backup data register 8"]
#[inline(always)]
pub fn bkp_dr8(&self) -> BkpDr8R {
BkpDr8R::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15 - Backup data register 8"]
#[inline(always)]
pub fn bkp_dr8(&mut self) -> BkpDr8W<BkpDr8Spec> {
BkpDr8W::new(self, 0)
}
}
#[doc = "Backup data register 8\n\nYou can [`read`](crate::Reg::read) this register and get [`bkp_dr8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bkp_dr8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct BkpDr8Spec;
impl crate::RegisterSpec for BkpDr8Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`bkp_dr8::R`](R) reader structure"]
impl crate::Readable for BkpDr8Spec {}
#[doc = "`write(|w| ..)` method takes [`bkp_dr8::W`](W) writer structure"]
impl crate::Writable for BkpDr8Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets BKP_DR8 to value 0"]
impl crate::Resettable for BkpDr8Spec {}
}
#[doc = "BKP_DR9 (rw) register accessor: Backup data register 9\n\nYou can [`read`](crate::Reg::read) this register and get [`bkp_dr9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bkp_dr9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bkp_dr9`] module"]
#[doc(alias = "BKP_DR9")]
pub type BkpDr9 = crate::Reg<bkp_dr9::BkpDr9Spec>;
#[doc = "Backup data register 9"]
pub mod bkp_dr9 {
#[doc = "Register `BKP_DR9` reader"]
pub type R = crate::R<BkpDr9Spec>;
#[doc = "Register `BKP_DR9` writer"]
pub type W = crate::W<BkpDr9Spec>;
#[doc = "Field `BKP_DR9` reader - Backup data register 9"]
pub type BkpDr9R = crate::FieldReader<u16>;
#[doc = "Field `BKP_DR9` writer - Backup data register 9"]
pub type BkpDr9W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - Backup data register 9"]
#[inline(always)]
pub fn bkp_dr9(&self) -> BkpDr9R {
BkpDr9R::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15 - Backup data register 9"]
#[inline(always)]
pub fn bkp_dr9(&mut self) -> BkpDr9W<BkpDr9Spec> {
BkpDr9W::new(self, 0)
}
}
#[doc = "Backup data register 9\n\nYou can [`read`](crate::Reg::read) this register and get [`bkp_dr9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bkp_dr9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct BkpDr9Spec;
impl crate::RegisterSpec for BkpDr9Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`bkp_dr9::R`](R) reader structure"]
impl crate::Readable for BkpDr9Spec {}
#[doc = "`write(|w| ..)` method takes [`bkp_dr9::W`](W) writer structure"]
impl crate::Writable for BkpDr9Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets BKP_DR9 to value 0"]
impl crate::Resettable for BkpDr9Spec {}
}
#[doc = "BKP_DR10 (rw) register accessor: Backup data register 10\n\nYou can [`read`](crate::Reg::read) this register and get [`bkp_dr10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bkp_dr10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bkp_dr10`] module"]
#[doc(alias = "BKP_DR10")]
pub type BkpDr10 = crate::Reg<bkp_dr10::BkpDr10Spec>;
#[doc = "Backup data register 10"]
pub mod bkp_dr10 {
#[doc = "Register `BKP_DR10` reader"]
pub type R = crate::R<BkpDr10Spec>;
#[doc = "Register `BKP_DR10` writer"]
pub type W = crate::W<BkpDr10Spec>;
#[doc = "Field `BKP_DR10` reader - Backup data register 10"]
pub type BkpDr10R = crate::FieldReader<u16>;
#[doc = "Field `BKP_DR10` writer - Backup data register 10"]
pub type BkpDr10W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - Backup data register 10"]
#[inline(always)]
pub fn bkp_dr10(&self) -> BkpDr10R {
BkpDr10R::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15 - Backup data register 10"]
#[inline(always)]
pub fn bkp_dr10(&mut self) -> BkpDr10W<BkpDr10Spec> {
BkpDr10W::new(self, 0)
}
}
#[doc = "Backup data register 10\n\nYou can [`read`](crate::Reg::read) this register and get [`bkp_dr10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bkp_dr10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct BkpDr10Spec;
impl crate::RegisterSpec for BkpDr10Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`bkp_dr10::R`](R) reader structure"]
impl crate::Readable for BkpDr10Spec {}
#[doc = "`write(|w| ..)` method takes [`bkp_dr10::W`](W) writer structure"]
impl crate::Writable for BkpDr10Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets BKP_DR10 to value 0"]
impl crate::Resettable for BkpDr10Spec {}
}
#[doc = "BKP_DR11 (rw) register accessor: Backup data register 11\n\nYou can [`read`](crate::Reg::read) this register and get [`bkp_dr11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bkp_dr11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bkp_dr11`] module"]
#[doc(alias = "BKP_DR11")]
pub type BkpDr11 = crate::Reg<bkp_dr11::BkpDr11Spec>;
#[doc = "Backup data register 11"]
pub mod bkp_dr11 {
#[doc = "Register `BKP_DR11` reader"]
pub type R = crate::R<BkpDr11Spec>;
#[doc = "Register `BKP_DR11` writer"]
pub type W = crate::W<BkpDr11Spec>;
#[doc = "Field `BKP_DR11` reader - Backup data register 11"]
pub type BkpDr11R = crate::FieldReader<u16>;
#[doc = "Field `BKP_DR11` writer - Backup data register 11"]
pub type BkpDr11W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - Backup data register 11"]
#[inline(always)]
pub fn bkp_dr11(&self) -> BkpDr11R {
BkpDr11R::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15 - Backup data register 11"]
#[inline(always)]
pub fn bkp_dr11(&mut self) -> BkpDr11W<BkpDr11Spec> {
BkpDr11W::new(self, 0)
}
}
#[doc = "Backup data register 11\n\nYou can [`read`](crate::Reg::read) this register and get [`bkp_dr11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bkp_dr11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct BkpDr11Spec;
impl crate::RegisterSpec for BkpDr11Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`bkp_dr11::R`](R) reader structure"]
impl crate::Readable for BkpDr11Spec {}
#[doc = "`write(|w| ..)` method takes [`bkp_dr11::W`](W) writer structure"]
impl crate::Writable for BkpDr11Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets BKP_DR11 to value 0"]
impl crate::Resettable for BkpDr11Spec {}
}
#[doc = "BKP_DR12 (rw) register accessor: Backup data register 12\n\nYou can [`read`](crate::Reg::read) this register and get [`bkp_dr12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bkp_dr12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bkp_dr12`] module"]
#[doc(alias = "BKP_DR12")]
pub type BkpDr12 = crate::Reg<bkp_dr12::BkpDr12Spec>;
#[doc = "Backup data register 12"]
pub mod bkp_dr12 {
#[doc = "Register `BKP_DR12` reader"]
pub type R = crate::R<BkpDr12Spec>;
#[doc = "Register `BKP_DR12` writer"]
pub type W = crate::W<BkpDr12Spec>;
#[doc = "Field `BKP_DR12` reader - Backup data register 12"]
pub type BkpDr12R = crate::FieldReader<u16>;
#[doc = "Field `BKP_DR12` writer - Backup data register 12"]
pub type BkpDr12W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - Backup data register 12"]
#[inline(always)]
pub fn bkp_dr12(&self) -> BkpDr12R {
BkpDr12R::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15 - Backup data register 12"]
#[inline(always)]
pub fn bkp_dr12(&mut self) -> BkpDr12W<BkpDr12Spec> {
BkpDr12W::new(self, 0)
}
}
#[doc = "Backup data register 12\n\nYou can [`read`](crate::Reg::read) this register and get [`bkp_dr12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bkp_dr12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct BkpDr12Spec;
impl crate::RegisterSpec for BkpDr12Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`bkp_dr12::R`](R) reader structure"]
impl crate::Readable for BkpDr12Spec {}
#[doc = "`write(|w| ..)` method takes [`bkp_dr12::W`](W) writer structure"]
impl crate::Writable for BkpDr12Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets BKP_DR12 to value 0"]
impl crate::Resettable for BkpDr12Spec {}
}
#[doc = "BKP_DR13 (rw) register accessor: Backup data register 13\n\nYou can [`read`](crate::Reg::read) this register and get [`bkp_dr13::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bkp_dr13::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bkp_dr13`] module"]
#[doc(alias = "BKP_DR13")]
pub type BkpDr13 = crate::Reg<bkp_dr13::BkpDr13Spec>;
#[doc = "Backup data register 13"]
pub mod bkp_dr13 {
#[doc = "Register `BKP_DR13` reader"]
pub type R = crate::R<BkpDr13Spec>;
#[doc = "Register `BKP_DR13` writer"]
pub type W = crate::W<BkpDr13Spec>;
#[doc = "Field `BKP_DR13` reader - Backup data register 13"]
pub type BkpDr13R = crate::FieldReader<u16>;
#[doc = "Field `BKP_DR13` writer - Backup data register 13"]
pub type BkpDr13W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - Backup data register 13"]
#[inline(always)]
pub fn bkp_dr13(&self) -> BkpDr13R {
BkpDr13R::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15 - Backup data register 13"]
#[inline(always)]
pub fn bkp_dr13(&mut self) -> BkpDr13W<BkpDr13Spec> {
BkpDr13W::new(self, 0)
}
}
#[doc = "Backup data register 13\n\nYou can [`read`](crate::Reg::read) this register and get [`bkp_dr13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bkp_dr13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct BkpDr13Spec;
impl crate::RegisterSpec for BkpDr13Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`bkp_dr13::R`](R) reader structure"]
impl crate::Readable for BkpDr13Spec {}
#[doc = "`write(|w| ..)` method takes [`bkp_dr13::W`](W) writer structure"]
impl crate::Writable for BkpDr13Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets BKP_DR13 to value 0"]
impl crate::Resettable for BkpDr13Spec {}
}
#[doc = "BKP_DR14 (rw) register accessor: Backup data register 14\n\nYou can [`read`](crate::Reg::read) this register and get [`bkp_dr14::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bkp_dr14::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bkp_dr14`] module"]
#[doc(alias = "BKP_DR14")]
pub type BkpDr14 = crate::Reg<bkp_dr14::BkpDr14Spec>;
#[doc = "Backup data register 14"]
pub mod bkp_dr14 {
#[doc = "Register `BKP_DR14` reader"]
pub type R = crate::R<BkpDr14Spec>;
#[doc = "Register `BKP_DR14` writer"]
pub type W = crate::W<BkpDr14Spec>;
#[doc = "Field `BKP_DR14` reader - Backup data register 14"]
pub type BkpDr14R = crate::FieldReader<u16>;
#[doc = "Field `BKP_DR14` writer - Backup data register 14"]
pub type BkpDr14W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - Backup data register 14"]
#[inline(always)]
pub fn bkp_dr14(&self) -> BkpDr14R {
BkpDr14R::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15 - Backup data register 14"]
#[inline(always)]
pub fn bkp_dr14(&mut self) -> BkpDr14W<BkpDr14Spec> {
BkpDr14W::new(self, 0)
}
}
#[doc = "Backup data register 14\n\nYou can [`read`](crate::Reg::read) this register and get [`bkp_dr14::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bkp_dr14::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct BkpDr14Spec;
impl crate::RegisterSpec for BkpDr14Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`bkp_dr14::R`](R) reader structure"]
impl crate::Readable for BkpDr14Spec {}
#[doc = "`write(|w| ..)` method takes [`bkp_dr14::W`](W) writer structure"]
impl crate::Writable for BkpDr14Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets BKP_DR14 to value 0"]
impl crate::Resettable for BkpDr14Spec {}
}
#[doc = "BKP_DR15 (rw) register accessor: Backup data register 15\n\nYou can [`read`](crate::Reg::read) this register and get [`bkp_dr15::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bkp_dr15::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bkp_dr15`] module"]
#[doc(alias = "BKP_DR15")]
pub type BkpDr15 = crate::Reg<bkp_dr15::BkpDr15Spec>;
#[doc = "Backup data register 15"]
pub mod bkp_dr15 {
#[doc = "Register `BKP_DR15` reader"]
pub type R = crate::R<BkpDr15Spec>;
#[doc = "Register `BKP_DR15` writer"]
pub type W = crate::W<BkpDr15Spec>;
#[doc = "Field `BKP_DR15` reader - Backup data register 15"]
pub type BkpDr15R = crate::FieldReader<u16>;
#[doc = "Field `BKP_DR15` writer - Backup data register 15"]
pub type BkpDr15W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - Backup data register 15"]
#[inline(always)]
pub fn bkp_dr15(&self) -> BkpDr15R {
BkpDr15R::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15 - Backup data register 15"]
#[inline(always)]
pub fn bkp_dr15(&mut self) -> BkpDr15W<BkpDr15Spec> {
BkpDr15W::new(self, 0)
}
}
#[doc = "Backup data register 15\n\nYou can [`read`](crate::Reg::read) this register and get [`bkp_dr15::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bkp_dr15::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct BkpDr15Spec;
impl crate::RegisterSpec for BkpDr15Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`bkp_dr15::R`](R) reader structure"]
impl crate::Readable for BkpDr15Spec {}
#[doc = "`write(|w| ..)` method takes [`bkp_dr15::W`](W) writer structure"]
impl crate::Writable for BkpDr15Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets BKP_DR15 to value 0"]
impl crate::Resettable for BkpDr15Spec {}
}
}
#[doc = "System control"]
pub type Sys = crate::Periph<sys::RegisterBlock, 0x0300_0000>;
impl core::fmt::Debug for Sys {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Sys").finish()
}
}
#[doc = "System control"]
pub mod sys {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
boot_mode: BootMode,
rst_cntl: RstCntl,
pwr_cntl: PwrCntl,
clk_cntl: ClkCntl,
bus_cntl: BusCntl,
swj_cntl: SwjCntl,
misc_cntl: MiscCntl,
dbg_cntl: DbgCntl,
wkp_rise_trg: WkpRiseTrg,
wkp_fall_trg: WkpFallTrg,
wkp_pending: WkpPending,
_reserved11: [u8; 0x04],
mtime_psc: MtimePsc,
mtime_psc_cnt: MtimePscCnt,
pbus_div: PbusDiv,
_reserved14: [u8; 0x04],
apb_rst: ApbRst,
_reserved15: [u8; 0x0c],
ahb_rst: AhbRst,
_reserved16: [u8; 0x0c],
apb_clk_en: ApbClkEn,
_reserved17: [u8; 0x0c],
ahb_clk_en: AhbClkEn,
_reserved18: [u8; 0x0c],
apb_clk_stop: ApbClkStop,
_reserved19: [u8; 0x7c],
device_id: DeviceId,
}
impl RegisterBlock {
#[doc = "0x00 - Boot mode"]
#[inline(always)]
pub const fn boot_mode(&self) -> &BootMode {
&self.boot_mode
}
#[doc = "0x04 - Reset control register"]
#[inline(always)]
pub const fn rst_cntl(&self) -> &RstCntl {
&self.rst_cntl
}
#[doc = "0x08 - Power control register"]
#[inline(always)]
pub const fn pwr_cntl(&self) -> &PwrCntl {
&self.pwr_cntl
}
#[doc = "0x0c - Clock control register"]
#[inline(always)]
pub const fn clk_cntl(&self) -> &ClkCntl {
&self.clk_cntl
}
#[doc = "0x10 - Bus control register"]
#[inline(always)]
pub const fn bus_cntl(&self) -> &BusCntl {
&self.bus_cntl
}
#[doc = "0x14 - SWJ pin control register"]
#[inline(always)]
pub const fn swj_cntl(&self) -> &SwjCntl {
&self.swj_cntl
}
#[doc = "0x18 - Miscellaneous control register"]
#[inline(always)]
pub const fn misc_cntl(&self) -> &MiscCntl {
&self.misc_cntl
}
#[doc = "0x1c - Debug control register"]
#[inline(always)]
pub const fn dbg_cntl(&self) -> &DbgCntl {
&self.dbg_cntl
}
#[doc = "0x20 - Wake up rise triggers"]
#[inline(always)]
pub const fn wkp_rise_trg(&self) -> &WkpRiseTrg {
&self.wkp_rise_trg
}
#[doc = "0x24 - Wake up fall triggers"]
#[inline(always)]
pub const fn wkp_fall_trg(&self) -> &WkpFallTrg {
&self.wkp_fall_trg
}
#[doc = "0x28 - Wake up pending register"]
#[inline(always)]
pub const fn wkp_pending(&self) -> &WkpPending {
&self.wkp_pending
}
#[doc = "0x30 - Mtime prescaler value"]
#[inline(always)]
pub const fn mtime_psc(&self) -> &MtimePsc {
&self.mtime_psc
}
#[doc = "0x34 - Mtime prescaler counter"]
#[inline(always)]
pub const fn mtime_psc_cnt(&self) -> &MtimePscCnt {
&self.mtime_psc_cnt
}
#[doc = "0x38 - Pbus clock divider"]
#[inline(always)]
pub const fn pbus_div(&self) -> &PbusDiv {
&self.pbus_div
}
#[doc = "0x40 - APB peripheral reset"]
#[inline(always)]
pub const fn apb_rst(&self) -> &ApbRst {
&self.apb_rst
}
#[doc = "0x50 - AHB peripheral reset"]
#[inline(always)]
pub const fn ahb_rst(&self) -> &AhbRst {
&self.ahb_rst
}
#[doc = "0x60 - APB peripheral clock enable"]
#[inline(always)]
pub const fn apb_clk_en(&self) -> &ApbClkEn {
&self.apb_clk_en
}
#[doc = "0x70 - AHB peripheral clock enable"]
#[inline(always)]
pub const fn ahb_clk_en(&self) -> &AhbClkEn {
&self.ahb_clk_en
}
#[doc = "0x80 - APB peripheral clock stop during debug"]
#[inline(always)]
pub const fn apb_clk_stop(&self) -> &ApbClkStop {
&self.apb_clk_stop
}
#[doc = "0x100 - Device ID code"]
#[inline(always)]
pub const fn device_id(&self) -> &DeviceId {
&self.device_id
}
}
#[doc = "BOOT_MODE (r) register accessor: Boot mode\n\nYou can [`read`](crate::Reg::read) this register and get [`boot_mode::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@boot_mode`] module"]
#[doc(alias = "BOOT_MODE")]
pub type BootMode = crate::Reg<boot_mode::BootModeSpec>;
#[doc = "Boot mode"]
pub mod boot_mode {
#[doc = "Register `BOOT_MODE` reader"]
pub type R = crate::R<BootModeSpec>;
#[doc = "Field `BOOT_MODE` reader - Boot mode"]
pub type BootModeR = crate::FieldReader;
impl R {
#[doc = "Bits 0:1 - Boot mode"]
#[inline(always)]
pub fn boot_mode(&self) -> BootModeR {
BootModeR::new((self.bits & 3) as u8)
}
}
#[doc = "Boot mode\n\nYou can [`read`](crate::Reg::read) this register and get [`boot_mode::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct BootModeSpec;
impl crate::RegisterSpec for BootModeSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`boot_mode::R`](R) reader structure"]
impl crate::Readable for BootModeSpec {}
#[doc = "`reset()` method sets BOOT_MODE to value 0"]
impl crate::Resettable for BootModeSpec {}
}
#[doc = "RST_CNTL (rw) register accessor: Reset control register\n\nYou can [`read`](crate::Reg::read) this register and get [`rst_cntl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rst_cntl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rst_cntl`] module"]
#[doc(alias = "RST_CNTL")]
pub type RstCntl = crate::Reg<rst_cntl::RstCntlSpec>;
#[doc = "Reset control register"]
pub mod rst_cntl {
#[doc = "Register `RST_CNTL` reader"]
pub type R = crate::R<RstCntlSpec>;
#[doc = "Register `RST_CNTL` writer"]
pub type W = crate::W<RstCntlSpec>;
#[doc = "Field `SFT_RST` reader - Software reset"]
pub type SftRstR = crate::BitReader;
#[doc = "Field `SFT_RST` writer - Software reset"]
pub type SftRstW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EXT_RST_EN` reader - External reset enable"]
pub type ExtRstEnR = crate::BitReader;
#[doc = "Field `EXT_RST_EN` writer - External reset enable"]
pub type ExtRstEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `FCB_RST_DIS` reader - FCB reset disable"]
pub type FcbRstDisR = crate::BitReader;
#[doc = "Field `FCB_RST_DIS` writer - FCB reset disable"]
pub type FcbRstDisW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `REMOVE_RST` writer - Remove reset flags"]
pub type RemoveRstW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EXT_RST_FLAG` reader - External reset flag"]
pub type ExtRstFlagR = crate::BitReader;
#[doc = "Field `PIN_RST_FLAG` reader - Pin reset flag"]
pub type PinRstFlagR = crate::BitReader;
#[doc = "Field `POR_RST_FLAG` reader - Power on reset flag"]
pub type PorRstFlagR = crate::BitReader;
#[doc = "Field `SFT_RST_FLAG` reader - Software reset flag"]
pub type SftRstFlagR = crate::BitReader;
#[doc = "Field `IWDG_RST_FLAG` reader - IWDG reset flag"]
pub type IwdgRstFlagR = crate::BitReader;
#[doc = "Field `WDOG_RST_FLAG` reader - Watch dog reset flag"]
pub type WdogRstFlagR = crate::BitReader;
#[doc = "Field `LP_RST_FLAG` reader - Low power reset flag"]
pub type LpRstFlagR = crate::BitReader;
impl R {
#[doc = "Bit 0 - Software reset"]
#[inline(always)]
pub fn sft_rst(&self) -> SftRstR {
SftRstR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - External reset enable"]
#[inline(always)]
pub fn ext_rst_en(&self) -> ExtRstEnR {
ExtRstEnR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - FCB reset disable"]
#[inline(always)]
pub fn fcb_rst_dis(&self) -> FcbRstDisR {
FcbRstDisR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 25 - External reset flag"]
#[inline(always)]
pub fn ext_rst_flag(&self) -> ExtRstFlagR {
ExtRstFlagR::new(((self.bits >> 25) & 1) != 0)
}
#[doc = "Bit 26 - Pin reset flag"]
#[inline(always)]
pub fn pin_rst_flag(&self) -> PinRstFlagR {
PinRstFlagR::new(((self.bits >> 26) & 1) != 0)
}
#[doc = "Bit 27 - Power on reset flag"]
#[inline(always)]
pub fn por_rst_flag(&self) -> PorRstFlagR {
PorRstFlagR::new(((self.bits >> 27) & 1) != 0)
}
#[doc = "Bit 28 - Software reset flag"]
#[inline(always)]
pub fn sft_rst_flag(&self) -> SftRstFlagR {
SftRstFlagR::new(((self.bits >> 28) & 1) != 0)
}
#[doc = "Bit 29 - IWDG reset flag"]
#[inline(always)]
pub fn iwdg_rst_flag(&self) -> IwdgRstFlagR {
IwdgRstFlagR::new(((self.bits >> 29) & 1) != 0)
}
#[doc = "Bit 30 - Watch dog reset flag"]
#[inline(always)]
pub fn wdog_rst_flag(&self) -> WdogRstFlagR {
WdogRstFlagR::new(((self.bits >> 30) & 1) != 0)
}
#[doc = "Bit 31 - Low power reset flag"]
#[inline(always)]
pub fn lp_rst_flag(&self) -> LpRstFlagR {
LpRstFlagR::new(((self.bits >> 31) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Software reset"]
#[inline(always)]
pub fn sft_rst(&mut self) -> SftRstW<RstCntlSpec> {
SftRstW::new(self, 0)
}
#[doc = "Bit 1 - External reset enable"]
#[inline(always)]
pub fn ext_rst_en(&mut self) -> ExtRstEnW<RstCntlSpec> {
ExtRstEnW::new(self, 1)
}
#[doc = "Bit 2 - FCB reset disable"]
#[inline(always)]
pub fn fcb_rst_dis(&mut self) -> FcbRstDisW<RstCntlSpec> {
FcbRstDisW::new(self, 2)
}
#[doc = "Bit 24 - Remove reset flags"]
#[inline(always)]
pub fn remove_rst(&mut self) -> RemoveRstW<RstCntlSpec> {
RemoveRstW::new(self, 24)
}
}
#[doc = "Reset control register\n\nYou can [`read`](crate::Reg::read) this register and get [`rst_cntl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rst_cntl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RstCntlSpec;
impl crate::RegisterSpec for RstCntlSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rst_cntl::R`](R) reader structure"]
impl crate::Readable for RstCntlSpec {}
#[doc = "`write(|w| ..)` method takes [`rst_cntl::W`](W) writer structure"]
impl crate::Writable for RstCntlSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets RST_CNTL to value 0"]
impl crate::Resettable for RstCntlSpec {}
}
#[doc = "PWR_CNTL (rw) register accessor: Power control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pwr_cntl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwr_cntl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwr_cntl`] module"]
#[doc(alias = "PWR_CNTL")]
pub type PwrCntl = crate::Reg<pwr_cntl::PwrCntlSpec>;
#[doc = "Power control register"]
pub mod pwr_cntl {
#[doc = "Register `PWR_CNTL` reader"]
pub type R = crate::R<PwrCntlSpec>;
#[doc = "Register `PWR_CNTL` writer"]
pub type W = crate::W<PwrCntlSpec>;
#[doc = "Field `SLEEP_DEEP` reader - Stop mode enable"]
pub type SleepDeepR = crate::BitReader;
#[doc = "Field `SLEEP_DEEP` writer - Stop mode enable"]
pub type SleepDeepW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `POWER_DOWN` reader - Standy mode enable"]
pub type PowerDownR = crate::BitReader;
#[doc = "Field `POWER_DOWN` writer - Standy mode enable"]
pub type PowerDownW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - Stop mode enable"]
#[inline(always)]
pub fn sleep_deep(&self) -> SleepDeepR {
SleepDeepR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Standy mode enable"]
#[inline(always)]
pub fn power_down(&self) -> PowerDownR {
PowerDownR::new(((self.bits >> 1) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Stop mode enable"]
#[inline(always)]
pub fn sleep_deep(&mut self) -> SleepDeepW<PwrCntlSpec> {
SleepDeepW::new(self, 0)
}
#[doc = "Bit 1 - Standy mode enable"]
#[inline(always)]
pub fn power_down(&mut self) -> PowerDownW<PwrCntlSpec> {
PowerDownW::new(self, 1)
}
}
#[doc = "Power control register\n\nYou can [`read`](crate::Reg::read) this register and get [`pwr_cntl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwr_cntl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PwrCntlSpec;
impl crate::RegisterSpec for PwrCntlSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`pwr_cntl::R`](R) reader structure"]
impl crate::Readable for PwrCntlSpec {}
#[doc = "`write(|w| ..)` method takes [`pwr_cntl::W`](W) writer structure"]
impl crate::Writable for PwrCntlSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets PWR_CNTL to value 0"]
impl crate::Resettable for PwrCntlSpec {}
}
#[doc = "CLK_CNTL (rw) register accessor: Clock control register\n\nYou can [`read`](crate::Reg::read) this register and get [`clk_cntl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_cntl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_cntl`] module"]
#[doc(alias = "CLK_CNTL")]
pub type ClkCntl = crate::Reg<clk_cntl::ClkCntlSpec>;
#[doc = "Clock control register"]
pub mod clk_cntl {
#[doc = "Register `CLK_CNTL` reader"]
pub type R = crate::R<ClkCntlSpec>;
#[doc = "Register `CLK_CNTL` writer"]
pub type W = crate::W<ClkCntlSpec>;
#[doc = "Clock source\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum ClkSource {
#[doc = "0: HSI"]
Hsi = 0,
#[doc = "1: HSE"]
Hse = 1,
#[doc = "2: PLL"]
Pll = 2,
#[doc = "3: External"]
External = 3,
}
impl From<ClkSource> for u8 {
#[inline(always)]
fn from(variant: ClkSource) -> Self {
variant as _
}
}
impl crate::FieldSpec for ClkSource {
type Ux = u8;
}
impl crate::IsEnum for ClkSource {}
#[doc = "Field `CLK_SOURCE` reader - Clock source"]
pub type ClkSourceR = crate::FieldReader<ClkSource>;
impl ClkSourceR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> ClkSource {
match self.bits {
0 => ClkSource::Hsi,
1 => ClkSource::Hse,
2 => ClkSource::Pll,
3 => ClkSource::External,
_ => unreachable!(),
}
}
#[doc = "HSI"]
#[inline(always)]
pub fn is_hsi(&self) -> bool {
*self == ClkSource::Hsi
}
#[doc = "HSE"]
#[inline(always)]
pub fn is_hse(&self) -> bool {
*self == ClkSource::Hse
}
#[doc = "PLL"]
#[inline(always)]
pub fn is_pll(&self) -> bool {
*self == ClkSource::Pll
}
#[doc = "External"]
#[inline(always)]
pub fn is_external(&self) -> bool {
*self == ClkSource::External
}
}
#[doc = "Field `CLK_SOURCE` writer - Clock source"]
pub type ClkSourceW<'a, REG> = crate::FieldWriter<'a, REG, 2, ClkSource, crate::Safe>;
impl<'a, REG> ClkSourceW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "HSI"]
#[inline(always)]
pub fn hsi(self) -> &'a mut crate::W<REG> {
self.variant(ClkSource::Hsi)
}
#[doc = "HSE"]
#[inline(always)]
pub fn hse(self) -> &'a mut crate::W<REG> {
self.variant(ClkSource::Hse)
}
#[doc = "PLL"]
#[inline(always)]
pub fn pll(self) -> &'a mut crate::W<REG> {
self.variant(ClkSource::Pll)
}
#[doc = "External"]
#[inline(always)]
pub fn external(self) -> &'a mut crate::W<REG> {
self.variant(ClkSource::External)
}
}
#[doc = "Field `HSE_ON` reader - HSE clock enable"]
pub type HseOnR = crate::BitReader;
#[doc = "Field `HSE_ON` writer - HSE clock enable"]
pub type HseOnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `HSE_BYP` reader - HSE clock bypass"]
pub type HseBypR = crate::BitReader;
#[doc = "Field `HSE_BYP` writer - HSE clock bypass"]
pub type HseBypW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `HSE_RDY` reader - HSE clock ready"]
pub type HseRdyR = crate::BitReader;
#[doc = "Field `PLL_ON` reader - PLL clock enable"]
pub type PllOnR = crate::BitReader;
#[doc = "Field `PLL_ON` writer - PLL clock enable"]
pub type PllOnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PLL_RDY` reader - PLL clock ready"]
pub type PllRdyR = crate::BitReader;
#[doc = "Field `SCLK_DIV` reader - Sclk divider"]
pub type SclkDivR = crate::FieldReader;
#[doc = "Field `SCLK_DIV` writer - Sclk divider"]
pub type SclkDivW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:1 - Clock source"]
#[inline(always)]
pub fn clk_source(&self) -> ClkSourceR {
ClkSourceR::new((self.bits & 3) as u8)
}
#[doc = "Bit 2 - HSE clock enable"]
#[inline(always)]
pub fn hse_on(&self) -> HseOnR {
HseOnR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - HSE clock bypass"]
#[inline(always)]
pub fn hse_byp(&self) -> HseBypR {
HseBypR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - HSE clock ready"]
#[inline(always)]
pub fn hse_rdy(&self) -> HseRdyR {
HseRdyR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - PLL clock enable"]
#[inline(always)]
pub fn pll_on(&self) -> PllOnR {
PllOnR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - PLL clock ready"]
#[inline(always)]
pub fn pll_rdy(&self) -> PllRdyR {
PllRdyR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bits 8:15 - Sclk divider"]
#[inline(always)]
pub fn sclk_div(&self) -> SclkDivR {
SclkDivR::new(((self.bits >> 8) & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:1 - Clock source"]
#[inline(always)]
pub fn clk_source(&mut self) -> ClkSourceW<ClkCntlSpec> {
ClkSourceW::new(self, 0)
}
#[doc = "Bit 2 - HSE clock enable"]
#[inline(always)]
pub fn hse_on(&mut self) -> HseOnW<ClkCntlSpec> {
HseOnW::new(self, 2)
}
#[doc = "Bit 3 - HSE clock bypass"]
#[inline(always)]
pub fn hse_byp(&mut self) -> HseBypW<ClkCntlSpec> {
HseBypW::new(self, 3)
}
#[doc = "Bit 5 - PLL clock enable"]
#[inline(always)]
pub fn pll_on(&mut self) -> PllOnW<ClkCntlSpec> {
PllOnW::new(self, 5)
}
#[doc = "Bits 8:15 - Sclk divider"]
#[inline(always)]
pub fn sclk_div(&mut self) -> SclkDivW<ClkCntlSpec> {
SclkDivW::new(self, 8)
}
}
#[doc = "Clock control register\n\nYou can [`read`](crate::Reg::read) this register and get [`clk_cntl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_cntl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ClkCntlSpec;
impl crate::RegisterSpec for ClkCntlSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`clk_cntl::R`](R) reader structure"]
impl crate::Readable for ClkCntlSpec {}
#[doc = "`write(|w| ..)` method takes [`clk_cntl::W`](W) writer structure"]
impl crate::Writable for ClkCntlSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets CLK_CNTL to value 0"]
impl crate::Resettable for ClkCntlSpec {}
}
#[doc = "BUS_CNTL (rw) register accessor: Bus control register\n\nYou can [`read`](crate::Reg::read) this register and get [`bus_cntl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bus_cntl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bus_cntl`] module"]
#[doc(alias = "BUS_CNTL")]
pub type BusCntl = crate::Reg<bus_cntl::BusCntlSpec>;
#[doc = "Bus control register"]
pub mod bus_cntl {
#[doc = "Register `BUS_CNTL` reader"]
pub type R = crate::R<BusCntlSpec>;
#[doc = "Register `BUS_CNTL` writer"]
pub type W = crate::W<BusCntlSpec>;
#[doc = "Field `EXT_AHB_SEL` reader - External AHB select"]
pub type ExtAhbSelR = crate::BitReader;
#[doc = "Field `EXT_AHB_SEL` writer - External AHB select"]
pub type ExtAhbSelW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - External AHB select"]
#[inline(always)]
pub fn ext_ahb_sel(&self) -> ExtAhbSelR {
ExtAhbSelR::new((self.bits & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - External AHB select"]
#[inline(always)]
pub fn ext_ahb_sel(&mut self) -> ExtAhbSelW<BusCntlSpec> {
ExtAhbSelW::new(self, 0)
}
}
#[doc = "Bus control register\n\nYou can [`read`](crate::Reg::read) this register and get [`bus_cntl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bus_cntl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct BusCntlSpec;
impl crate::RegisterSpec for BusCntlSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`bus_cntl::R`](R) reader structure"]
impl crate::Readable for BusCntlSpec {}
#[doc = "`write(|w| ..)` method takes [`bus_cntl::W`](W) writer structure"]
impl crate::Writable for BusCntlSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets BUS_CNTL to value 0"]
impl crate::Resettable for BusCntlSpec {}
}
#[doc = "SWJ_CNTL (rw) register accessor: SWJ pin control register\n\nYou can [`read`](crate::Reg::read) this register and get [`swj_cntl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`swj_cntl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@swj_cntl`] module"]
#[doc(alias = "SWJ_CNTL")]
pub type SwjCntl = crate::Reg<swj_cntl::SwjCntlSpec>;
#[doc = "SWJ pin control register"]
pub mod swj_cntl {
#[doc = "Register `SWJ_CNTL` reader"]
pub type R = crate::R<SwjCntlSpec>;
#[doc = "Register `SWJ_CNTL` writer"]
pub type W = crate::W<SwjCntlSpec>;
#[doc = "Field `SWJ_JTCK_DIS` reader - Disable JTCK pin and use it as GPIO"]
pub type SwjJtckDisR = crate::BitReader;
#[doc = "Field `SWJ_JTCK_DIS` writer - Disable JTCK pin and use it as GPIO"]
pub type SwjJtckDisW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SWJ_JTMS_DIS` reader - Disable JTMS pin and use it as GPIO"]
pub type SwjJtmsDisR = crate::BitReader;
#[doc = "Field `SWJ_JTMS_DIS` writer - Disable JTMS pin and use it as GPIO"]
pub type SwjJtmsDisW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SWJ_JTDI_DIS` reader - Disable JTDI pin and use it as GPIO"]
pub type SwjJtdiDisR = crate::BitReader;
#[doc = "Field `SWJ_JTDI_DIS` writer - Disable JTDI pin and use it as GPIO"]
pub type SwjJtdiDisW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SWJ_JTDO_DIS` reader - Disable JTDO pin and use it as GPIO"]
pub type SwjJtdoDisR = crate::BitReader;
#[doc = "Field `SWJ_JTDO_DIS` writer - Disable JTDO pin and use it as GPIO"]
pub type SwjJtdoDisW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SWJ_NJTRST_DIS` reader - Disable NJTRST pin and use it as GPIO"]
pub type SwjNjtrstDisR = crate::BitReader;
#[doc = "Field `SWJ_NJTRST_DIS` writer - Disable NJTRST pin and use it as GPIO"]
pub type SwjNjtrstDisW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - Disable JTCK pin and use it as GPIO"]
#[inline(always)]
pub fn swj_jtck_dis(&self) -> SwjJtckDisR {
SwjJtckDisR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Disable JTMS pin and use it as GPIO"]
#[inline(always)]
pub fn swj_jtms_dis(&self) -> SwjJtmsDisR {
SwjJtmsDisR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Disable JTDI pin and use it as GPIO"]
#[inline(always)]
pub fn swj_jtdi_dis(&self) -> SwjJtdiDisR {
SwjJtdiDisR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Disable JTDO pin and use it as GPIO"]
#[inline(always)]
pub fn swj_jtdo_dis(&self) -> SwjJtdoDisR {
SwjJtdoDisR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Disable NJTRST pin and use it as GPIO"]
#[inline(always)]
pub fn swj_njtrst_dis(&self) -> SwjNjtrstDisR {
SwjNjtrstDisR::new(((self.bits >> 4) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Disable JTCK pin and use it as GPIO"]
#[inline(always)]
pub fn swj_jtck_dis(&mut self) -> SwjJtckDisW<SwjCntlSpec> {
SwjJtckDisW::new(self, 0)
}
#[doc = "Bit 1 - Disable JTMS pin and use it as GPIO"]
#[inline(always)]
pub fn swj_jtms_dis(&mut self) -> SwjJtmsDisW<SwjCntlSpec> {
SwjJtmsDisW::new(self, 1)
}
#[doc = "Bit 2 - Disable JTDI pin and use it as GPIO"]
#[inline(always)]
pub fn swj_jtdi_dis(&mut self) -> SwjJtdiDisW<SwjCntlSpec> {
SwjJtdiDisW::new(self, 2)
}
#[doc = "Bit 3 - Disable JTDO pin and use it as GPIO"]
#[inline(always)]
pub fn swj_jtdo_dis(&mut self) -> SwjJtdoDisW<SwjCntlSpec> {
SwjJtdoDisW::new(self, 3)
}
#[doc = "Bit 4 - Disable NJTRST pin and use it as GPIO"]
#[inline(always)]
pub fn swj_njtrst_dis(&mut self) -> SwjNjtrstDisW<SwjCntlSpec> {
SwjNjtrstDisW::new(self, 4)
}
}
#[doc = "SWJ pin control register\n\nYou can [`read`](crate::Reg::read) this register and get [`swj_cntl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`swj_cntl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SwjCntlSpec;
impl crate::RegisterSpec for SwjCntlSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`swj_cntl::R`](R) reader structure"]
impl crate::Readable for SwjCntlSpec {}
#[doc = "`write(|w| ..)` method takes [`swj_cntl::W`](W) writer structure"]
impl crate::Writable for SwjCntlSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets SWJ_CNTL to value 0"]
impl crate::Resettable for SwjCntlSpec {}
}
#[doc = "MISC_CNTL (rw) register accessor: Miscellaneous control register\n\nYou can [`read`](crate::Reg::read) this register and get [`misc_cntl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`misc_cntl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@misc_cntl`] module"]
#[doc(alias = "MISC_CNTL")]
pub type MiscCntl = crate::Reg<misc_cntl::MiscCntlSpec>;
#[doc = "Miscellaneous control register"]
pub mod misc_cntl {
#[doc = "Register `MISC_CNTL` reader"]
pub type R = crate::R<MiscCntlSpec>;
#[doc = "Register `MISC_CNTL` writer"]
pub type W = crate::W<MiscCntlSpec>;
#[doc = "Field `OSC_CNTL` reader - Oscillator control"]
pub type OscCntlR = crate::FieldReader;
#[doc = "Field `OSC_CNTL` writer - Oscillator control"]
pub type OscCntlW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `VOL_CNTL` reader - Voltage control"]
pub type VolCntlR = crate::BitReader;
#[doc = "Field `VOL_CNTL` writer - Voltage control"]
pub type VolCntlW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:3 - Oscillator control"]
#[inline(always)]
pub fn osc_cntl(&self) -> OscCntlR {
OscCntlR::new((self.bits & 0x0f) as u8)
}
#[doc = "Bit 4 - Voltage control"]
#[inline(always)]
pub fn vol_cntl(&self) -> VolCntlR {
VolCntlR::new(((self.bits >> 4) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:3 - Oscillator control"]
#[inline(always)]
pub fn osc_cntl(&mut self) -> OscCntlW<MiscCntlSpec> {
OscCntlW::new(self, 0)
}
#[doc = "Bit 4 - Voltage control"]
#[inline(always)]
pub fn vol_cntl(&mut self) -> VolCntlW<MiscCntlSpec> {
VolCntlW::new(self, 4)
}
}
#[doc = "Miscellaneous control register\n\nYou can [`read`](crate::Reg::read) this register and get [`misc_cntl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`misc_cntl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MiscCntlSpec;
impl crate::RegisterSpec for MiscCntlSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`misc_cntl::R`](R) reader structure"]
impl crate::Readable for MiscCntlSpec {}
#[doc = "`write(|w| ..)` method takes [`misc_cntl::W`](W) writer structure"]
impl crate::Writable for MiscCntlSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets MISC_CNTL to value 0"]
impl crate::Resettable for MiscCntlSpec {}
}
#[doc = "DBG_CNTL (rw) register accessor: Debug control register\n\nYou can [`read`](crate::Reg::read) this register and get [`dbg_cntl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dbg_cntl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dbg_cntl`] module"]
#[doc(alias = "DBG_CNTL")]
pub type DbgCntl = crate::Reg<dbg_cntl::DbgCntlSpec>;
#[doc = "Debug control register"]
pub mod dbg_cntl {
#[doc = "Register `DBG_CNTL` reader"]
pub type R = crate::R<DbgCntlSpec>;
#[doc = "Register `DBG_CNTL` writer"]
pub type W = crate::W<DbgCntlSpec>;
#[doc = "Field `DBG_STOP` reader - Debug stop mode"]
pub type DbgStopR = crate::BitReader;
#[doc = "Field `DBG_STOP` writer - Debug stop mode"]
pub type DbgStopW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DBG_STANDBY` reader - Debug standby mode"]
pub type DbgStandbyR = crate::BitReader;
#[doc = "Field `DBG_STANDBY` writer - Debug standby mode"]
pub type DbgStandbyW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DBG_IWDG_STOP` reader - Stop IWDG during debug"]
pub type DbgIwdgStopR = crate::BitReader;
#[doc = "Field `DBG_IWDG_STOP` writer - Stop IWDG during debug"]
pub type DbgIwdgStopW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DBG_RTC_STOP` reader - Stop RTC during debug"]
pub type DbgRtcStopR = crate::BitReader;
#[doc = "Field `DBG_RTC_STOP` writer - Stop RTC during debug"]
pub type DbgRtcStopW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 1 - Debug stop mode"]
#[inline(always)]
pub fn dbg_stop(&self) -> DbgStopR {
DbgStopR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Debug standby mode"]
#[inline(always)]
pub fn dbg_standby(&self) -> DbgStandbyR {
DbgStandbyR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Stop IWDG during debug"]
#[inline(always)]
pub fn dbg_iwdg_stop(&self) -> DbgIwdgStopR {
DbgIwdgStopR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Stop RTC during debug"]
#[inline(always)]
pub fn dbg_rtc_stop(&self) -> DbgRtcStopR {
DbgRtcStopR::new(((self.bits >> 4) & 1) != 0)
}
}
impl W {
#[doc = "Bit 1 - Debug stop mode"]
#[inline(always)]
pub fn dbg_stop(&mut self) -> DbgStopW<DbgCntlSpec> {
DbgStopW::new(self, 1)
}
#[doc = "Bit 2 - Debug standby mode"]
#[inline(always)]
pub fn dbg_standby(&mut self) -> DbgStandbyW<DbgCntlSpec> {
DbgStandbyW::new(self, 2)
}
#[doc = "Bit 3 - Stop IWDG during debug"]
#[inline(always)]
pub fn dbg_iwdg_stop(&mut self) -> DbgIwdgStopW<DbgCntlSpec> {
DbgIwdgStopW::new(self, 3)
}
#[doc = "Bit 4 - Stop RTC during debug"]
#[inline(always)]
pub fn dbg_rtc_stop(&mut self) -> DbgRtcStopW<DbgCntlSpec> {
DbgRtcStopW::new(self, 4)
}
}
#[doc = "Debug control register\n\nYou can [`read`](crate::Reg::read) this register and get [`dbg_cntl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dbg_cntl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DbgCntlSpec;
impl crate::RegisterSpec for DbgCntlSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`dbg_cntl::R`](R) reader structure"]
impl crate::Readable for DbgCntlSpec {}
#[doc = "`write(|w| ..)` method takes [`dbg_cntl::W`](W) writer structure"]
impl crate::Writable for DbgCntlSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets DBG_CNTL to value 0"]
impl crate::Resettable for DbgCntlSpec {}
}
#[doc = "WKP_RISE_TRG (rw) register accessor: Wake up rise triggers\n\nYou can [`read`](crate::Reg::read) this register and get [`wkp_rise_trg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wkp_rise_trg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wkp_rise_trg`] module"]
#[doc(alias = "WKP_RISE_TRG")]
pub type WkpRiseTrg = crate::Reg<wkp_rise_trg::WkpRiseTrgSpec>;
#[doc = "Wake up rise triggers"]
pub mod wkp_rise_trg {
#[doc = "Register `WKP_RISE_TRG` reader"]
pub type R = crate::R<WkpRiseTrgSpec>;
#[doc = "Register `WKP_RISE_TRG` writer"]
pub type W = crate::W<WkpRiseTrgSpec>;
#[doc = "Field `EXT_INT0_RISE_TRG` reader - External interrupt 0 rise trigger"]
pub type ExtInt0RiseTrgR = crate::BitReader;
#[doc = "Field `EXT_INT0_RISE_TRG` writer - External interrupt 0 rise trigger"]
pub type ExtInt0RiseTrgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EXT_INT1_RISE_TRG` reader - External interrupt 1 rise trigger"]
pub type ExtInt1RiseTrgR = crate::BitReader;
#[doc = "Field `EXT_INT1_RISE_TRG` writer - External interrupt 1 rise trigger"]
pub type ExtInt1RiseTrgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EXT_INT2_RISE_TRG` reader - External interrupt 2 rise trigger"]
pub type ExtInt2RiseTrgR = crate::BitReader;
#[doc = "Field `EXT_INT2_RISE_TRG` writer - External interrupt 2 rise trigger"]
pub type ExtInt2RiseTrgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EXT_INT3_RISE_TRG` reader - External interrupt 3 rise trigger"]
pub type ExtInt3RiseTrgR = crate::BitReader;
#[doc = "Field `EXT_INT3_RISE_TRG` writer - External interrupt 3 rise trigger"]
pub type ExtInt3RiseTrgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EXT_INT4_RISE_TRG` reader - External interrupt 4 rise trigger"]
pub type ExtInt4RiseTrgR = crate::BitReader;
#[doc = "Field `EXT_INT4_RISE_TRG` writer - External interrupt 4 rise trigger"]
pub type ExtInt4RiseTrgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EXT_INT5_RISE_TRG` reader - External interrupt 5 rise trigger"]
pub type ExtInt5RiseTrgR = crate::BitReader;
#[doc = "Field `EXT_INT5_RISE_TRG` writer - External interrupt 5 rise trigger"]
pub type ExtInt5RiseTrgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EXT_INT6_RISE_TRG` reader - External interrupt 6 rise trigger"]
pub type ExtInt6RiseTrgR = crate::BitReader;
#[doc = "Field `EXT_INT6_RISE_TRG` writer - External interrupt 6 rise trigger"]
pub type ExtInt6RiseTrgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EXT_INT7_RISE_TRG` reader - External interrupt 7 rise trigger"]
pub type ExtInt7RiseTrgR = crate::BitReader;
#[doc = "Field `EXT_INT7_RISE_TRG` writer - External interrupt 7 rise trigger"]
pub type ExtInt7RiseTrgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ALARM_RISE_TRG` reader - Alarm rise trigger"]
pub type AlarmRiseTrgR = crate::BitReader;
#[doc = "Field `ALARM_RISE_TRG` writer - Alarm rise trigger"]
pub type AlarmRiseTrgW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - External interrupt 0 rise trigger"]
#[inline(always)]
pub fn ext_int0_rise_trg(&self) -> ExtInt0RiseTrgR {
ExtInt0RiseTrgR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - External interrupt 1 rise trigger"]
#[inline(always)]
pub fn ext_int1_rise_trg(&self) -> ExtInt1RiseTrgR {
ExtInt1RiseTrgR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - External interrupt 2 rise trigger"]
#[inline(always)]
pub fn ext_int2_rise_trg(&self) -> ExtInt2RiseTrgR {
ExtInt2RiseTrgR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - External interrupt 3 rise trigger"]
#[inline(always)]
pub fn ext_int3_rise_trg(&self) -> ExtInt3RiseTrgR {
ExtInt3RiseTrgR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - External interrupt 4 rise trigger"]
#[inline(always)]
pub fn ext_int4_rise_trg(&self) -> ExtInt4RiseTrgR {
ExtInt4RiseTrgR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - External interrupt 5 rise trigger"]
#[inline(always)]
pub fn ext_int5_rise_trg(&self) -> ExtInt5RiseTrgR {
ExtInt5RiseTrgR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - External interrupt 6 rise trigger"]
#[inline(always)]
pub fn ext_int6_rise_trg(&self) -> ExtInt6RiseTrgR {
ExtInt6RiseTrgR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - External interrupt 7 rise trigger"]
#[inline(always)]
pub fn ext_int7_rise_trg(&self) -> ExtInt7RiseTrgR {
ExtInt7RiseTrgR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - Alarm rise trigger"]
#[inline(always)]
pub fn alarm_rise_trg(&self) -> AlarmRiseTrgR {
AlarmRiseTrgR::new(((self.bits >> 8) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - External interrupt 0 rise trigger"]
#[inline(always)]
pub fn ext_int0_rise_trg(&mut self) -> ExtInt0RiseTrgW<WkpRiseTrgSpec> {
ExtInt0RiseTrgW::new(self, 0)
}
#[doc = "Bit 1 - External interrupt 1 rise trigger"]
#[inline(always)]
pub fn ext_int1_rise_trg(&mut self) -> ExtInt1RiseTrgW<WkpRiseTrgSpec> {
ExtInt1RiseTrgW::new(self, 1)
}
#[doc = "Bit 2 - External interrupt 2 rise trigger"]
#[inline(always)]
pub fn ext_int2_rise_trg(&mut self) -> ExtInt2RiseTrgW<WkpRiseTrgSpec> {
ExtInt2RiseTrgW::new(self, 2)
}
#[doc = "Bit 3 - External interrupt 3 rise trigger"]
#[inline(always)]
pub fn ext_int3_rise_trg(&mut self) -> ExtInt3RiseTrgW<WkpRiseTrgSpec> {
ExtInt3RiseTrgW::new(self, 3)
}
#[doc = "Bit 4 - External interrupt 4 rise trigger"]
#[inline(always)]
pub fn ext_int4_rise_trg(&mut self) -> ExtInt4RiseTrgW<WkpRiseTrgSpec> {
ExtInt4RiseTrgW::new(self, 4)
}
#[doc = "Bit 5 - External interrupt 5 rise trigger"]
#[inline(always)]
pub fn ext_int5_rise_trg(&mut self) -> ExtInt5RiseTrgW<WkpRiseTrgSpec> {
ExtInt5RiseTrgW::new(self, 5)
}
#[doc = "Bit 6 - External interrupt 6 rise trigger"]
#[inline(always)]
pub fn ext_int6_rise_trg(&mut self) -> ExtInt6RiseTrgW<WkpRiseTrgSpec> {
ExtInt6RiseTrgW::new(self, 6)
}
#[doc = "Bit 7 - External interrupt 7 rise trigger"]
#[inline(always)]
pub fn ext_int7_rise_trg(&mut self) -> ExtInt7RiseTrgW<WkpRiseTrgSpec> {
ExtInt7RiseTrgW::new(self, 7)
}
#[doc = "Bit 8 - Alarm rise trigger"]
#[inline(always)]
pub fn alarm_rise_trg(&mut self) -> AlarmRiseTrgW<WkpRiseTrgSpec> {
AlarmRiseTrgW::new(self, 8)
}
}
#[doc = "Wake up rise triggers\n\nYou can [`read`](crate::Reg::read) this register and get [`wkp_rise_trg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wkp_rise_trg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct WkpRiseTrgSpec;
impl crate::RegisterSpec for WkpRiseTrgSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`wkp_rise_trg::R`](R) reader structure"]
impl crate::Readable for WkpRiseTrgSpec {}
#[doc = "`write(|w| ..)` method takes [`wkp_rise_trg::W`](W) writer structure"]
impl crate::Writable for WkpRiseTrgSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets WKP_RISE_TRG to value 0"]
impl crate::Resettable for WkpRiseTrgSpec {}
}
#[doc = "WKP_FALL_TRG (rw) register accessor: Wake up fall triggers\n\nYou can [`read`](crate::Reg::read) this register and get [`wkp_fall_trg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wkp_fall_trg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wkp_fall_trg`] module"]
#[doc(alias = "WKP_FALL_TRG")]
pub type WkpFallTrg = crate::Reg<wkp_fall_trg::WkpFallTrgSpec>;
#[doc = "Wake up fall triggers"]
pub mod wkp_fall_trg {
#[doc = "Register `WKP_FALL_TRG` reader"]
pub type R = crate::R<WkpFallTrgSpec>;
#[doc = "Register `WKP_FALL_TRG` writer"]
pub type W = crate::W<WkpFallTrgSpec>;
#[doc = "Field `EXT_INT0_FALL_TRG` reader - External interrupt 0 fall trigger"]
pub type ExtInt0FallTrgR = crate::BitReader;
#[doc = "Field `EXT_INT0_FALL_TRG` writer - External interrupt 0 fall trigger"]
pub type ExtInt0FallTrgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EXT_INT1_FALL_TRG` reader - External interrupt 1 fall trigger"]
pub type ExtInt1FallTrgR = crate::BitReader;
#[doc = "Field `EXT_INT1_FALL_TRG` writer - External interrupt 1 fall trigger"]
pub type ExtInt1FallTrgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EXT_INT2_FALL_TRG` reader - External interrupt 2 fall trigger"]
pub type ExtInt2FallTrgR = crate::BitReader;
#[doc = "Field `EXT_INT2_FALL_TRG` writer - External interrupt 2 fall trigger"]
pub type ExtInt2FallTrgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EXT_INT3_FALL_TRG` reader - External interrupt 3 fall trigger"]
pub type ExtInt3FallTrgR = crate::BitReader;
#[doc = "Field `EXT_INT3_FALL_TRG` writer - External interrupt 3 fall trigger"]
pub type ExtInt3FallTrgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EXT_INT4_FALL_TRG` reader - External interrupt 4 fall trigger"]
pub type ExtInt4FallTrgR = crate::BitReader;
#[doc = "Field `EXT_INT4_FALL_TRG` writer - External interrupt 4 fall trigger"]
pub type ExtInt4FallTrgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EXT_INT5_FALL_TRG` reader - External interrupt 5 fall trigger"]
pub type ExtInt5FallTrgR = crate::BitReader;
#[doc = "Field `EXT_INT5_FALL_TRG` writer - External interrupt 5 fall trigger"]
pub type ExtInt5FallTrgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EXT_INT6_FALL_TRG` reader - External interrupt 6 fall trigger"]
pub type ExtInt6FallTrgR = crate::BitReader;
#[doc = "Field `EXT_INT6_FALL_TRG` writer - External interrupt 6 fall trigger"]
pub type ExtInt6FallTrgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EXT_INT7_FALL_TRG` reader - External interrupt 7 fall trigger"]
pub type ExtInt7FallTrgR = crate::BitReader;
#[doc = "Field `EXT_INT7_FALL_TRG` writer - External interrupt 7 fall trigger"]
pub type ExtInt7FallTrgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ALARM_FALL_TRG` reader - Alarm fall trigger"]
pub type AlarmFallTrgR = crate::BitReader;
#[doc = "Field `ALARM_FALL_TRG` writer - Alarm fall trigger"]
pub type AlarmFallTrgW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - External interrupt 0 fall trigger"]
#[inline(always)]
pub fn ext_int0_fall_trg(&self) -> ExtInt0FallTrgR {
ExtInt0FallTrgR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - External interrupt 1 fall trigger"]
#[inline(always)]
pub fn ext_int1_fall_trg(&self) -> ExtInt1FallTrgR {
ExtInt1FallTrgR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - External interrupt 2 fall trigger"]
#[inline(always)]
pub fn ext_int2_fall_trg(&self) -> ExtInt2FallTrgR {
ExtInt2FallTrgR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - External interrupt 3 fall trigger"]
#[inline(always)]
pub fn ext_int3_fall_trg(&self) -> ExtInt3FallTrgR {
ExtInt3FallTrgR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - External interrupt 4 fall trigger"]
#[inline(always)]
pub fn ext_int4_fall_trg(&self) -> ExtInt4FallTrgR {
ExtInt4FallTrgR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - External interrupt 5 fall trigger"]
#[inline(always)]
pub fn ext_int5_fall_trg(&self) -> ExtInt5FallTrgR {
ExtInt5FallTrgR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - External interrupt 6 fall trigger"]
#[inline(always)]
pub fn ext_int6_fall_trg(&self) -> ExtInt6FallTrgR {
ExtInt6FallTrgR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - External interrupt 7 fall trigger"]
#[inline(always)]
pub fn ext_int7_fall_trg(&self) -> ExtInt7FallTrgR {
ExtInt7FallTrgR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - Alarm fall trigger"]
#[inline(always)]
pub fn alarm_fall_trg(&self) -> AlarmFallTrgR {
AlarmFallTrgR::new(((self.bits >> 8) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - External interrupt 0 fall trigger"]
#[inline(always)]
pub fn ext_int0_fall_trg(&mut self) -> ExtInt0FallTrgW<WkpFallTrgSpec> {
ExtInt0FallTrgW::new(self, 0)
}
#[doc = "Bit 1 - External interrupt 1 fall trigger"]
#[inline(always)]
pub fn ext_int1_fall_trg(&mut self) -> ExtInt1FallTrgW<WkpFallTrgSpec> {
ExtInt1FallTrgW::new(self, 1)
}
#[doc = "Bit 2 - External interrupt 2 fall trigger"]
#[inline(always)]
pub fn ext_int2_fall_trg(&mut self) -> ExtInt2FallTrgW<WkpFallTrgSpec> {
ExtInt2FallTrgW::new(self, 2)
}
#[doc = "Bit 3 - External interrupt 3 fall trigger"]
#[inline(always)]
pub fn ext_int3_fall_trg(&mut self) -> ExtInt3FallTrgW<WkpFallTrgSpec> {
ExtInt3FallTrgW::new(self, 3)
}
#[doc = "Bit 4 - External interrupt 4 fall trigger"]
#[inline(always)]
pub fn ext_int4_fall_trg(&mut self) -> ExtInt4FallTrgW<WkpFallTrgSpec> {
ExtInt4FallTrgW::new(self, 4)
}
#[doc = "Bit 5 - External interrupt 5 fall trigger"]
#[inline(always)]
pub fn ext_int5_fall_trg(&mut self) -> ExtInt5FallTrgW<WkpFallTrgSpec> {
ExtInt5FallTrgW::new(self, 5)
}
#[doc = "Bit 6 - External interrupt 6 fall trigger"]
#[inline(always)]
pub fn ext_int6_fall_trg(&mut self) -> ExtInt6FallTrgW<WkpFallTrgSpec> {
ExtInt6FallTrgW::new(self, 6)
}
#[doc = "Bit 7 - External interrupt 7 fall trigger"]
#[inline(always)]
pub fn ext_int7_fall_trg(&mut self) -> ExtInt7FallTrgW<WkpFallTrgSpec> {
ExtInt7FallTrgW::new(self, 7)
}
#[doc = "Bit 8 - Alarm fall trigger"]
#[inline(always)]
pub fn alarm_fall_trg(&mut self) -> AlarmFallTrgW<WkpFallTrgSpec> {
AlarmFallTrgW::new(self, 8)
}
}
#[doc = "Wake up fall triggers\n\nYou can [`read`](crate::Reg::read) this register and get [`wkp_fall_trg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wkp_fall_trg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct WkpFallTrgSpec;
impl crate::RegisterSpec for WkpFallTrgSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`wkp_fall_trg::R`](R) reader structure"]
impl crate::Readable for WkpFallTrgSpec {}
#[doc = "`write(|w| ..)` method takes [`wkp_fall_trg::W`](W) writer structure"]
impl crate::Writable for WkpFallTrgSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets WKP_FALL_TRG to value 0"]
impl crate::Resettable for WkpFallTrgSpec {}
}
#[doc = "WKP_PENDING (rw) register accessor: Wake up pending register\n\nYou can [`read`](crate::Reg::read) this register and get [`wkp_pending::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wkp_pending::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wkp_pending`] module"]
#[doc(alias = "WKP_PENDING")]
pub type WkpPending = crate::Reg<wkp_pending::WkpPendingSpec>;
#[doc = "Wake up pending register"]
pub mod wkp_pending {
#[doc = "Register `WKP_PENDING` reader"]
pub type R = crate::R<WkpPendingSpec>;
#[doc = "Register `WKP_PENDING` writer"]
pub type W = crate::W<WkpPendingSpec>;
#[doc = "Field `EXT_INT0_PENDING` reader - External interrupt 0 pending"]
pub type ExtInt0PendingR = crate::BitReader;
#[doc = "Field `EXT_INT0_PENDING` writer - External interrupt 0 pending"]
pub type ExtInt0PendingW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EXT_INT1_PENDING` reader - External interrupt 1 pending"]
pub type ExtInt1PendingR = crate::BitReader;
#[doc = "Field `EXT_INT1_PENDING` writer - External interrupt 1 pending"]
pub type ExtInt1PendingW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EXT_INT2_PENDING` reader - External interrupt 2 pending"]
pub type ExtInt2PendingR = crate::BitReader;
#[doc = "Field `EXT_INT2_PENDING` writer - External interrupt 2 pending"]
pub type ExtInt2PendingW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EXT_INT3_PENDING` reader - External interrupt 3 pending"]
pub type ExtInt3PendingR = crate::BitReader;
#[doc = "Field `EXT_INT3_PENDING` writer - External interrupt 3 pending"]
pub type ExtInt3PendingW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EXT_INT4_PENDING` reader - External interrupt 4 pending"]
pub type ExtInt4PendingR = crate::BitReader;
#[doc = "Field `EXT_INT4_PENDING` writer - External interrupt 4 pending"]
pub type ExtInt4PendingW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EXT_INT5_PENDING` reader - External interrupt 5 pending"]
pub type ExtInt5PendingR = crate::BitReader;
#[doc = "Field `EXT_INT5_PENDING` writer - External interrupt 5 pending"]
pub type ExtInt5PendingW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EXT_INT6_PENDING` reader - External interrupt 6 pending"]
pub type ExtInt6PendingR = crate::BitReader;
#[doc = "Field `EXT_INT6_PENDING` writer - External interrupt 6 pending"]
pub type ExtInt6PendingW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EXT_INT7_PENDING` reader - External interrupt 7 pending"]
pub type ExtInt7PendingR = crate::BitReader;
#[doc = "Field `EXT_INT7_PENDING` writer - External interrupt 7 pending"]
pub type ExtInt7PendingW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ALARM_PENDING` reader - Alarm pending"]
pub type AlarmPendingR = crate::BitReader;
#[doc = "Field `ALARM_PENDING` writer - Alarm pending"]
pub type AlarmPendingW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - External interrupt 0 pending"]
#[inline(always)]
pub fn ext_int0_pending(&self) -> ExtInt0PendingR {
ExtInt0PendingR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - External interrupt 1 pending"]
#[inline(always)]
pub fn ext_int1_pending(&self) -> ExtInt1PendingR {
ExtInt1PendingR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - External interrupt 2 pending"]
#[inline(always)]
pub fn ext_int2_pending(&self) -> ExtInt2PendingR {
ExtInt2PendingR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - External interrupt 3 pending"]
#[inline(always)]
pub fn ext_int3_pending(&self) -> ExtInt3PendingR {
ExtInt3PendingR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - External interrupt 4 pending"]
#[inline(always)]
pub fn ext_int4_pending(&self) -> ExtInt4PendingR {
ExtInt4PendingR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - External interrupt 5 pending"]
#[inline(always)]
pub fn ext_int5_pending(&self) -> ExtInt5PendingR {
ExtInt5PendingR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - External interrupt 6 pending"]
#[inline(always)]
pub fn ext_int6_pending(&self) -> ExtInt6PendingR {
ExtInt6PendingR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - External interrupt 7 pending"]
#[inline(always)]
pub fn ext_int7_pending(&self) -> ExtInt7PendingR {
ExtInt7PendingR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - Alarm pending"]
#[inline(always)]
pub fn alarm_pending(&self) -> AlarmPendingR {
AlarmPendingR::new(((self.bits >> 8) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - External interrupt 0 pending"]
#[inline(always)]
pub fn ext_int0_pending(&mut self) -> ExtInt0PendingW<WkpPendingSpec> {
ExtInt0PendingW::new(self, 0)
}
#[doc = "Bit 1 - External interrupt 1 pending"]
#[inline(always)]
pub fn ext_int1_pending(&mut self) -> ExtInt1PendingW<WkpPendingSpec> {
ExtInt1PendingW::new(self, 1)
}
#[doc = "Bit 2 - External interrupt 2 pending"]
#[inline(always)]
pub fn ext_int2_pending(&mut self) -> ExtInt2PendingW<WkpPendingSpec> {
ExtInt2PendingW::new(self, 2)
}
#[doc = "Bit 3 - External interrupt 3 pending"]
#[inline(always)]
pub fn ext_int3_pending(&mut self) -> ExtInt3PendingW<WkpPendingSpec> {
ExtInt3PendingW::new(self, 3)
}
#[doc = "Bit 4 - External interrupt 4 pending"]
#[inline(always)]
pub fn ext_int4_pending(&mut self) -> ExtInt4PendingW<WkpPendingSpec> {
ExtInt4PendingW::new(self, 4)
}
#[doc = "Bit 5 - External interrupt 5 pending"]
#[inline(always)]
pub fn ext_int5_pending(&mut self) -> ExtInt5PendingW<WkpPendingSpec> {
ExtInt5PendingW::new(self, 5)
}
#[doc = "Bit 6 - External interrupt 6 pending"]
#[inline(always)]
pub fn ext_int6_pending(&mut self) -> ExtInt6PendingW<WkpPendingSpec> {
ExtInt6PendingW::new(self, 6)
}
#[doc = "Bit 7 - External interrupt 7 pending"]
#[inline(always)]
pub fn ext_int7_pending(&mut self) -> ExtInt7PendingW<WkpPendingSpec> {
ExtInt7PendingW::new(self, 7)
}
#[doc = "Bit 8 - Alarm pending"]
#[inline(always)]
pub fn alarm_pending(&mut self) -> AlarmPendingW<WkpPendingSpec> {
AlarmPendingW::new(self, 8)
}
}
#[doc = "Wake up pending register\n\nYou can [`read`](crate::Reg::read) this register and get [`wkp_pending::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wkp_pending::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct WkpPendingSpec;
impl crate::RegisterSpec for WkpPendingSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`wkp_pending::R`](R) reader structure"]
impl crate::Readable for WkpPendingSpec {}
#[doc = "`write(|w| ..)` method takes [`wkp_pending::W`](W) writer structure"]
impl crate::Writable for WkpPendingSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets WKP_PENDING to value 0"]
impl crate::Resettable for WkpPendingSpec {}
}
#[doc = "MTIME_PSC (rw) register accessor: Mtime prescaler value\n\nYou can [`read`](crate::Reg::read) this register and get [`mtime_psc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mtime_psc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mtime_psc`] module"]
#[doc(alias = "MTIME_PSC")]
pub type MtimePsc = crate::Reg<mtime_psc::MtimePscSpec>;
#[doc = "Mtime prescaler value"]
pub mod mtime_psc {
#[doc = "Register `MTIME_PSC` reader"]
pub type R = crate::R<MtimePscSpec>;
#[doc = "Register `MTIME_PSC` writer"]
pub type W = crate::W<MtimePscSpec>;
#[doc = "Field `MTIME_PSC` reader - Mtime prescaler value"]
pub type MtimePscR = crate::FieldReader<u16>;
#[doc = "Field `MTIME_PSC` writer - Mtime prescaler value"]
pub type MtimePscW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
#[doc = "Field `MTIME_OFF` reader - Mtime off"]
pub type MtimeOffR = crate::BitReader;
#[doc = "Field `MTIME_OFF` writer - Mtime off"]
pub type MtimeOffW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MTIME_DBG_STOP` reader - Stop mtime during debug"]
pub type MtimeDbgStopR = crate::BitReader;
#[doc = "Field `MTIME_DBG_STOP` writer - Stop mtime during debug"]
pub type MtimeDbgStopW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:15 - Mtime prescaler value"]
#[inline(always)]
pub fn mtime_psc(&self) -> MtimePscR {
MtimePscR::new((self.bits & 0xffff) as u16)
}
#[doc = "Bit 30 - Mtime off"]
#[inline(always)]
pub fn mtime_off(&self) -> MtimeOffR {
MtimeOffR::new(((self.bits >> 30) & 1) != 0)
}
#[doc = "Bit 31 - Stop mtime during debug"]
#[inline(always)]
pub fn mtime_dbg_stop(&self) -> MtimeDbgStopR {
MtimeDbgStopR::new(((self.bits >> 31) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:15 - Mtime prescaler value"]
#[inline(always)]
pub fn mtime_psc(&mut self) -> MtimePscW<MtimePscSpec> {
MtimePscW::new(self, 0)
}
#[doc = "Bit 30 - Mtime off"]
#[inline(always)]
pub fn mtime_off(&mut self) -> MtimeOffW<MtimePscSpec> {
MtimeOffW::new(self, 30)
}
#[doc = "Bit 31 - Stop mtime during debug"]
#[inline(always)]
pub fn mtime_dbg_stop(&mut self) -> MtimeDbgStopW<MtimePscSpec> {
MtimeDbgStopW::new(self, 31)
}
}
#[doc = "Mtime prescaler value\n\nYou can [`read`](crate::Reg::read) this register and get [`mtime_psc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mtime_psc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MtimePscSpec;
impl crate::RegisterSpec for MtimePscSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`mtime_psc::R`](R) reader structure"]
impl crate::Readable for MtimePscSpec {}
#[doc = "`write(|w| ..)` method takes [`mtime_psc::W`](W) writer structure"]
impl crate::Writable for MtimePscSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets MTIME_PSC to value 0"]
impl crate::Resettable for MtimePscSpec {}
}
#[doc = "MTIME_PSC_CNT (r) register accessor: Mtime prescaler counter\n\nYou can [`read`](crate::Reg::read) this register and get [`mtime_psc_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mtime_psc_cnt`] module"]
#[doc(alias = "MTIME_PSC_CNT")]
pub type MtimePscCnt = crate::Reg<mtime_psc_cnt::MtimePscCntSpec>;
#[doc = "Mtime prescaler counter"]
pub mod mtime_psc_cnt {
#[doc = "Register `MTIME_PSC_CNT` reader"]
pub type R = crate::R<MtimePscCntSpec>;
#[doc = "Field `MTIME_PSC_CNT` reader - Mtime prescaler counter"]
pub type MtimePscCntR = crate::FieldReader<u16>;
impl R {
#[doc = "Bits 0:15 - Mtime prescaler counter"]
#[inline(always)]
pub fn mtime_psc_cnt(&self) -> MtimePscCntR {
MtimePscCntR::new((self.bits & 0xffff) as u16)
}
}
#[doc = "Mtime prescaler counter\n\nYou can [`read`](crate::Reg::read) this register and get [`mtime_psc_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MtimePscCntSpec;
impl crate::RegisterSpec for MtimePscCntSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`mtime_psc_cnt::R`](R) reader structure"]
impl crate::Readable for MtimePscCntSpec {}
#[doc = "`reset()` method sets MTIME_PSC_CNT to value 0"]
impl crate::Resettable for MtimePscCntSpec {}
}
#[doc = "PBUS_DIV (rw) register accessor: Pbus clock divider\n\nYou can [`read`](crate::Reg::read) this register and get [`pbus_div::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pbus_div::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pbus_div`] module"]
#[doc(alias = "PBUS_DIV")]
pub type PbusDiv = crate::Reg<pbus_div::PbusDivSpec>;
#[doc = "Pbus clock divider"]
pub mod pbus_div {
#[doc = "Register `PBUS_DIV` reader"]
pub type R = crate::R<PbusDivSpec>;
#[doc = "Register `PBUS_DIV` writer"]
pub type W = crate::W<PbusDivSpec>;
#[doc = "Field `PBUS_DIV` reader - Pbus clock divider"]
pub type PbusDivR = crate::FieldReader;
#[doc = "Field `PBUS_DIV` writer - Pbus clock divider"]
pub type PbusDivW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
impl R {
#[doc = "Bits 0:3 - Pbus clock divider"]
#[inline(always)]
pub fn pbus_div(&self) -> PbusDivR {
PbusDivR::new((self.bits & 0x0f) as u8)
}
}
impl W {
#[doc = "Bits 0:3 - Pbus clock divider"]
#[inline(always)]
pub fn pbus_div(&mut self) -> PbusDivW<PbusDivSpec> {
PbusDivW::new(self, 0)
}
}
#[doc = "Pbus clock divider\n\nYou can [`read`](crate::Reg::read) this register and get [`pbus_div::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pbus_div::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PbusDivSpec;
impl crate::RegisterSpec for PbusDivSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`pbus_div::R`](R) reader structure"]
impl crate::Readable for PbusDivSpec {}
#[doc = "`write(|w| ..)` method takes [`pbus_div::W`](W) writer structure"]
impl crate::Writable for PbusDivSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets PBUS_DIV to value 0"]
impl crate::Resettable for PbusDivSpec {}
}
#[doc = "APB_RST (rw) register accessor: APB peripheral reset\n\nYou can [`read`](crate::Reg::read) this register and get [`apb_rst::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb_rst::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb_rst`] module"]
#[doc(alias = "APB_RST")]
pub type ApbRst = crate::Reg<apb_rst::ApbRstSpec>;
#[doc = "APB peripheral reset"]
pub mod apb_rst {
#[doc = "Register `APB_RST` reader"]
pub type R = crate::R<ApbRstSpec>;
#[doc = "Register `APB_RST` writer"]
pub type W = crate::W<ApbRstSpec>;
#[doc = "Field `APB_RST_FCB0` reader - APB reset for FCB"]
pub type ApbRstFcb0R = crate::BitReader;
#[doc = "Field `APB_RST_FCB0` writer - APB reset for FCB"]
pub type ApbRstFcb0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_RST_WATCHDOG0` reader - APB reset for WATCHDOG"]
pub type ApbRstWatchdog0R = crate::BitReader;
#[doc = "Field `APB_RST_WATCHDOG0` writer - APB reset for WATCHDOG"]
pub type ApbRstWatchdog0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_RST_SPI0` reader - APB reset for SPI"]
pub type ApbRstSpi0R = crate::BitReader;
#[doc = "Field `APB_RST_SPI0` writer - APB reset for SPI"]
pub type ApbRstSpi0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_RST_SPI1` reader - APB reset for SPI"]
pub type ApbRstSpi1R = crate::BitReader;
#[doc = "Field `APB_RST_SPI1` writer - APB reset for SPI"]
pub type ApbRstSpi1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_RST_GPIO0` reader - APB reset for GPIO"]
pub type ApbRstGpio0R = crate::BitReader;
#[doc = "Field `APB_RST_GPIO0` writer - APB reset for GPIO"]
pub type ApbRstGpio0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_RST_GPIO1` reader - APB reset for GPIO"]
pub type ApbRstGpio1R = crate::BitReader;
#[doc = "Field `APB_RST_GPIO1` writer - APB reset for GPIO"]
pub type ApbRstGpio1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_RST_GPIO2` reader - APB reset for GPIO"]
pub type ApbRstGpio2R = crate::BitReader;
#[doc = "Field `APB_RST_GPIO2` writer - APB reset for GPIO"]
pub type ApbRstGpio2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_RST_GPIO3` reader - APB reset for GPIO"]
pub type ApbRstGpio3R = crate::BitReader;
#[doc = "Field `APB_RST_GPIO3` writer - APB reset for GPIO"]
pub type ApbRstGpio3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_RST_GPIO4` reader - APB reset for GPIO"]
pub type ApbRstGpio4R = crate::BitReader;
#[doc = "Field `APB_RST_GPIO4` writer - APB reset for GPIO"]
pub type ApbRstGpio4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_RST_GPIO5` reader - APB reset for GPIO"]
pub type ApbRstGpio5R = crate::BitReader;
#[doc = "Field `APB_RST_GPIO5` writer - APB reset for GPIO"]
pub type ApbRstGpio5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_RST_GPIO6` reader - APB reset for GPIO"]
pub type ApbRstGpio6R = crate::BitReader;
#[doc = "Field `APB_RST_GPIO6` writer - APB reset for GPIO"]
pub type ApbRstGpio6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_RST_GPIO7` reader - APB reset for GPIO"]
pub type ApbRstGpio7R = crate::BitReader;
#[doc = "Field `APB_RST_GPIO7` writer - APB reset for GPIO"]
pub type ApbRstGpio7W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_RST_GPIO8` reader - APB reset for GPIO"]
pub type ApbRstGpio8R = crate::BitReader;
#[doc = "Field `APB_RST_GPIO8` writer - APB reset for GPIO"]
pub type ApbRstGpio8W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_RST_GPIO9` reader - APB reset for GPIO"]
pub type ApbRstGpio9R = crate::BitReader;
#[doc = "Field `APB_RST_GPIO9` writer - APB reset for GPIO"]
pub type ApbRstGpio9W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_RST_TIMER0` reader - APB reset for TIMER"]
pub type ApbRstTimer0R = crate::BitReader;
#[doc = "Field `APB_RST_TIMER0` writer - APB reset for TIMER"]
pub type ApbRstTimer0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_RST_TIMER1` reader - APB reset for TIMER"]
pub type ApbRstTimer1R = crate::BitReader;
#[doc = "Field `APB_RST_TIMER1` writer - APB reset for TIMER"]
pub type ApbRstTimer1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_RST_GPTIMER0` reader - APB reset for GPTIMER"]
pub type ApbRstGptimer0R = crate::BitReader;
#[doc = "Field `APB_RST_GPTIMER0` writer - APB reset for GPTIMER"]
pub type ApbRstGptimer0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_RST_GPTIMER1` reader - APB reset for GPTIMER"]
pub type ApbRstGptimer1R = crate::BitReader;
#[doc = "Field `APB_RST_GPTIMER1` writer - APB reset for GPTIMER"]
pub type ApbRstGptimer1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_RST_GPTIMER2` reader - APB reset for GPTIMER"]
pub type ApbRstGptimer2R = crate::BitReader;
#[doc = "Field `APB_RST_GPTIMER2` writer - APB reset for GPTIMER"]
pub type ApbRstGptimer2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_RST_GPTIMER3` reader - APB reset for GPTIMER"]
pub type ApbRstGptimer3R = crate::BitReader;
#[doc = "Field `APB_RST_GPTIMER3` writer - APB reset for GPTIMER"]
pub type ApbRstGptimer3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_RST_GPTIMER4` reader - APB reset for GPTIMER"]
pub type ApbRstGptimer4R = crate::BitReader;
#[doc = "Field `APB_RST_GPTIMER4` writer - APB reset for GPTIMER"]
pub type ApbRstGptimer4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_RST_UART0` reader - APB reset for UART"]
pub type ApbRstUart0R = crate::BitReader;
#[doc = "Field `APB_RST_UART0` writer - APB reset for UART"]
pub type ApbRstUart0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_RST_UART1` reader - APB reset for UART"]
pub type ApbRstUart1R = crate::BitReader;
#[doc = "Field `APB_RST_UART1` writer - APB reset for UART"]
pub type ApbRstUart1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_RST_UART2` reader - APB reset for UART"]
pub type ApbRstUart2R = crate::BitReader;
#[doc = "Field `APB_RST_UART2` writer - APB reset for UART"]
pub type ApbRstUart2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_RST_UART3` reader - APB reset for UART"]
pub type ApbRstUart3R = crate::BitReader;
#[doc = "Field `APB_RST_UART3` writer - APB reset for UART"]
pub type ApbRstUart3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_RST_UART4` reader - APB reset for UART"]
pub type ApbRstUart4R = crate::BitReader;
#[doc = "Field `APB_RST_UART4` writer - APB reset for UART"]
pub type ApbRstUart4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_RST_CAN0` reader - APB reset for CAN"]
pub type ApbRstCan0R = crate::BitReader;
#[doc = "Field `APB_RST_CAN0` writer - APB reset for CAN"]
pub type ApbRstCan0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_RST_I2C0` reader - APB reset for I2C"]
pub type ApbRstI2c0R = crate::BitReader;
#[doc = "Field `APB_RST_I2C0` writer - APB reset for I2C"]
pub type ApbRstI2c0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_RST_I2C1` reader - APB reset for I2C"]
pub type ApbRstI2c1R = crate::BitReader;
#[doc = "Field `APB_RST_I2C1` writer - APB reset for I2C"]
pub type ApbRstI2c1W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - APB reset for FCB"]
#[inline(always)]
pub fn apb_rst_fcb0(&self) -> ApbRstFcb0R {
ApbRstFcb0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - APB reset for WATCHDOG"]
#[inline(always)]
pub fn apb_rst_watchdog0(&self) -> ApbRstWatchdog0R {
ApbRstWatchdog0R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - APB reset for SPI"]
#[inline(always)]
pub fn apb_rst_spi0(&self) -> ApbRstSpi0R {
ApbRstSpi0R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - APB reset for SPI"]
#[inline(always)]
pub fn apb_rst_spi1(&self) -> ApbRstSpi1R {
ApbRstSpi1R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - APB reset for GPIO"]
#[inline(always)]
pub fn apb_rst_gpio0(&self) -> ApbRstGpio0R {
ApbRstGpio0R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - APB reset for GPIO"]
#[inline(always)]
pub fn apb_rst_gpio1(&self) -> ApbRstGpio1R {
ApbRstGpio1R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - APB reset for GPIO"]
#[inline(always)]
pub fn apb_rst_gpio2(&self) -> ApbRstGpio2R {
ApbRstGpio2R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - APB reset for GPIO"]
#[inline(always)]
pub fn apb_rst_gpio3(&self) -> ApbRstGpio3R {
ApbRstGpio3R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - APB reset for GPIO"]
#[inline(always)]
pub fn apb_rst_gpio4(&self) -> ApbRstGpio4R {
ApbRstGpio4R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - APB reset for GPIO"]
#[inline(always)]
pub fn apb_rst_gpio5(&self) -> ApbRstGpio5R {
ApbRstGpio5R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - APB reset for GPIO"]
#[inline(always)]
pub fn apb_rst_gpio6(&self) -> ApbRstGpio6R {
ApbRstGpio6R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - APB reset for GPIO"]
#[inline(always)]
pub fn apb_rst_gpio7(&self) -> ApbRstGpio7R {
ApbRstGpio7R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12 - APB reset for GPIO"]
#[inline(always)]
pub fn apb_rst_gpio8(&self) -> ApbRstGpio8R {
ApbRstGpio8R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13 - APB reset for GPIO"]
#[inline(always)]
pub fn apb_rst_gpio9(&self) -> ApbRstGpio9R {
ApbRstGpio9R::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - APB reset for TIMER"]
#[inline(always)]
pub fn apb_rst_timer0(&self) -> ApbRstTimer0R {
ApbRstTimer0R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15 - APB reset for TIMER"]
#[inline(always)]
pub fn apb_rst_timer1(&self) -> ApbRstTimer1R {
ApbRstTimer1R::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bit 16 - APB reset for GPTIMER"]
#[inline(always)]
pub fn apb_rst_gptimer0(&self) -> ApbRstGptimer0R {
ApbRstGptimer0R::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 17 - APB reset for GPTIMER"]
#[inline(always)]
pub fn apb_rst_gptimer1(&self) -> ApbRstGptimer1R {
ApbRstGptimer1R::new(((self.bits >> 17) & 1) != 0)
}
#[doc = "Bit 18 - APB reset for GPTIMER"]
#[inline(always)]
pub fn apb_rst_gptimer2(&self) -> ApbRstGptimer2R {
ApbRstGptimer2R::new(((self.bits >> 18) & 1) != 0)
}
#[doc = "Bit 19 - APB reset for GPTIMER"]
#[inline(always)]
pub fn apb_rst_gptimer3(&self) -> ApbRstGptimer3R {
ApbRstGptimer3R::new(((self.bits >> 19) & 1) != 0)
}
#[doc = "Bit 20 - APB reset for GPTIMER"]
#[inline(always)]
pub fn apb_rst_gptimer4(&self) -> ApbRstGptimer4R {
ApbRstGptimer4R::new(((self.bits >> 20) & 1) != 0)
}
#[doc = "Bit 21 - APB reset for UART"]
#[inline(always)]
pub fn apb_rst_uart0(&self) -> ApbRstUart0R {
ApbRstUart0R::new(((self.bits >> 21) & 1) != 0)
}
#[doc = "Bit 22 - APB reset for UART"]
#[inline(always)]
pub fn apb_rst_uart1(&self) -> ApbRstUart1R {
ApbRstUart1R::new(((self.bits >> 22) & 1) != 0)
}
#[doc = "Bit 23 - APB reset for UART"]
#[inline(always)]
pub fn apb_rst_uart2(&self) -> ApbRstUart2R {
ApbRstUart2R::new(((self.bits >> 23) & 1) != 0)
}
#[doc = "Bit 24 - APB reset for UART"]
#[inline(always)]
pub fn apb_rst_uart3(&self) -> ApbRstUart3R {
ApbRstUart3R::new(((self.bits >> 24) & 1) != 0)
}
#[doc = "Bit 25 - APB reset for UART"]
#[inline(always)]
pub fn apb_rst_uart4(&self) -> ApbRstUart4R {
ApbRstUart4R::new(((self.bits >> 25) & 1) != 0)
}
#[doc = "Bit 26 - APB reset for CAN"]
#[inline(always)]
pub fn apb_rst_can0(&self) -> ApbRstCan0R {
ApbRstCan0R::new(((self.bits >> 26) & 1) != 0)
}
#[doc = "Bit 27 - APB reset for I2C"]
#[inline(always)]
pub fn apb_rst_i2c0(&self) -> ApbRstI2c0R {
ApbRstI2c0R::new(((self.bits >> 27) & 1) != 0)
}
#[doc = "Bit 28 - APB reset for I2C"]
#[inline(always)]
pub fn apb_rst_i2c1(&self) -> ApbRstI2c1R {
ApbRstI2c1R::new(((self.bits >> 28) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - APB reset for FCB"]
#[inline(always)]
pub fn apb_rst_fcb0(&mut self) -> ApbRstFcb0W<ApbRstSpec> {
ApbRstFcb0W::new(self, 0)
}
#[doc = "Bit 1 - APB reset for WATCHDOG"]
#[inline(always)]
pub fn apb_rst_watchdog0(&mut self) -> ApbRstWatchdog0W<ApbRstSpec> {
ApbRstWatchdog0W::new(self, 1)
}
#[doc = "Bit 2 - APB reset for SPI"]
#[inline(always)]
pub fn apb_rst_spi0(&mut self) -> ApbRstSpi0W<ApbRstSpec> {
ApbRstSpi0W::new(self, 2)
}
#[doc = "Bit 3 - APB reset for SPI"]
#[inline(always)]
pub fn apb_rst_spi1(&mut self) -> ApbRstSpi1W<ApbRstSpec> {
ApbRstSpi1W::new(self, 3)
}
#[doc = "Bit 4 - APB reset for GPIO"]
#[inline(always)]
pub fn apb_rst_gpio0(&mut self) -> ApbRstGpio0W<ApbRstSpec> {
ApbRstGpio0W::new(self, 4)
}
#[doc = "Bit 5 - APB reset for GPIO"]
#[inline(always)]
pub fn apb_rst_gpio1(&mut self) -> ApbRstGpio1W<ApbRstSpec> {
ApbRstGpio1W::new(self, 5)
}
#[doc = "Bit 6 - APB reset for GPIO"]
#[inline(always)]
pub fn apb_rst_gpio2(&mut self) -> ApbRstGpio2W<ApbRstSpec> {
ApbRstGpio2W::new(self, 6)
}
#[doc = "Bit 7 - APB reset for GPIO"]
#[inline(always)]
pub fn apb_rst_gpio3(&mut self) -> ApbRstGpio3W<ApbRstSpec> {
ApbRstGpio3W::new(self, 7)
}
#[doc = "Bit 8 - APB reset for GPIO"]
#[inline(always)]
pub fn apb_rst_gpio4(&mut self) -> ApbRstGpio4W<ApbRstSpec> {
ApbRstGpio4W::new(self, 8)
}
#[doc = "Bit 9 - APB reset for GPIO"]
#[inline(always)]
pub fn apb_rst_gpio5(&mut self) -> ApbRstGpio5W<ApbRstSpec> {
ApbRstGpio5W::new(self, 9)
}
#[doc = "Bit 10 - APB reset for GPIO"]
#[inline(always)]
pub fn apb_rst_gpio6(&mut self) -> ApbRstGpio6W<ApbRstSpec> {
ApbRstGpio6W::new(self, 10)
}
#[doc = "Bit 11 - APB reset for GPIO"]
#[inline(always)]
pub fn apb_rst_gpio7(&mut self) -> ApbRstGpio7W<ApbRstSpec> {
ApbRstGpio7W::new(self, 11)
}
#[doc = "Bit 12 - APB reset for GPIO"]
#[inline(always)]
pub fn apb_rst_gpio8(&mut self) -> ApbRstGpio8W<ApbRstSpec> {
ApbRstGpio8W::new(self, 12)
}
#[doc = "Bit 13 - APB reset for GPIO"]
#[inline(always)]
pub fn apb_rst_gpio9(&mut self) -> ApbRstGpio9W<ApbRstSpec> {
ApbRstGpio9W::new(self, 13)
}
#[doc = "Bit 14 - APB reset for TIMER"]
#[inline(always)]
pub fn apb_rst_timer0(&mut self) -> ApbRstTimer0W<ApbRstSpec> {
ApbRstTimer0W::new(self, 14)
}
#[doc = "Bit 15 - APB reset for TIMER"]
#[inline(always)]
pub fn apb_rst_timer1(&mut self) -> ApbRstTimer1W<ApbRstSpec> {
ApbRstTimer1W::new(self, 15)
}
#[doc = "Bit 16 - APB reset for GPTIMER"]
#[inline(always)]
pub fn apb_rst_gptimer0(&mut self) -> ApbRstGptimer0W<ApbRstSpec> {
ApbRstGptimer0W::new(self, 16)
}
#[doc = "Bit 17 - APB reset for GPTIMER"]
#[inline(always)]
pub fn apb_rst_gptimer1(&mut self) -> ApbRstGptimer1W<ApbRstSpec> {
ApbRstGptimer1W::new(self, 17)
}
#[doc = "Bit 18 - APB reset for GPTIMER"]
#[inline(always)]
pub fn apb_rst_gptimer2(&mut self) -> ApbRstGptimer2W<ApbRstSpec> {
ApbRstGptimer2W::new(self, 18)
}
#[doc = "Bit 19 - APB reset for GPTIMER"]
#[inline(always)]
pub fn apb_rst_gptimer3(&mut self) -> ApbRstGptimer3W<ApbRstSpec> {
ApbRstGptimer3W::new(self, 19)
}
#[doc = "Bit 20 - APB reset for GPTIMER"]
#[inline(always)]
pub fn apb_rst_gptimer4(&mut self) -> ApbRstGptimer4W<ApbRstSpec> {
ApbRstGptimer4W::new(self, 20)
}
#[doc = "Bit 21 - APB reset for UART"]
#[inline(always)]
pub fn apb_rst_uart0(&mut self) -> ApbRstUart0W<ApbRstSpec> {
ApbRstUart0W::new(self, 21)
}
#[doc = "Bit 22 - APB reset for UART"]
#[inline(always)]
pub fn apb_rst_uart1(&mut self) -> ApbRstUart1W<ApbRstSpec> {
ApbRstUart1W::new(self, 22)
}
#[doc = "Bit 23 - APB reset for UART"]
#[inline(always)]
pub fn apb_rst_uart2(&mut self) -> ApbRstUart2W<ApbRstSpec> {
ApbRstUart2W::new(self, 23)
}
#[doc = "Bit 24 - APB reset for UART"]
#[inline(always)]
pub fn apb_rst_uart3(&mut self) -> ApbRstUart3W<ApbRstSpec> {
ApbRstUart3W::new(self, 24)
}
#[doc = "Bit 25 - APB reset for UART"]
#[inline(always)]
pub fn apb_rst_uart4(&mut self) -> ApbRstUart4W<ApbRstSpec> {
ApbRstUart4W::new(self, 25)
}
#[doc = "Bit 26 - APB reset for CAN"]
#[inline(always)]
pub fn apb_rst_can0(&mut self) -> ApbRstCan0W<ApbRstSpec> {
ApbRstCan0W::new(self, 26)
}
#[doc = "Bit 27 - APB reset for I2C"]
#[inline(always)]
pub fn apb_rst_i2c0(&mut self) -> ApbRstI2c0W<ApbRstSpec> {
ApbRstI2c0W::new(self, 27)
}
#[doc = "Bit 28 - APB reset for I2C"]
#[inline(always)]
pub fn apb_rst_i2c1(&mut self) -> ApbRstI2c1W<ApbRstSpec> {
ApbRstI2c1W::new(self, 28)
}
}
#[doc = "APB peripheral reset\n\nYou can [`read`](crate::Reg::read) this register and get [`apb_rst::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb_rst::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ApbRstSpec;
impl crate::RegisterSpec for ApbRstSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`apb_rst::R`](R) reader structure"]
impl crate::Readable for ApbRstSpec {}
#[doc = "`write(|w| ..)` method takes [`apb_rst::W`](W) writer structure"]
impl crate::Writable for ApbRstSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets APB_RST to value 0"]
impl crate::Resettable for ApbRstSpec {}
}
#[doc = "AHB_RST (rw) register accessor: AHB peripheral reset\n\nYou can [`read`](crate::Reg::read) this register and get [`ahb_rst::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ahb_rst::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ahb_rst`] module"]
#[doc(alias = "AHB_RST")]
pub type AhbRst = crate::Reg<ahb_rst::AhbRstSpec>;
#[doc = "AHB peripheral reset"]
pub mod ahb_rst {
#[doc = "Register `AHB_RST` reader"]
pub type R = crate::R<AhbRstSpec>;
#[doc = "Register `AHB_RST` writer"]
pub type W = crate::W<AhbRstSpec>;
#[doc = "Field `AHB_RST_DMAC0` reader - AHB reset for DMAC"]
pub type AhbRstDmac0R = crate::BitReader;
#[doc = "Field `AHB_RST_DMAC0` writer - AHB reset for DMAC"]
pub type AhbRstDmac0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `AHB_RST_USB0` reader - AHB reset for USB"]
pub type AhbRstUsb0R = crate::BitReader;
#[doc = "Field `AHB_RST_USB0` writer - AHB reset for USB"]
pub type AhbRstUsb0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `AHB_RST_CRC0` reader - AHB reset for CRC"]
pub type AhbRstCrc0R = crate::BitReader;
#[doc = "Field `AHB_RST_CRC0` writer - AHB reset for CRC"]
pub type AhbRstCrc0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `AHB_RST_MAC0` reader - AHB reset for MAC"]
pub type AhbRstMac0R = crate::BitReader;
#[doc = "Field `AHB_RST_MAC0` writer - AHB reset for MAC"]
pub type AhbRstMac0W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - AHB reset for DMAC"]
#[inline(always)]
pub fn ahb_rst_dmac0(&self) -> AhbRstDmac0R {
AhbRstDmac0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - AHB reset for USB"]
#[inline(always)]
pub fn ahb_rst_usb0(&self) -> AhbRstUsb0R {
AhbRstUsb0R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - AHB reset for CRC"]
#[inline(always)]
pub fn ahb_rst_crc0(&self) -> AhbRstCrc0R {
AhbRstCrc0R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - AHB reset for MAC"]
#[inline(always)]
pub fn ahb_rst_mac0(&self) -> AhbRstMac0R {
AhbRstMac0R::new(((self.bits >> 3) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - AHB reset for DMAC"]
#[inline(always)]
pub fn ahb_rst_dmac0(&mut self) -> AhbRstDmac0W<AhbRstSpec> {
AhbRstDmac0W::new(self, 0)
}
#[doc = "Bit 1 - AHB reset for USB"]
#[inline(always)]
pub fn ahb_rst_usb0(&mut self) -> AhbRstUsb0W<AhbRstSpec> {
AhbRstUsb0W::new(self, 1)
}
#[doc = "Bit 2 - AHB reset for CRC"]
#[inline(always)]
pub fn ahb_rst_crc0(&mut self) -> AhbRstCrc0W<AhbRstSpec> {
AhbRstCrc0W::new(self, 2)
}
#[doc = "Bit 3 - AHB reset for MAC"]
#[inline(always)]
pub fn ahb_rst_mac0(&mut self) -> AhbRstMac0W<AhbRstSpec> {
AhbRstMac0W::new(self, 3)
}
}
#[doc = "AHB peripheral reset\n\nYou can [`read`](crate::Reg::read) this register and get [`ahb_rst::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ahb_rst::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AhbRstSpec;
impl crate::RegisterSpec for AhbRstSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ahb_rst::R`](R) reader structure"]
impl crate::Readable for AhbRstSpec {}
#[doc = "`write(|w| ..)` method takes [`ahb_rst::W`](W) writer structure"]
impl crate::Writable for AhbRstSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets AHB_RST to value 0"]
impl crate::Resettable for AhbRstSpec {}
}
#[doc = "APB_CLK_EN (rw) register accessor: APB peripheral clock enable\n\nYou can [`read`](crate::Reg::read) this register and get [`apb_clk_en::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb_clk_en::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb_clk_en`] module"]
#[doc(alias = "APB_CLK_EN")]
pub type ApbClkEn = crate::Reg<apb_clk_en::ApbClkEnSpec>;
#[doc = "APB peripheral clock enable"]
pub mod apb_clk_en {
#[doc = "Register `APB_CLK_EN` reader"]
pub type R = crate::R<ApbClkEnSpec>;
#[doc = "Register `APB_CLK_EN` writer"]
pub type W = crate::W<ApbClkEnSpec>;
#[doc = "Field `APB_CLK_EN_FCB0` reader - APB clock enable for FCB"]
pub type ApbClkEnFcb0R = crate::BitReader;
#[doc = "Field `APB_CLK_EN_FCB0` writer - APB clock enable for FCB"]
pub type ApbClkEnFcb0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_CLK_EN_WATCHDOG0` reader - APB clock enable for WATCHDOG"]
pub type ApbClkEnWatchdog0R = crate::BitReader;
#[doc = "Field `APB_CLK_EN_WATCHDOG0` writer - APB clock enable for WATCHDOG"]
pub type ApbClkEnWatchdog0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_CLK_EN_SPI0` reader - APB clock enable for SPI"]
pub type ApbClkEnSpi0R = crate::BitReader;
#[doc = "Field `APB_CLK_EN_SPI0` writer - APB clock enable for SPI"]
pub type ApbClkEnSpi0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_CLK_EN_SPI1` reader - APB clock enable for SPI"]
pub type ApbClkEnSpi1R = crate::BitReader;
#[doc = "Field `APB_CLK_EN_SPI1` writer - APB clock enable for SPI"]
pub type ApbClkEnSpi1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_CLK_EN_GPIO0` reader - APB clock enable for GPIO"]
pub type ApbClkEnGpio0R = crate::BitReader;
#[doc = "Field `APB_CLK_EN_GPIO0` writer - APB clock enable for GPIO"]
pub type ApbClkEnGpio0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_CLK_EN_GPIO1` reader - APB clock enable for GPIO"]
pub type ApbClkEnGpio1R = crate::BitReader;
#[doc = "Field `APB_CLK_EN_GPIO1` writer - APB clock enable for GPIO"]
pub type ApbClkEnGpio1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_CLK_EN_GPIO2` reader - APB clock enable for GPIO"]
pub type ApbClkEnGpio2R = crate::BitReader;
#[doc = "Field `APB_CLK_EN_GPIO2` writer - APB clock enable for GPIO"]
pub type ApbClkEnGpio2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_CLK_EN_GPIO3` reader - APB clock enable for GPIO"]
pub type ApbClkEnGpio3R = crate::BitReader;
#[doc = "Field `APB_CLK_EN_GPIO3` writer - APB clock enable for GPIO"]
pub type ApbClkEnGpio3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_CLK_EN_GPIO4` reader - APB clock enable for GPIO"]
pub type ApbClkEnGpio4R = crate::BitReader;
#[doc = "Field `APB_CLK_EN_GPIO4` writer - APB clock enable for GPIO"]
pub type ApbClkEnGpio4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_CLK_EN_GPIO5` reader - APB clock enable for GPIO"]
pub type ApbClkEnGpio5R = crate::BitReader;
#[doc = "Field `APB_CLK_EN_GPIO5` writer - APB clock enable for GPIO"]
pub type ApbClkEnGpio5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_CLK_EN_GPIO6` reader - APB clock enable for GPIO"]
pub type ApbClkEnGpio6R = crate::BitReader;
#[doc = "Field `APB_CLK_EN_GPIO6` writer - APB clock enable for GPIO"]
pub type ApbClkEnGpio6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_CLK_EN_GPIO7` reader - APB clock enable for GPIO"]
pub type ApbClkEnGpio7R = crate::BitReader;
#[doc = "Field `APB_CLK_EN_GPIO7` writer - APB clock enable for GPIO"]
pub type ApbClkEnGpio7W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_CLK_EN_GPIO8` reader - APB clock enable for GPIO"]
pub type ApbClkEnGpio8R = crate::BitReader;
#[doc = "Field `APB_CLK_EN_GPIO8` writer - APB clock enable for GPIO"]
pub type ApbClkEnGpio8W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_CLK_EN_GPIO9` reader - APB clock enable for GPIO"]
pub type ApbClkEnGpio9R = crate::BitReader;
#[doc = "Field `APB_CLK_EN_GPIO9` writer - APB clock enable for GPIO"]
pub type ApbClkEnGpio9W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_CLK_EN_TIMER0` reader - APB clock enable for TIMER"]
pub type ApbClkEnTimer0R = crate::BitReader;
#[doc = "Field `APB_CLK_EN_TIMER0` writer - APB clock enable for TIMER"]
pub type ApbClkEnTimer0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_CLK_EN_TIMER1` reader - APB clock enable for TIMER"]
pub type ApbClkEnTimer1R = crate::BitReader;
#[doc = "Field `APB_CLK_EN_TIMER1` writer - APB clock enable for TIMER"]
pub type ApbClkEnTimer1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_CLK_EN_GPTIMER0` reader - APB clock enable for GPTIMER"]
pub type ApbClkEnGptimer0R = crate::BitReader;
#[doc = "Field `APB_CLK_EN_GPTIMER0` writer - APB clock enable for GPTIMER"]
pub type ApbClkEnGptimer0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_CLK_EN_GPTIMER1` reader - APB clock enable for GPTIMER"]
pub type ApbClkEnGptimer1R = crate::BitReader;
#[doc = "Field `APB_CLK_EN_GPTIMER1` writer - APB clock enable for GPTIMER"]
pub type ApbClkEnGptimer1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_CLK_EN_GPTIMER2` reader - APB clock enable for GPTIMER"]
pub type ApbClkEnGptimer2R = crate::BitReader;
#[doc = "Field `APB_CLK_EN_GPTIMER2` writer - APB clock enable for GPTIMER"]
pub type ApbClkEnGptimer2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_CLK_EN_GPTIMER3` reader - APB clock enable for GPTIMER"]
pub type ApbClkEnGptimer3R = crate::BitReader;
#[doc = "Field `APB_CLK_EN_GPTIMER3` writer - APB clock enable for GPTIMER"]
pub type ApbClkEnGptimer3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_CLK_EN_GPTIMER4` reader - APB clock enable for GPTIMER"]
pub type ApbClkEnGptimer4R = crate::BitReader;
#[doc = "Field `APB_CLK_EN_GPTIMER4` writer - APB clock enable for GPTIMER"]
pub type ApbClkEnGptimer4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_CLK_EN_UART0` reader - APB clock enable for UART"]
pub type ApbClkEnUart0R = crate::BitReader;
#[doc = "Field `APB_CLK_EN_UART0` writer - APB clock enable for UART"]
pub type ApbClkEnUart0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_CLK_EN_UART1` reader - APB clock enable for UART"]
pub type ApbClkEnUart1R = crate::BitReader;
#[doc = "Field `APB_CLK_EN_UART1` writer - APB clock enable for UART"]
pub type ApbClkEnUart1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_CLK_EN_UART2` reader - APB clock enable for UART"]
pub type ApbClkEnUart2R = crate::BitReader;
#[doc = "Field `APB_CLK_EN_UART2` writer - APB clock enable for UART"]
pub type ApbClkEnUart2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_CLK_EN_UART3` reader - APB clock enable for UART"]
pub type ApbClkEnUart3R = crate::BitReader;
#[doc = "Field `APB_CLK_EN_UART3` writer - APB clock enable for UART"]
pub type ApbClkEnUart3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_CLK_EN_UART4` reader - APB clock enable for UART"]
pub type ApbClkEnUart4R = crate::BitReader;
#[doc = "Field `APB_CLK_EN_UART4` writer - APB clock enable for UART"]
pub type ApbClkEnUart4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_CLK_EN_CAN0` reader - APB clock enable for CAN"]
pub type ApbClkEnCan0R = crate::BitReader;
#[doc = "Field `APB_CLK_EN_CAN0` writer - APB clock enable for CAN"]
pub type ApbClkEnCan0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_CLK_EN_I2C0` reader - APB clock enable for I2C"]
pub type ApbClkEnI2c0R = crate::BitReader;
#[doc = "Field `APB_CLK_EN_I2C0` writer - APB clock enable for I2C"]
pub type ApbClkEnI2c0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_CLK_EN_I2C1` reader - APB clock enable for I2C"]
pub type ApbClkEnI2c1R = crate::BitReader;
#[doc = "Field `APB_CLK_EN_I2C1` writer - APB clock enable for I2C"]
pub type ApbClkEnI2c1W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - APB clock enable for FCB"]
#[inline(always)]
pub fn apb_clk_en_fcb0(&self) -> ApbClkEnFcb0R {
ApbClkEnFcb0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - APB clock enable for WATCHDOG"]
#[inline(always)]
pub fn apb_clk_en_watchdog0(&self) -> ApbClkEnWatchdog0R {
ApbClkEnWatchdog0R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - APB clock enable for SPI"]
#[inline(always)]
pub fn apb_clk_en_spi0(&self) -> ApbClkEnSpi0R {
ApbClkEnSpi0R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - APB clock enable for SPI"]
#[inline(always)]
pub fn apb_clk_en_spi1(&self) -> ApbClkEnSpi1R {
ApbClkEnSpi1R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - APB clock enable for GPIO"]
#[inline(always)]
pub fn apb_clk_en_gpio0(&self) -> ApbClkEnGpio0R {
ApbClkEnGpio0R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - APB clock enable for GPIO"]
#[inline(always)]
pub fn apb_clk_en_gpio1(&self) -> ApbClkEnGpio1R {
ApbClkEnGpio1R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - APB clock enable for GPIO"]
#[inline(always)]
pub fn apb_clk_en_gpio2(&self) -> ApbClkEnGpio2R {
ApbClkEnGpio2R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - APB clock enable for GPIO"]
#[inline(always)]
pub fn apb_clk_en_gpio3(&self) -> ApbClkEnGpio3R {
ApbClkEnGpio3R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - APB clock enable for GPIO"]
#[inline(always)]
pub fn apb_clk_en_gpio4(&self) -> ApbClkEnGpio4R {
ApbClkEnGpio4R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - APB clock enable for GPIO"]
#[inline(always)]
pub fn apb_clk_en_gpio5(&self) -> ApbClkEnGpio5R {
ApbClkEnGpio5R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - APB clock enable for GPIO"]
#[inline(always)]
pub fn apb_clk_en_gpio6(&self) -> ApbClkEnGpio6R {
ApbClkEnGpio6R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - APB clock enable for GPIO"]
#[inline(always)]
pub fn apb_clk_en_gpio7(&self) -> ApbClkEnGpio7R {
ApbClkEnGpio7R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12 - APB clock enable for GPIO"]
#[inline(always)]
pub fn apb_clk_en_gpio8(&self) -> ApbClkEnGpio8R {
ApbClkEnGpio8R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13 - APB clock enable for GPIO"]
#[inline(always)]
pub fn apb_clk_en_gpio9(&self) -> ApbClkEnGpio9R {
ApbClkEnGpio9R::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - APB clock enable for TIMER"]
#[inline(always)]
pub fn apb_clk_en_timer0(&self) -> ApbClkEnTimer0R {
ApbClkEnTimer0R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15 - APB clock enable for TIMER"]
#[inline(always)]
pub fn apb_clk_en_timer1(&self) -> ApbClkEnTimer1R {
ApbClkEnTimer1R::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bit 16 - APB clock enable for GPTIMER"]
#[inline(always)]
pub fn apb_clk_en_gptimer0(&self) -> ApbClkEnGptimer0R {
ApbClkEnGptimer0R::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 17 - APB clock enable for GPTIMER"]
#[inline(always)]
pub fn apb_clk_en_gptimer1(&self) -> ApbClkEnGptimer1R {
ApbClkEnGptimer1R::new(((self.bits >> 17) & 1) != 0)
}
#[doc = "Bit 18 - APB clock enable for GPTIMER"]
#[inline(always)]
pub fn apb_clk_en_gptimer2(&self) -> ApbClkEnGptimer2R {
ApbClkEnGptimer2R::new(((self.bits >> 18) & 1) != 0)
}
#[doc = "Bit 19 - APB clock enable for GPTIMER"]
#[inline(always)]
pub fn apb_clk_en_gptimer3(&self) -> ApbClkEnGptimer3R {
ApbClkEnGptimer3R::new(((self.bits >> 19) & 1) != 0)
}
#[doc = "Bit 20 - APB clock enable for GPTIMER"]
#[inline(always)]
pub fn apb_clk_en_gptimer4(&self) -> ApbClkEnGptimer4R {
ApbClkEnGptimer4R::new(((self.bits >> 20) & 1) != 0)
}
#[doc = "Bit 21 - APB clock enable for UART"]
#[inline(always)]
pub fn apb_clk_en_uart0(&self) -> ApbClkEnUart0R {
ApbClkEnUart0R::new(((self.bits >> 21) & 1) != 0)
}
#[doc = "Bit 22 - APB clock enable for UART"]
#[inline(always)]
pub fn apb_clk_en_uart1(&self) -> ApbClkEnUart1R {
ApbClkEnUart1R::new(((self.bits >> 22) & 1) != 0)
}
#[doc = "Bit 23 - APB clock enable for UART"]
#[inline(always)]
pub fn apb_clk_en_uart2(&self) -> ApbClkEnUart2R {
ApbClkEnUart2R::new(((self.bits >> 23) & 1) != 0)
}
#[doc = "Bit 24 - APB clock enable for UART"]
#[inline(always)]
pub fn apb_clk_en_uart3(&self) -> ApbClkEnUart3R {
ApbClkEnUart3R::new(((self.bits >> 24) & 1) != 0)
}
#[doc = "Bit 25 - APB clock enable for UART"]
#[inline(always)]
pub fn apb_clk_en_uart4(&self) -> ApbClkEnUart4R {
ApbClkEnUart4R::new(((self.bits >> 25) & 1) != 0)
}
#[doc = "Bit 26 - APB clock enable for CAN"]
#[inline(always)]
pub fn apb_clk_en_can0(&self) -> ApbClkEnCan0R {
ApbClkEnCan0R::new(((self.bits >> 26) & 1) != 0)
}
#[doc = "Bit 27 - APB clock enable for I2C"]
#[inline(always)]
pub fn apb_clk_en_i2c0(&self) -> ApbClkEnI2c0R {
ApbClkEnI2c0R::new(((self.bits >> 27) & 1) != 0)
}
#[doc = "Bit 28 - APB clock enable for I2C"]
#[inline(always)]
pub fn apb_clk_en_i2c1(&self) -> ApbClkEnI2c1R {
ApbClkEnI2c1R::new(((self.bits >> 28) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - APB clock enable for FCB"]
#[inline(always)]
pub fn apb_clk_en_fcb0(&mut self) -> ApbClkEnFcb0W<ApbClkEnSpec> {
ApbClkEnFcb0W::new(self, 0)
}
#[doc = "Bit 1 - APB clock enable for WATCHDOG"]
#[inline(always)]
pub fn apb_clk_en_watchdog0(&mut self) -> ApbClkEnWatchdog0W<ApbClkEnSpec> {
ApbClkEnWatchdog0W::new(self, 1)
}
#[doc = "Bit 2 - APB clock enable for SPI"]
#[inline(always)]
pub fn apb_clk_en_spi0(&mut self) -> ApbClkEnSpi0W<ApbClkEnSpec> {
ApbClkEnSpi0W::new(self, 2)
}
#[doc = "Bit 3 - APB clock enable for SPI"]
#[inline(always)]
pub fn apb_clk_en_spi1(&mut self) -> ApbClkEnSpi1W<ApbClkEnSpec> {
ApbClkEnSpi1W::new(self, 3)
}
#[doc = "Bit 4 - APB clock enable for GPIO"]
#[inline(always)]
pub fn apb_clk_en_gpio0(&mut self) -> ApbClkEnGpio0W<ApbClkEnSpec> {
ApbClkEnGpio0W::new(self, 4)
}
#[doc = "Bit 5 - APB clock enable for GPIO"]
#[inline(always)]
pub fn apb_clk_en_gpio1(&mut self) -> ApbClkEnGpio1W<ApbClkEnSpec> {
ApbClkEnGpio1W::new(self, 5)
}
#[doc = "Bit 6 - APB clock enable for GPIO"]
#[inline(always)]
pub fn apb_clk_en_gpio2(&mut self) -> ApbClkEnGpio2W<ApbClkEnSpec> {
ApbClkEnGpio2W::new(self, 6)
}
#[doc = "Bit 7 - APB clock enable for GPIO"]
#[inline(always)]
pub fn apb_clk_en_gpio3(&mut self) -> ApbClkEnGpio3W<ApbClkEnSpec> {
ApbClkEnGpio3W::new(self, 7)
}
#[doc = "Bit 8 - APB clock enable for GPIO"]
#[inline(always)]
pub fn apb_clk_en_gpio4(&mut self) -> ApbClkEnGpio4W<ApbClkEnSpec> {
ApbClkEnGpio4W::new(self, 8)
}
#[doc = "Bit 9 - APB clock enable for GPIO"]
#[inline(always)]
pub fn apb_clk_en_gpio5(&mut self) -> ApbClkEnGpio5W<ApbClkEnSpec> {
ApbClkEnGpio5W::new(self, 9)
}
#[doc = "Bit 10 - APB clock enable for GPIO"]
#[inline(always)]
pub fn apb_clk_en_gpio6(&mut self) -> ApbClkEnGpio6W<ApbClkEnSpec> {
ApbClkEnGpio6W::new(self, 10)
}
#[doc = "Bit 11 - APB clock enable for GPIO"]
#[inline(always)]
pub fn apb_clk_en_gpio7(&mut self) -> ApbClkEnGpio7W<ApbClkEnSpec> {
ApbClkEnGpio7W::new(self, 11)
}
#[doc = "Bit 12 - APB clock enable for GPIO"]
#[inline(always)]
pub fn apb_clk_en_gpio8(&mut self) -> ApbClkEnGpio8W<ApbClkEnSpec> {
ApbClkEnGpio8W::new(self, 12)
}
#[doc = "Bit 13 - APB clock enable for GPIO"]
#[inline(always)]
pub fn apb_clk_en_gpio9(&mut self) -> ApbClkEnGpio9W<ApbClkEnSpec> {
ApbClkEnGpio9W::new(self, 13)
}
#[doc = "Bit 14 - APB clock enable for TIMER"]
#[inline(always)]
pub fn apb_clk_en_timer0(&mut self) -> ApbClkEnTimer0W<ApbClkEnSpec> {
ApbClkEnTimer0W::new(self, 14)
}
#[doc = "Bit 15 - APB clock enable for TIMER"]
#[inline(always)]
pub fn apb_clk_en_timer1(&mut self) -> ApbClkEnTimer1W<ApbClkEnSpec> {
ApbClkEnTimer1W::new(self, 15)
}
#[doc = "Bit 16 - APB clock enable for GPTIMER"]
#[inline(always)]
pub fn apb_clk_en_gptimer0(&mut self) -> ApbClkEnGptimer0W<ApbClkEnSpec> {
ApbClkEnGptimer0W::new(self, 16)
}
#[doc = "Bit 17 - APB clock enable for GPTIMER"]
#[inline(always)]
pub fn apb_clk_en_gptimer1(&mut self) -> ApbClkEnGptimer1W<ApbClkEnSpec> {
ApbClkEnGptimer1W::new(self, 17)
}
#[doc = "Bit 18 - APB clock enable for GPTIMER"]
#[inline(always)]
pub fn apb_clk_en_gptimer2(&mut self) -> ApbClkEnGptimer2W<ApbClkEnSpec> {
ApbClkEnGptimer2W::new(self, 18)
}
#[doc = "Bit 19 - APB clock enable for GPTIMER"]
#[inline(always)]
pub fn apb_clk_en_gptimer3(&mut self) -> ApbClkEnGptimer3W<ApbClkEnSpec> {
ApbClkEnGptimer3W::new(self, 19)
}
#[doc = "Bit 20 - APB clock enable for GPTIMER"]
#[inline(always)]
pub fn apb_clk_en_gptimer4(&mut self) -> ApbClkEnGptimer4W<ApbClkEnSpec> {
ApbClkEnGptimer4W::new(self, 20)
}
#[doc = "Bit 21 - APB clock enable for UART"]
#[inline(always)]
pub fn apb_clk_en_uart0(&mut self) -> ApbClkEnUart0W<ApbClkEnSpec> {
ApbClkEnUart0W::new(self, 21)
}
#[doc = "Bit 22 - APB clock enable for UART"]
#[inline(always)]
pub fn apb_clk_en_uart1(&mut self) -> ApbClkEnUart1W<ApbClkEnSpec> {
ApbClkEnUart1W::new(self, 22)
}
#[doc = "Bit 23 - APB clock enable for UART"]
#[inline(always)]
pub fn apb_clk_en_uart2(&mut self) -> ApbClkEnUart2W<ApbClkEnSpec> {
ApbClkEnUart2W::new(self, 23)
}
#[doc = "Bit 24 - APB clock enable for UART"]
#[inline(always)]
pub fn apb_clk_en_uart3(&mut self) -> ApbClkEnUart3W<ApbClkEnSpec> {
ApbClkEnUart3W::new(self, 24)
}
#[doc = "Bit 25 - APB clock enable for UART"]
#[inline(always)]
pub fn apb_clk_en_uart4(&mut self) -> ApbClkEnUart4W<ApbClkEnSpec> {
ApbClkEnUart4W::new(self, 25)
}
#[doc = "Bit 26 - APB clock enable for CAN"]
#[inline(always)]
pub fn apb_clk_en_can0(&mut self) -> ApbClkEnCan0W<ApbClkEnSpec> {
ApbClkEnCan0W::new(self, 26)
}
#[doc = "Bit 27 - APB clock enable for I2C"]
#[inline(always)]
pub fn apb_clk_en_i2c0(&mut self) -> ApbClkEnI2c0W<ApbClkEnSpec> {
ApbClkEnI2c0W::new(self, 27)
}
#[doc = "Bit 28 - APB clock enable for I2C"]
#[inline(always)]
pub fn apb_clk_en_i2c1(&mut self) -> ApbClkEnI2c1W<ApbClkEnSpec> {
ApbClkEnI2c1W::new(self, 28)
}
}
#[doc = "APB peripheral clock enable\n\nYou can [`read`](crate::Reg::read) this register and get [`apb_clk_en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb_clk_en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ApbClkEnSpec;
impl crate::RegisterSpec for ApbClkEnSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`apb_clk_en::R`](R) reader structure"]
impl crate::Readable for ApbClkEnSpec {}
#[doc = "`write(|w| ..)` method takes [`apb_clk_en::W`](W) writer structure"]
impl crate::Writable for ApbClkEnSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets APB_CLK_EN to value 0"]
impl crate::Resettable for ApbClkEnSpec {}
}
#[doc = "AHB_CLK_EN (rw) register accessor: AHB peripheral clock enable\n\nYou can [`read`](crate::Reg::read) this register and get [`ahb_clk_en::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ahb_clk_en::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ahb_clk_en`] module"]
#[doc(alias = "AHB_CLK_EN")]
pub type AhbClkEn = crate::Reg<ahb_clk_en::AhbClkEnSpec>;
#[doc = "AHB peripheral clock enable"]
pub mod ahb_clk_en {
#[doc = "Register `AHB_CLK_EN` reader"]
pub type R = crate::R<AhbClkEnSpec>;
#[doc = "Register `AHB_CLK_EN` writer"]
pub type W = crate::W<AhbClkEnSpec>;
#[doc = "Field `AHB_CLK_EN_DMAC0` reader - AHB clock enable for DMAC"]
pub type AhbClkEnDmac0R = crate::BitReader;
#[doc = "Field `AHB_CLK_EN_DMAC0` writer - AHB clock enable for DMAC"]
pub type AhbClkEnDmac0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `AHB_CLK_EN_USB0` reader - AHB clock enable for USB"]
pub type AhbClkEnUsb0R = crate::BitReader;
#[doc = "Field `AHB_CLK_EN_USB0` writer - AHB clock enable for USB"]
pub type AhbClkEnUsb0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `AHB_CLK_EN_CRC0` reader - AHB clock enable for CRC"]
pub type AhbClkEnCrc0R = crate::BitReader;
#[doc = "Field `AHB_CLK_EN_CRC0` writer - AHB clock enable for CRC"]
pub type AhbClkEnCrc0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `AHB_CLK_EN_MAC0` reader - AHB clock enable for MAC"]
pub type AhbClkEnMac0R = crate::BitReader;
#[doc = "Field `AHB_CLK_EN_MAC0` writer - AHB clock enable for MAC"]
pub type AhbClkEnMac0W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - AHB clock enable for DMAC"]
#[inline(always)]
pub fn ahb_clk_en_dmac0(&self) -> AhbClkEnDmac0R {
AhbClkEnDmac0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - AHB clock enable for USB"]
#[inline(always)]
pub fn ahb_clk_en_usb0(&self) -> AhbClkEnUsb0R {
AhbClkEnUsb0R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - AHB clock enable for CRC"]
#[inline(always)]
pub fn ahb_clk_en_crc0(&self) -> AhbClkEnCrc0R {
AhbClkEnCrc0R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - AHB clock enable for MAC"]
#[inline(always)]
pub fn ahb_clk_en_mac0(&self) -> AhbClkEnMac0R {
AhbClkEnMac0R::new(((self.bits >> 3) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - AHB clock enable for DMAC"]
#[inline(always)]
pub fn ahb_clk_en_dmac0(&mut self) -> AhbClkEnDmac0W<AhbClkEnSpec> {
AhbClkEnDmac0W::new(self, 0)
}
#[doc = "Bit 1 - AHB clock enable for USB"]
#[inline(always)]
pub fn ahb_clk_en_usb0(&mut self) -> AhbClkEnUsb0W<AhbClkEnSpec> {
AhbClkEnUsb0W::new(self, 1)
}
#[doc = "Bit 2 - AHB clock enable for CRC"]
#[inline(always)]
pub fn ahb_clk_en_crc0(&mut self) -> AhbClkEnCrc0W<AhbClkEnSpec> {
AhbClkEnCrc0W::new(self, 2)
}
#[doc = "Bit 3 - AHB clock enable for MAC"]
#[inline(always)]
pub fn ahb_clk_en_mac0(&mut self) -> AhbClkEnMac0W<AhbClkEnSpec> {
AhbClkEnMac0W::new(self, 3)
}
}
#[doc = "AHB peripheral clock enable\n\nYou can [`read`](crate::Reg::read) this register and get [`ahb_clk_en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ahb_clk_en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AhbClkEnSpec;
impl crate::RegisterSpec for AhbClkEnSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ahb_clk_en::R`](R) reader structure"]
impl crate::Readable for AhbClkEnSpec {}
#[doc = "`write(|w| ..)` method takes [`ahb_clk_en::W`](W) writer structure"]
impl crate::Writable for AhbClkEnSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets AHB_CLK_EN to value 0"]
impl crate::Resettable for AhbClkEnSpec {}
}
#[doc = "APB_CLK_STOP (rw) register accessor: APB peripheral clock stop during debug\n\nYou can [`read`](crate::Reg::read) this register and get [`apb_clk_stop::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb_clk_stop::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb_clk_stop`] module"]
#[doc(alias = "APB_CLK_STOP")]
pub type ApbClkStop = crate::Reg<apb_clk_stop::ApbClkStopSpec>;
#[doc = "APB peripheral clock stop during debug"]
pub mod apb_clk_stop {
#[doc = "Register `APB_CLK_STOP` reader"]
pub type R = crate::R<ApbClkStopSpec>;
#[doc = "Register `APB_CLK_STOP` writer"]
pub type W = crate::W<ApbClkStopSpec>;
#[doc = "Field `APB_CLK_STOP_FCB0` reader - APB clock clock for FCB"]
pub type ApbClkStopFcb0R = crate::BitReader;
#[doc = "Field `APB_CLK_STOP_FCB0` writer - APB clock clock for FCB"]
pub type ApbClkStopFcb0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_CLK_STOP_WATCHDOG0` reader - APB clock clock for WATCHDOG"]
pub type ApbClkStopWatchdog0R = crate::BitReader;
#[doc = "Field `APB_CLK_STOP_WATCHDOG0` writer - APB clock clock for WATCHDOG"]
pub type ApbClkStopWatchdog0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_CLK_STOP_SPI0` reader - APB clock clock for SPI"]
pub type ApbClkStopSpi0R = crate::BitReader;
#[doc = "Field `APB_CLK_STOP_SPI0` writer - APB clock clock for SPI"]
pub type ApbClkStopSpi0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_CLK_STOP_SPI1` reader - APB clock clock for SPI"]
pub type ApbClkStopSpi1R = crate::BitReader;
#[doc = "Field `APB_CLK_STOP_SPI1` writer - APB clock clock for SPI"]
pub type ApbClkStopSpi1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_CLK_STOP_GPIO0` reader - APB clock clock for GPIO"]
pub type ApbClkStopGpio0R = crate::BitReader;
#[doc = "Field `APB_CLK_STOP_GPIO0` writer - APB clock clock for GPIO"]
pub type ApbClkStopGpio0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_CLK_STOP_GPIO1` reader - APB clock clock for GPIO"]
pub type ApbClkStopGpio1R = crate::BitReader;
#[doc = "Field `APB_CLK_STOP_GPIO1` writer - APB clock clock for GPIO"]
pub type ApbClkStopGpio1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_CLK_STOP_GPIO2` reader - APB clock clock for GPIO"]
pub type ApbClkStopGpio2R = crate::BitReader;
#[doc = "Field `APB_CLK_STOP_GPIO2` writer - APB clock clock for GPIO"]
pub type ApbClkStopGpio2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_CLK_STOP_GPIO3` reader - APB clock clock for GPIO"]
pub type ApbClkStopGpio3R = crate::BitReader;
#[doc = "Field `APB_CLK_STOP_GPIO3` writer - APB clock clock for GPIO"]
pub type ApbClkStopGpio3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_CLK_STOP_GPIO4` reader - APB clock clock for GPIO"]
pub type ApbClkStopGpio4R = crate::BitReader;
#[doc = "Field `APB_CLK_STOP_GPIO4` writer - APB clock clock for GPIO"]
pub type ApbClkStopGpio4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_CLK_STOP_GPIO5` reader - APB clock clock for GPIO"]
pub type ApbClkStopGpio5R = crate::BitReader;
#[doc = "Field `APB_CLK_STOP_GPIO5` writer - APB clock clock for GPIO"]
pub type ApbClkStopGpio5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_CLK_STOP_GPIO6` reader - APB clock clock for GPIO"]
pub type ApbClkStopGpio6R = crate::BitReader;
#[doc = "Field `APB_CLK_STOP_GPIO6` writer - APB clock clock for GPIO"]
pub type ApbClkStopGpio6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_CLK_STOP_GPIO7` reader - APB clock clock for GPIO"]
pub type ApbClkStopGpio7R = crate::BitReader;
#[doc = "Field `APB_CLK_STOP_GPIO7` writer - APB clock clock for GPIO"]
pub type ApbClkStopGpio7W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_CLK_STOP_GPIO8` reader - APB clock clock for GPIO"]
pub type ApbClkStopGpio8R = crate::BitReader;
#[doc = "Field `APB_CLK_STOP_GPIO8` writer - APB clock clock for GPIO"]
pub type ApbClkStopGpio8W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_CLK_STOP_GPIO9` reader - APB clock clock for GPIO"]
pub type ApbClkStopGpio9R = crate::BitReader;
#[doc = "Field `APB_CLK_STOP_GPIO9` writer - APB clock clock for GPIO"]
pub type ApbClkStopGpio9W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_CLK_STOP_TIMER0` reader - APB clock clock for TIMER"]
pub type ApbClkStopTimer0R = crate::BitReader;
#[doc = "Field `APB_CLK_STOP_TIMER0` writer - APB clock clock for TIMER"]
pub type ApbClkStopTimer0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_CLK_STOP_TIMER1` reader - APB clock clock for TIMER"]
pub type ApbClkStopTimer1R = crate::BitReader;
#[doc = "Field `APB_CLK_STOP_TIMER1` writer - APB clock clock for TIMER"]
pub type ApbClkStopTimer1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_CLK_STOP_GPTIMER0` reader - APB clock clock for GPTIMER"]
pub type ApbClkStopGptimer0R = crate::BitReader;
#[doc = "Field `APB_CLK_STOP_GPTIMER0` writer - APB clock clock for GPTIMER"]
pub type ApbClkStopGptimer0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_CLK_STOP_GPTIMER1` reader - APB clock clock for GPTIMER"]
pub type ApbClkStopGptimer1R = crate::BitReader;
#[doc = "Field `APB_CLK_STOP_GPTIMER1` writer - APB clock clock for GPTIMER"]
pub type ApbClkStopGptimer1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_CLK_STOP_GPTIMER2` reader - APB clock clock for GPTIMER"]
pub type ApbClkStopGptimer2R = crate::BitReader;
#[doc = "Field `APB_CLK_STOP_GPTIMER2` writer - APB clock clock for GPTIMER"]
pub type ApbClkStopGptimer2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_CLK_STOP_GPTIMER3` reader - APB clock clock for GPTIMER"]
pub type ApbClkStopGptimer3R = crate::BitReader;
#[doc = "Field `APB_CLK_STOP_GPTIMER3` writer - APB clock clock for GPTIMER"]
pub type ApbClkStopGptimer3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_CLK_STOP_GPTIMER4` reader - APB clock clock for GPTIMER"]
pub type ApbClkStopGptimer4R = crate::BitReader;
#[doc = "Field `APB_CLK_STOP_GPTIMER4` writer - APB clock clock for GPTIMER"]
pub type ApbClkStopGptimer4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_CLK_STOP_UART0` reader - APB clock clock for UART"]
pub type ApbClkStopUart0R = crate::BitReader;
#[doc = "Field `APB_CLK_STOP_UART0` writer - APB clock clock for UART"]
pub type ApbClkStopUart0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_CLK_STOP_UART1` reader - APB clock clock for UART"]
pub type ApbClkStopUart1R = crate::BitReader;
#[doc = "Field `APB_CLK_STOP_UART1` writer - APB clock clock for UART"]
pub type ApbClkStopUart1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_CLK_STOP_UART2` reader - APB clock clock for UART"]
pub type ApbClkStopUart2R = crate::BitReader;
#[doc = "Field `APB_CLK_STOP_UART2` writer - APB clock clock for UART"]
pub type ApbClkStopUart2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_CLK_STOP_UART3` reader - APB clock clock for UART"]
pub type ApbClkStopUart3R = crate::BitReader;
#[doc = "Field `APB_CLK_STOP_UART3` writer - APB clock clock for UART"]
pub type ApbClkStopUart3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_CLK_STOP_UART4` reader - APB clock clock for UART"]
pub type ApbClkStopUart4R = crate::BitReader;
#[doc = "Field `APB_CLK_STOP_UART4` writer - APB clock clock for UART"]
pub type ApbClkStopUart4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_CLK_STOP_CAN0` reader - APB clock clock for CAN"]
pub type ApbClkStopCan0R = crate::BitReader;
#[doc = "Field `APB_CLK_STOP_CAN0` writer - APB clock clock for CAN"]
pub type ApbClkStopCan0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_CLK_STOP_I2C0` reader - APB clock clock for I2C"]
pub type ApbClkStopI2c0R = crate::BitReader;
#[doc = "Field `APB_CLK_STOP_I2C0` writer - APB clock clock for I2C"]
pub type ApbClkStopI2c0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `APB_CLK_STOP_I2C1` reader - APB clock clock for I2C"]
pub type ApbClkStopI2c1R = crate::BitReader;
#[doc = "Field `APB_CLK_STOP_I2C1` writer - APB clock clock for I2C"]
pub type ApbClkStopI2c1W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - APB clock clock for FCB"]
#[inline(always)]
pub fn apb_clk_stop_fcb0(&self) -> ApbClkStopFcb0R {
ApbClkStopFcb0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - APB clock clock for WATCHDOG"]
#[inline(always)]
pub fn apb_clk_stop_watchdog0(&self) -> ApbClkStopWatchdog0R {
ApbClkStopWatchdog0R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - APB clock clock for SPI"]
#[inline(always)]
pub fn apb_clk_stop_spi0(&self) -> ApbClkStopSpi0R {
ApbClkStopSpi0R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - APB clock clock for SPI"]
#[inline(always)]
pub fn apb_clk_stop_spi1(&self) -> ApbClkStopSpi1R {
ApbClkStopSpi1R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - APB clock clock for GPIO"]
#[inline(always)]
pub fn apb_clk_stop_gpio0(&self) -> ApbClkStopGpio0R {
ApbClkStopGpio0R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - APB clock clock for GPIO"]
#[inline(always)]
pub fn apb_clk_stop_gpio1(&self) -> ApbClkStopGpio1R {
ApbClkStopGpio1R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - APB clock clock for GPIO"]
#[inline(always)]
pub fn apb_clk_stop_gpio2(&self) -> ApbClkStopGpio2R {
ApbClkStopGpio2R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - APB clock clock for GPIO"]
#[inline(always)]
pub fn apb_clk_stop_gpio3(&self) -> ApbClkStopGpio3R {
ApbClkStopGpio3R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - APB clock clock for GPIO"]
#[inline(always)]
pub fn apb_clk_stop_gpio4(&self) -> ApbClkStopGpio4R {
ApbClkStopGpio4R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - APB clock clock for GPIO"]
#[inline(always)]
pub fn apb_clk_stop_gpio5(&self) -> ApbClkStopGpio5R {
ApbClkStopGpio5R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - APB clock clock for GPIO"]
#[inline(always)]
pub fn apb_clk_stop_gpio6(&self) -> ApbClkStopGpio6R {
ApbClkStopGpio6R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - APB clock clock for GPIO"]
#[inline(always)]
pub fn apb_clk_stop_gpio7(&self) -> ApbClkStopGpio7R {
ApbClkStopGpio7R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12 - APB clock clock for GPIO"]
#[inline(always)]
pub fn apb_clk_stop_gpio8(&self) -> ApbClkStopGpio8R {
ApbClkStopGpio8R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13 - APB clock clock for GPIO"]
#[inline(always)]
pub fn apb_clk_stop_gpio9(&self) -> ApbClkStopGpio9R {
ApbClkStopGpio9R::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - APB clock clock for TIMER"]
#[inline(always)]
pub fn apb_clk_stop_timer0(&self) -> ApbClkStopTimer0R {
ApbClkStopTimer0R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15 - APB clock clock for TIMER"]
#[inline(always)]
pub fn apb_clk_stop_timer1(&self) -> ApbClkStopTimer1R {
ApbClkStopTimer1R::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bit 16 - APB clock clock for GPTIMER"]
#[inline(always)]
pub fn apb_clk_stop_gptimer0(&self) -> ApbClkStopGptimer0R {
ApbClkStopGptimer0R::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 17 - APB clock clock for GPTIMER"]
#[inline(always)]
pub fn apb_clk_stop_gptimer1(&self) -> ApbClkStopGptimer1R {
ApbClkStopGptimer1R::new(((self.bits >> 17) & 1) != 0)
}
#[doc = "Bit 18 - APB clock clock for GPTIMER"]
#[inline(always)]
pub fn apb_clk_stop_gptimer2(&self) -> ApbClkStopGptimer2R {
ApbClkStopGptimer2R::new(((self.bits >> 18) & 1) != 0)
}
#[doc = "Bit 19 - APB clock clock for GPTIMER"]
#[inline(always)]
pub fn apb_clk_stop_gptimer3(&self) -> ApbClkStopGptimer3R {
ApbClkStopGptimer3R::new(((self.bits >> 19) & 1) != 0)
}
#[doc = "Bit 20 - APB clock clock for GPTIMER"]
#[inline(always)]
pub fn apb_clk_stop_gptimer4(&self) -> ApbClkStopGptimer4R {
ApbClkStopGptimer4R::new(((self.bits >> 20) & 1) != 0)
}
#[doc = "Bit 21 - APB clock clock for UART"]
#[inline(always)]
pub fn apb_clk_stop_uart0(&self) -> ApbClkStopUart0R {
ApbClkStopUart0R::new(((self.bits >> 21) & 1) != 0)
}
#[doc = "Bit 22 - APB clock clock for UART"]
#[inline(always)]
pub fn apb_clk_stop_uart1(&self) -> ApbClkStopUart1R {
ApbClkStopUart1R::new(((self.bits >> 22) & 1) != 0)
}
#[doc = "Bit 23 - APB clock clock for UART"]
#[inline(always)]
pub fn apb_clk_stop_uart2(&self) -> ApbClkStopUart2R {
ApbClkStopUart2R::new(((self.bits >> 23) & 1) != 0)
}
#[doc = "Bit 24 - APB clock clock for UART"]
#[inline(always)]
pub fn apb_clk_stop_uart3(&self) -> ApbClkStopUart3R {
ApbClkStopUart3R::new(((self.bits >> 24) & 1) != 0)
}
#[doc = "Bit 25 - APB clock clock for UART"]
#[inline(always)]
pub fn apb_clk_stop_uart4(&self) -> ApbClkStopUart4R {
ApbClkStopUart4R::new(((self.bits >> 25) & 1) != 0)
}
#[doc = "Bit 26 - APB clock clock for CAN"]
#[inline(always)]
pub fn apb_clk_stop_can0(&self) -> ApbClkStopCan0R {
ApbClkStopCan0R::new(((self.bits >> 26) & 1) != 0)
}
#[doc = "Bit 27 - APB clock clock for I2C"]
#[inline(always)]
pub fn apb_clk_stop_i2c0(&self) -> ApbClkStopI2c0R {
ApbClkStopI2c0R::new(((self.bits >> 27) & 1) != 0)
}
#[doc = "Bit 28 - APB clock clock for I2C"]
#[inline(always)]
pub fn apb_clk_stop_i2c1(&self) -> ApbClkStopI2c1R {
ApbClkStopI2c1R::new(((self.bits >> 28) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - APB clock clock for FCB"]
#[inline(always)]
pub fn apb_clk_stop_fcb0(&mut self) -> ApbClkStopFcb0W<ApbClkStopSpec> {
ApbClkStopFcb0W::new(self, 0)
}
#[doc = "Bit 1 - APB clock clock for WATCHDOG"]
#[inline(always)]
pub fn apb_clk_stop_watchdog0(&mut self) -> ApbClkStopWatchdog0W<ApbClkStopSpec> {
ApbClkStopWatchdog0W::new(self, 1)
}
#[doc = "Bit 2 - APB clock clock for SPI"]
#[inline(always)]
pub fn apb_clk_stop_spi0(&mut self) -> ApbClkStopSpi0W<ApbClkStopSpec> {
ApbClkStopSpi0W::new(self, 2)
}
#[doc = "Bit 3 - APB clock clock for SPI"]
#[inline(always)]
pub fn apb_clk_stop_spi1(&mut self) -> ApbClkStopSpi1W<ApbClkStopSpec> {
ApbClkStopSpi1W::new(self, 3)
}
#[doc = "Bit 4 - APB clock clock for GPIO"]
#[inline(always)]
pub fn apb_clk_stop_gpio0(&mut self) -> ApbClkStopGpio0W<ApbClkStopSpec> {
ApbClkStopGpio0W::new(self, 4)
}
#[doc = "Bit 5 - APB clock clock for GPIO"]
#[inline(always)]
pub fn apb_clk_stop_gpio1(&mut self) -> ApbClkStopGpio1W<ApbClkStopSpec> {
ApbClkStopGpio1W::new(self, 5)
}
#[doc = "Bit 6 - APB clock clock for GPIO"]
#[inline(always)]
pub fn apb_clk_stop_gpio2(&mut self) -> ApbClkStopGpio2W<ApbClkStopSpec> {
ApbClkStopGpio2W::new(self, 6)
}
#[doc = "Bit 7 - APB clock clock for GPIO"]
#[inline(always)]
pub fn apb_clk_stop_gpio3(&mut self) -> ApbClkStopGpio3W<ApbClkStopSpec> {
ApbClkStopGpio3W::new(self, 7)
}
#[doc = "Bit 8 - APB clock clock for GPIO"]
#[inline(always)]
pub fn apb_clk_stop_gpio4(&mut self) -> ApbClkStopGpio4W<ApbClkStopSpec> {
ApbClkStopGpio4W::new(self, 8)
}
#[doc = "Bit 9 - APB clock clock for GPIO"]
#[inline(always)]
pub fn apb_clk_stop_gpio5(&mut self) -> ApbClkStopGpio5W<ApbClkStopSpec> {
ApbClkStopGpio5W::new(self, 9)
}
#[doc = "Bit 10 - APB clock clock for GPIO"]
#[inline(always)]
pub fn apb_clk_stop_gpio6(&mut self) -> ApbClkStopGpio6W<ApbClkStopSpec> {
ApbClkStopGpio6W::new(self, 10)
}
#[doc = "Bit 11 - APB clock clock for GPIO"]
#[inline(always)]
pub fn apb_clk_stop_gpio7(&mut self) -> ApbClkStopGpio7W<ApbClkStopSpec> {
ApbClkStopGpio7W::new(self, 11)
}
#[doc = "Bit 12 - APB clock clock for GPIO"]
#[inline(always)]
pub fn apb_clk_stop_gpio8(&mut self) -> ApbClkStopGpio8W<ApbClkStopSpec> {
ApbClkStopGpio8W::new(self, 12)
}
#[doc = "Bit 13 - APB clock clock for GPIO"]
#[inline(always)]
pub fn apb_clk_stop_gpio9(&mut self) -> ApbClkStopGpio9W<ApbClkStopSpec> {
ApbClkStopGpio9W::new(self, 13)
}
#[doc = "Bit 14 - APB clock clock for TIMER"]
#[inline(always)]
pub fn apb_clk_stop_timer0(&mut self) -> ApbClkStopTimer0W<ApbClkStopSpec> {
ApbClkStopTimer0W::new(self, 14)
}
#[doc = "Bit 15 - APB clock clock for TIMER"]
#[inline(always)]
pub fn apb_clk_stop_timer1(&mut self) -> ApbClkStopTimer1W<ApbClkStopSpec> {
ApbClkStopTimer1W::new(self, 15)
}
#[doc = "Bit 16 - APB clock clock for GPTIMER"]
#[inline(always)]
pub fn apb_clk_stop_gptimer0(&mut self) -> ApbClkStopGptimer0W<ApbClkStopSpec> {
ApbClkStopGptimer0W::new(self, 16)
}
#[doc = "Bit 17 - APB clock clock for GPTIMER"]
#[inline(always)]
pub fn apb_clk_stop_gptimer1(&mut self) -> ApbClkStopGptimer1W<ApbClkStopSpec> {
ApbClkStopGptimer1W::new(self, 17)
}
#[doc = "Bit 18 - APB clock clock for GPTIMER"]
#[inline(always)]
pub fn apb_clk_stop_gptimer2(&mut self) -> ApbClkStopGptimer2W<ApbClkStopSpec> {
ApbClkStopGptimer2W::new(self, 18)
}
#[doc = "Bit 19 - APB clock clock for GPTIMER"]
#[inline(always)]
pub fn apb_clk_stop_gptimer3(&mut self) -> ApbClkStopGptimer3W<ApbClkStopSpec> {
ApbClkStopGptimer3W::new(self, 19)
}
#[doc = "Bit 20 - APB clock clock for GPTIMER"]
#[inline(always)]
pub fn apb_clk_stop_gptimer4(&mut self) -> ApbClkStopGptimer4W<ApbClkStopSpec> {
ApbClkStopGptimer4W::new(self, 20)
}
#[doc = "Bit 21 - APB clock clock for UART"]
#[inline(always)]
pub fn apb_clk_stop_uart0(&mut self) -> ApbClkStopUart0W<ApbClkStopSpec> {
ApbClkStopUart0W::new(self, 21)
}
#[doc = "Bit 22 - APB clock clock for UART"]
#[inline(always)]
pub fn apb_clk_stop_uart1(&mut self) -> ApbClkStopUart1W<ApbClkStopSpec> {
ApbClkStopUart1W::new(self, 22)
}
#[doc = "Bit 23 - APB clock clock for UART"]
#[inline(always)]
pub fn apb_clk_stop_uart2(&mut self) -> ApbClkStopUart2W<ApbClkStopSpec> {
ApbClkStopUart2W::new(self, 23)
}
#[doc = "Bit 24 - APB clock clock for UART"]
#[inline(always)]
pub fn apb_clk_stop_uart3(&mut self) -> ApbClkStopUart3W<ApbClkStopSpec> {
ApbClkStopUart3W::new(self, 24)
}
#[doc = "Bit 25 - APB clock clock for UART"]
#[inline(always)]
pub fn apb_clk_stop_uart4(&mut self) -> ApbClkStopUart4W<ApbClkStopSpec> {
ApbClkStopUart4W::new(self, 25)
}
#[doc = "Bit 26 - APB clock clock for CAN"]
#[inline(always)]
pub fn apb_clk_stop_can0(&mut self) -> ApbClkStopCan0W<ApbClkStopSpec> {
ApbClkStopCan0W::new(self, 26)
}
#[doc = "Bit 27 - APB clock clock for I2C"]
#[inline(always)]
pub fn apb_clk_stop_i2c0(&mut self) -> ApbClkStopI2c0W<ApbClkStopSpec> {
ApbClkStopI2c0W::new(self, 27)
}
#[doc = "Bit 28 - APB clock clock for I2C"]
#[inline(always)]
pub fn apb_clk_stop_i2c1(&mut self) -> ApbClkStopI2c1W<ApbClkStopSpec> {
ApbClkStopI2c1W::new(self, 28)
}
}
#[doc = "APB peripheral clock stop during debug\n\nYou can [`read`](crate::Reg::read) this register and get [`apb_clk_stop::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb_clk_stop::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ApbClkStopSpec;
impl crate::RegisterSpec for ApbClkStopSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`apb_clk_stop::R`](R) reader structure"]
impl crate::Readable for ApbClkStopSpec {}
#[doc = "`write(|w| ..)` method takes [`apb_clk_stop::W`](W) writer structure"]
impl crate::Writable for ApbClkStopSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets APB_CLK_STOP to value 0"]
impl crate::Resettable for ApbClkStopSpec {}
}
#[doc = "DEVICE_ID (r) register accessor: Device ID code\n\nYou can [`read`](crate::Reg::read) this register and get [`device_id::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@device_id`] module"]
#[doc(alias = "DEVICE_ID")]
pub type DeviceId = crate::Reg<device_id::DeviceIdSpec>;
#[doc = "Device ID code"]
pub mod device_id {
#[doc = "Register `DEVICE_ID` reader"]
pub type R = crate::R<DeviceIdSpec>;
#[doc = "Field `DEVICE_ID` reader - Device ID code"]
pub type DeviceIdR = crate::FieldReader<u32>;
impl R {
#[doc = "Bits 0:31 - Device ID code"]
#[inline(always)]
pub fn device_id(&self) -> DeviceIdR {
DeviceIdR::new(self.bits)
}
}
#[doc = "Device ID code\n\nYou can [`read`](crate::Reg::read) this register and get [`device_id::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DeviceIdSpec;
impl crate::RegisterSpec for DeviceIdSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`device_id::R`](R) reader structure"]
impl crate::Readable for DeviceIdSpec {}
#[doc = "`reset()` method sets DEVICE_ID to value 0"]
impl crate::Resettable for DeviceIdSpec {}
}
}
#[doc = "Flash controller"]
pub type Flash = crate::Periph<flash::RegisterBlock, 0x4000_1000>;
impl core::fmt::Debug for Flash {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Flash").finish()
}
}
#[doc = "Flash controller"]
pub mod flash {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
_reserved0: [u8; 0x04],
flash_keyr: FlashKeyr,
flash_optkeyr: FlashOptkeyr,
flash_sr: FlashSr,
flash_cr: FlashCr,
flash_ar: FlashAr,
_reserved5: [u8; 0x04],
flash_obr: FlashObr,
flash_wrpr: FlashWrpr,
flash_config: FlashConfig,
flash_dma_data: FlashDmaData,
flash_read_ctrl: FlashReadCtrl,
flash_read_data: FlashReadData,
}
impl RegisterBlock {
#[doc = "0x04 - Flash key register"]
#[inline(always)]
pub const fn flash_keyr(&self) -> &FlashKeyr {
&self.flash_keyr
}
#[doc = "0x08 - Flash OPTKEY register"]
#[inline(always)]
pub const fn flash_optkeyr(&self) -> &FlashOptkeyr {
&self.flash_optkeyr
}
#[doc = "0x0c - Flash status register"]
#[inline(always)]
pub const fn flash_sr(&self) -> &FlashSr {
&self.flash_sr
}
#[doc = "0x10 - Flash control register"]
#[inline(always)]
pub const fn flash_cr(&self) -> &FlashCr {
&self.flash_cr
}
#[doc = "0x14 - Flash address register"]
#[inline(always)]
pub const fn flash_ar(&self) -> &FlashAr {
&self.flash_ar
}
#[doc = "0x1c - Option byte register"]
#[inline(always)]
pub const fn flash_obr(&self) -> &FlashObr {
&self.flash_obr
}
#[doc = "0x20 - Write protection register"]
#[inline(always)]
pub const fn flash_wrpr(&self) -> &FlashWrpr {
&self.flash_wrpr
}
#[doc = "0x24 - Flash configuratioin"]
#[inline(always)]
pub const fn flash_config(&self) -> &FlashConfig {
&self.flash_config
}
#[doc = "0x28 - Flash dma data"]
#[inline(always)]
pub const fn flash_dma_data(&self) -> &FlashDmaData {
&self.flash_dma_data
}
#[doc = "0x2c - Flash read ctrl"]
#[inline(always)]
pub const fn flash_read_ctrl(&self) -> &FlashReadCtrl {
&self.flash_read_ctrl
}
#[doc = "0x30 - Flash read data"]
#[inline(always)]
pub const fn flash_read_data(&self) -> &FlashReadData {
&self.flash_read_data
}
}
#[doc = "FLASH_KEYR (rw) register accessor: Flash key register\n\nYou can [`read`](crate::Reg::read) this register and get [`flash_keyr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flash_keyr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flash_keyr`] module"]
#[doc(alias = "FLASH_KEYR")]
pub type FlashKeyr = crate::Reg<flash_keyr::FlashKeyrSpec>;
#[doc = "Flash key register"]
pub mod flash_keyr {
#[doc = "Register `FLASH_KEYR` reader"]
pub type R = crate::R<FlashKeyrSpec>;
#[doc = "Register `FLASH_KEYR` writer"]
pub type W = crate::W<FlashKeyrSpec>;
#[doc = "Field `FLASH_KEYR` reader - Flash key register"]
pub type FlashKeyrR = crate::FieldReader<u32>;
#[doc = "Field `FLASH_KEYR` writer - Flash key register"]
pub type FlashKeyrW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - Flash key register"]
#[inline(always)]
pub fn flash_keyr(&self) -> FlashKeyrR {
FlashKeyrR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - Flash key register"]
#[inline(always)]
pub fn flash_keyr(&mut self) -> FlashKeyrW<FlashKeyrSpec> {
FlashKeyrW::new(self, 0)
}
}
#[doc = "Flash key register\n\nYou can [`read`](crate::Reg::read) this register and get [`flash_keyr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flash_keyr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FlashKeyrSpec;
impl crate::RegisterSpec for FlashKeyrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`flash_keyr::R`](R) reader structure"]
impl crate::Readable for FlashKeyrSpec {}
#[doc = "`write(|w| ..)` method takes [`flash_keyr::W`](W) writer structure"]
impl crate::Writable for FlashKeyrSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets FLASH_KEYR to value 0"]
impl crate::Resettable for FlashKeyrSpec {}
}
#[doc = "FLASH_OPTKEYR (rw) register accessor: Flash OPTKEY register\n\nYou can [`read`](crate::Reg::read) this register and get [`flash_optkeyr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flash_optkeyr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flash_optkeyr`] module"]
#[doc(alias = "FLASH_OPTKEYR")]
pub type FlashOptkeyr = crate::Reg<flash_optkeyr::FlashOptkeyrSpec>;
#[doc = "Flash OPTKEY register"]
pub mod flash_optkeyr {
#[doc = "Register `FLASH_OPTKEYR` reader"]
pub type R = crate::R<FlashOptkeyrSpec>;
#[doc = "Register `FLASH_OPTKEYR` writer"]
pub type W = crate::W<FlashOptkeyrSpec>;
#[doc = "Field `FLASH_OPTKEYR` reader - Flash OPTKEY register"]
pub type FlashOptkeyrR = crate::FieldReader<u32>;
#[doc = "Field `FLASH_OPTKEYR` writer - Flash OPTKEY register"]
pub type FlashOptkeyrW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - Flash OPTKEY register"]
#[inline(always)]
pub fn flash_optkeyr(&self) -> FlashOptkeyrR {
FlashOptkeyrR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - Flash OPTKEY register"]
#[inline(always)]
pub fn flash_optkeyr(&mut self) -> FlashOptkeyrW<FlashOptkeyrSpec> {
FlashOptkeyrW::new(self, 0)
}
}
#[doc = "Flash OPTKEY register\n\nYou can [`read`](crate::Reg::read) this register and get [`flash_optkeyr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flash_optkeyr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FlashOptkeyrSpec;
impl crate::RegisterSpec for FlashOptkeyrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`flash_optkeyr::R`](R) reader structure"]
impl crate::Readable for FlashOptkeyrSpec {}
#[doc = "`write(|w| ..)` method takes [`flash_optkeyr::W`](W) writer structure"]
impl crate::Writable for FlashOptkeyrSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets FLASH_OPTKEYR to value 0"]
impl crate::Resettable for FlashOptkeyrSpec {}
}
#[doc = "FLASH_SR (rw) register accessor: Flash status register\n\nYou can [`read`](crate::Reg::read) this register and get [`flash_sr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flash_sr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flash_sr`] module"]
#[doc(alias = "FLASH_SR")]
pub type FlashSr = crate::Reg<flash_sr::FlashSrSpec>;
#[doc = "Flash status register"]
pub mod flash_sr {
#[doc = "Register `FLASH_SR` reader"]
pub type R = crate::R<FlashSrSpec>;
#[doc = "Register `FLASH_SR` writer"]
pub type W = crate::W<FlashSrSpec>;
#[doc = "Field `FLASH_SR_BSY` reader - Flash busy"]
pub type FlashSrBsyR = crate::BitReader;
#[doc = "Field `FLASH_SR_PGERR` reader - Programming error"]
pub type FlashSrPgerrR = crate::BitReader;
#[doc = "Field `FLASH_SR_PGERR` writer - Programming error"]
pub type FlashSrPgerrW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `FLASH_SR_WRPRTERR` reader - Write protection error"]
pub type FlashSrWrprterrR = crate::BitReader;
#[doc = "Field `FLASH_SR_WRPRTERR` writer - Write protection error"]
pub type FlashSrWrprterrW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `FLASH_SR_EOP` reader - End of operation"]
pub type FlashSrEopR = crate::BitReader;
#[doc = "Field `FLASH_SR_EOP` writer - End of operation"]
pub type FlashSrEopW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - Flash busy"]
#[inline(always)]
pub fn flash_sr_bsy(&self) -> FlashSrBsyR {
FlashSrBsyR::new((self.bits & 1) != 0)
}
#[doc = "Bit 2 - Programming error"]
#[inline(always)]
pub fn flash_sr_pgerr(&self) -> FlashSrPgerrR {
FlashSrPgerrR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 4 - Write protection error"]
#[inline(always)]
pub fn flash_sr_wrprterr(&self) -> FlashSrWrprterrR {
FlashSrWrprterrR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - End of operation"]
#[inline(always)]
pub fn flash_sr_eop(&self) -> FlashSrEopR {
FlashSrEopR::new(((self.bits >> 5) & 1) != 0)
}
}
impl W {
#[doc = "Bit 2 - Programming error"]
#[inline(always)]
pub fn flash_sr_pgerr(&mut self) -> FlashSrPgerrW<FlashSrSpec> {
FlashSrPgerrW::new(self, 2)
}
#[doc = "Bit 4 - Write protection error"]
#[inline(always)]
pub fn flash_sr_wrprterr(&mut self) -> FlashSrWrprterrW<FlashSrSpec> {
FlashSrWrprterrW::new(self, 4)
}
#[doc = "Bit 5 - End of operation"]
#[inline(always)]
pub fn flash_sr_eop(&mut self) -> FlashSrEopW<FlashSrSpec> {
FlashSrEopW::new(self, 5)
}
}
#[doc = "Flash status register\n\nYou can [`read`](crate::Reg::read) this register and get [`flash_sr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flash_sr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FlashSrSpec;
impl crate::RegisterSpec for FlashSrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`flash_sr::R`](R) reader structure"]
impl crate::Readable for FlashSrSpec {}
#[doc = "`write(|w| ..)` method takes [`flash_sr::W`](W) writer structure"]
impl crate::Writable for FlashSrSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets FLASH_SR to value 0"]
impl crate::Resettable for FlashSrSpec {}
}
#[doc = "FLASH_CR (rw) register accessor: Flash control register\n\nYou can [`read`](crate::Reg::read) this register and get [`flash_cr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flash_cr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flash_cr`] module"]
#[doc(alias = "FLASH_CR")]
pub type FlashCr = crate::Reg<flash_cr::FlashCrSpec>;
#[doc = "Flash control register"]
pub mod flash_cr {
#[doc = "Register `FLASH_CR` reader"]
pub type R = crate::R<FlashCrSpec>;
#[doc = "Register `FLASH_CR` writer"]
pub type W = crate::W<FlashCrSpec>;
#[doc = "Field `FLASH_CR_PG` reader - Flash programming"]
pub type FlashCrPgR = crate::BitReader;
#[doc = "Field `FLASH_CR_PG` writer - Flash programming"]
pub type FlashCrPgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `FLASH_CR_PER` reader - Flash page erase"]
pub type FlashCrPerR = crate::BitReader;
#[doc = "Field `FLASH_CR_PER` writer - Flash page erase"]
pub type FlashCrPerW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `FLASH_CR_MER` reader - Flash mass erase"]
pub type FlashCrMerR = crate::BitReader;
#[doc = "Field `FLASH_CR_MER` writer - Flash mass erase"]
pub type FlashCrMerW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `FLASH_CR_BER` reader - Flash block erase"]
pub type FlashCrBerR = crate::BitReader;
#[doc = "Field `FLASH_CR_BER` writer - Flash block erase"]
pub type FlashCrBerW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `FLASH_CR_OPTPG` reader - Option byte programming"]
pub type FlashCrOptpgR = crate::BitReader;
#[doc = "Field `FLASH_CR_OPTPG` writer - Option byte programming"]
pub type FlashCrOptpgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `FLASH_CR_OPTER` reader - Option byte erase"]
pub type FlashCrOpterR = crate::BitReader;
#[doc = "Field `FLASH_CR_OPTER` writer - Option byte erase"]
pub type FlashCrOpterW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `FLASH_CR_STRT` reader - Flash erase start"]
pub type FlashCrStrtR = crate::BitReader;
#[doc = "Field `FLASH_CR_STRT` writer - Flash erase start"]
pub type FlashCrStrtW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `FLASH_CR_LOCK` reader - Flash lock"]
pub type FlashCrLockR = crate::BitReader;
#[doc = "Field `FLASH_CR_LOCK` writer - Flash lock"]
pub type FlashCrLockW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `FLASH_CR_OPTWRE` reader - Option bytes write enable"]
pub type FlashCrOptwreR = crate::BitReader;
#[doc = "Field `FLASH_CR_OPTWRE` writer - Option bytes write enable"]
pub type FlashCrOptwreW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `FLASH_CR_ERRIE` reader - Error interrupt enable"]
pub type FlashCrErrieR = crate::BitReader;
#[doc = "Field `FLASH_CR_ERRIE` writer - Error interrupt enable"]
pub type FlashCrErrieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `FLASH_CR_EOPIE` reader - End of operation interrupt enable"]
pub type FlashCrEopieR = crate::BitReader;
#[doc = "Field `FLASH_CR_EOPIE` writer - End of operation interrupt enable"]
pub type FlashCrEopieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `FLASH_CR_READ` reader - Flash flexible read"]
pub type FlashCrReadR = crate::BitReader;
#[doc = "Field `FLASH_CR_READ` writer - Flash flexible read"]
pub type FlashCrReadW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `FLASH_CR_FASTPG` reader - Flash fast programming"]
pub type FlashCrFastpgR = crate::BitReader;
#[doc = "Field `FLASH_CR_FASTPG` writer - Flash fast programming"]
pub type FlashCrFastpgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `FLASH_CR_DMA` reader - Flash DMA programming"]
pub type FlashCrDmaR = crate::BitReader;
#[doc = "Field `FLASH_CR_DMA` writer - Flash DMA programming"]
pub type FlashCrDmaW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `FLASH_CR_STDBY` reader - Flash standby, which disables fast read"]
pub type FlashCrStdbyR = crate::BitReader;
#[doc = "Field `FLASH_CR_STDBY` writer - Flash standby, which disables fast read"]
pub type FlashCrStdbyW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `FLASH_CR_NO_PD` reader - Flash no power down"]
pub type FlashCrNoPdR = crate::BitReader;
#[doc = "Field `FLASH_CR_NO_PD` writer - Flash no power down"]
pub type FlashCrNoPdW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - Flash programming"]
#[inline(always)]
pub fn flash_cr_pg(&self) -> FlashCrPgR {
FlashCrPgR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Flash page erase"]
#[inline(always)]
pub fn flash_cr_per(&self) -> FlashCrPerR {
FlashCrPerR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Flash mass erase"]
#[inline(always)]
pub fn flash_cr_mer(&self) -> FlashCrMerR {
FlashCrMerR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Flash block erase"]
#[inline(always)]
pub fn flash_cr_ber(&self) -> FlashCrBerR {
FlashCrBerR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Option byte programming"]
#[inline(always)]
pub fn flash_cr_optpg(&self) -> FlashCrOptpgR {
FlashCrOptpgR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Option byte erase"]
#[inline(always)]
pub fn flash_cr_opter(&self) -> FlashCrOpterR {
FlashCrOpterR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Flash erase start"]
#[inline(always)]
pub fn flash_cr_strt(&self) -> FlashCrStrtR {
FlashCrStrtR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Flash lock"]
#[inline(always)]
pub fn flash_cr_lock(&self) -> FlashCrLockR {
FlashCrLockR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 9 - Option bytes write enable"]
#[inline(always)]
pub fn flash_cr_optwre(&self) -> FlashCrOptwreR {
FlashCrOptwreR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - Error interrupt enable"]
#[inline(always)]
pub fn flash_cr_errie(&self) -> FlashCrErrieR {
FlashCrErrieR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 12 - End of operation interrupt enable"]
#[inline(always)]
pub fn flash_cr_eopie(&self) -> FlashCrEopieR {
FlashCrEopieR::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 14 - Flash flexible read"]
#[inline(always)]
pub fn flash_cr_read(&self) -> FlashCrReadR {
FlashCrReadR::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15 - Flash fast programming"]
#[inline(always)]
pub fn flash_cr_fastpg(&self) -> FlashCrFastpgR {
FlashCrFastpgR::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bit 16 - Flash DMA programming"]
#[inline(always)]
pub fn flash_cr_dma(&self) -> FlashCrDmaR {
FlashCrDmaR::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 17 - Flash standby, which disables fast read"]
#[inline(always)]
pub fn flash_cr_stdby(&self) -> FlashCrStdbyR {
FlashCrStdbyR::new(((self.bits >> 17) & 1) != 0)
}
#[doc = "Bit 18 - Flash no power down"]
#[inline(always)]
pub fn flash_cr_no_pd(&self) -> FlashCrNoPdR {
FlashCrNoPdR::new(((self.bits >> 18) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Flash programming"]
#[inline(always)]
pub fn flash_cr_pg(&mut self) -> FlashCrPgW<FlashCrSpec> {
FlashCrPgW::new(self, 0)
}
#[doc = "Bit 1 - Flash page erase"]
#[inline(always)]
pub fn flash_cr_per(&mut self) -> FlashCrPerW<FlashCrSpec> {
FlashCrPerW::new(self, 1)
}
#[doc = "Bit 2 - Flash mass erase"]
#[inline(always)]
pub fn flash_cr_mer(&mut self) -> FlashCrMerW<FlashCrSpec> {
FlashCrMerW::new(self, 2)
}
#[doc = "Bit 3 - Flash block erase"]
#[inline(always)]
pub fn flash_cr_ber(&mut self) -> FlashCrBerW<FlashCrSpec> {
FlashCrBerW::new(self, 3)
}
#[doc = "Bit 4 - Option byte programming"]
#[inline(always)]
pub fn flash_cr_optpg(&mut self) -> FlashCrOptpgW<FlashCrSpec> {
FlashCrOptpgW::new(self, 4)
}
#[doc = "Bit 5 - Option byte erase"]
#[inline(always)]
pub fn flash_cr_opter(&mut self) -> FlashCrOpterW<FlashCrSpec> {
FlashCrOpterW::new(self, 5)
}
#[doc = "Bit 6 - Flash erase start"]
#[inline(always)]
pub fn flash_cr_strt(&mut self) -> FlashCrStrtW<FlashCrSpec> {
FlashCrStrtW::new(self, 6)
}
#[doc = "Bit 7 - Flash lock"]
#[inline(always)]
pub fn flash_cr_lock(&mut self) -> FlashCrLockW<FlashCrSpec> {
FlashCrLockW::new(self, 7)
}
#[doc = "Bit 9 - Option bytes write enable"]
#[inline(always)]
pub fn flash_cr_optwre(&mut self) -> FlashCrOptwreW<FlashCrSpec> {
FlashCrOptwreW::new(self, 9)
}
#[doc = "Bit 10 - Error interrupt enable"]
#[inline(always)]
pub fn flash_cr_errie(&mut self) -> FlashCrErrieW<FlashCrSpec> {
FlashCrErrieW::new(self, 10)
}
#[doc = "Bit 12 - End of operation interrupt enable"]
#[inline(always)]
pub fn flash_cr_eopie(&mut self) -> FlashCrEopieW<FlashCrSpec> {
FlashCrEopieW::new(self, 12)
}
#[doc = "Bit 14 - Flash flexible read"]
#[inline(always)]
pub fn flash_cr_read(&mut self) -> FlashCrReadW<FlashCrSpec> {
FlashCrReadW::new(self, 14)
}
#[doc = "Bit 15 - Flash fast programming"]
#[inline(always)]
pub fn flash_cr_fastpg(&mut self) -> FlashCrFastpgW<FlashCrSpec> {
FlashCrFastpgW::new(self, 15)
}
#[doc = "Bit 16 - Flash DMA programming"]
#[inline(always)]
pub fn flash_cr_dma(&mut self) -> FlashCrDmaW<FlashCrSpec> {
FlashCrDmaW::new(self, 16)
}
#[doc = "Bit 17 - Flash standby, which disables fast read"]
#[inline(always)]
pub fn flash_cr_stdby(&mut self) -> FlashCrStdbyW<FlashCrSpec> {
FlashCrStdbyW::new(self, 17)
}
#[doc = "Bit 18 - Flash no power down"]
#[inline(always)]
pub fn flash_cr_no_pd(&mut self) -> FlashCrNoPdW<FlashCrSpec> {
FlashCrNoPdW::new(self, 18)
}
}
#[doc = "Flash control register\n\nYou can [`read`](crate::Reg::read) this register and get [`flash_cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flash_cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FlashCrSpec;
impl crate::RegisterSpec for FlashCrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`flash_cr::R`](R) reader structure"]
impl crate::Readable for FlashCrSpec {}
#[doc = "`write(|w| ..)` method takes [`flash_cr::W`](W) writer structure"]
impl crate::Writable for FlashCrSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets FLASH_CR to value 0"]
impl crate::Resettable for FlashCrSpec {}
}
#[doc = "FLASH_AR (rw) register accessor: Flash address register\n\nYou can [`read`](crate::Reg::read) this register and get [`flash_ar::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flash_ar::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flash_ar`] module"]
#[doc(alias = "FLASH_AR")]
pub type FlashAr = crate::Reg<flash_ar::FlashArSpec>;
#[doc = "Flash address register"]
pub mod flash_ar {
#[doc = "Register `FLASH_AR` reader"]
pub type R = crate::R<FlashArSpec>;
#[doc = "Register `FLASH_AR` writer"]
pub type W = crate::W<FlashArSpec>;
#[doc = "Field `FLASH_AR` reader - Flash address register"]
pub type FlashArR = crate::FieldReader<u32>;
#[doc = "Field `FLASH_AR` writer - Flash address register"]
pub type FlashArW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - Flash address register"]
#[inline(always)]
pub fn flash_ar(&self) -> FlashArR {
FlashArR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - Flash address register"]
#[inline(always)]
pub fn flash_ar(&mut self) -> FlashArW<FlashArSpec> {
FlashArW::new(self, 0)
}
}
#[doc = "Flash address register\n\nYou can [`read`](crate::Reg::read) this register and get [`flash_ar::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flash_ar::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FlashArSpec;
impl crate::RegisterSpec for FlashArSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`flash_ar::R`](R) reader structure"]
impl crate::Readable for FlashArSpec {}
#[doc = "`write(|w| ..)` method takes [`flash_ar::W`](W) writer structure"]
impl crate::Writable for FlashArSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets FLASH_AR to value 0"]
impl crate::Resettable for FlashArSpec {}
}
#[doc = "FLASH_OBR (r) register accessor: Option byte register\n\nYou can [`read`](crate::Reg::read) this register and get [`flash_obr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flash_obr`] module"]
#[doc(alias = "FLASH_OBR")]
pub type FlashObr = crate::Reg<flash_obr::FlashObrSpec>;
#[doc = "Option byte register"]
pub mod flash_obr {
#[doc = "Register `FLASH_OBR` reader"]
pub type R = crate::R<FlashObrSpec>;
#[doc = "Field `OPTERR` reader - Option byte load error"]
pub type OpterrR = crate::BitReader;
#[doc = "Field `RDPRT` reader - Read protection"]
pub type RdprtR = crate::BitReader;
#[doc = "Field `nRST_STOP` reader - Generate reset when entering stop mode"]
pub type NRstStopR = crate::BitReader;
#[doc = "Field `nRST_STDBY` reader - Generate reset when entering standby mode"]
pub type NRstStdbyR = crate::BitReader;
#[doc = "Field `Data0` reader - Data0"]
pub type Data0R = crate::FieldReader;
#[doc = "Field `Data1` reader - Data1"]
pub type Data1R = crate::FieldReader;
impl R {
#[doc = "Bit 0 - Option byte load error"]
#[inline(always)]
pub fn opterr(&self) -> OpterrR {
OpterrR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Read protection"]
#[inline(always)]
pub fn rdprt(&self) -> RdprtR {
RdprtR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 3 - Generate reset when entering stop mode"]
#[inline(always)]
pub fn n_rst_stop(&self) -> NRstStopR {
NRstStopR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Generate reset when entering standby mode"]
#[inline(always)]
pub fn n_rst_stdby(&self) -> NRstStdbyR {
NRstStdbyR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bits 10:17 - Data0"]
#[inline(always)]
pub fn data0(&self) -> Data0R {
Data0R::new(((self.bits >> 10) & 0xff) as u8)
}
#[doc = "Bits 18:25 - Data1"]
#[inline(always)]
pub fn data1(&self) -> Data1R {
Data1R::new(((self.bits >> 18) & 0xff) as u8)
}
}
#[doc = "Option byte register\n\nYou can [`read`](crate::Reg::read) this register and get [`flash_obr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FlashObrSpec;
impl crate::RegisterSpec for FlashObrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`flash_obr::R`](R) reader structure"]
impl crate::Readable for FlashObrSpec {}
#[doc = "`reset()` method sets FLASH_OBR to value 0"]
impl crate::Resettable for FlashObrSpec {}
}
#[doc = "FLASH_WRPR (r) register accessor: Write protection register\n\nYou can [`read`](crate::Reg::read) this register and get [`flash_wrpr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flash_wrpr`] module"]
#[doc(alias = "FLASH_WRPR")]
pub type FlashWrpr = crate::Reg<flash_wrpr::FlashWrprSpec>;
#[doc = "Write protection register"]
pub mod flash_wrpr {
#[doc = "Register `FLASH_WRPR` reader"]
pub type R = crate::R<FlashWrprSpec>;
#[doc = "Field `FLASH_WRPR` reader - Write protection register"]
pub type FlashWrprR = crate::FieldReader<u32>;
impl R {
#[doc = "Bits 0:31 - Write protection register"]
#[inline(always)]
pub fn flash_wrpr(&self) -> FlashWrprR {
FlashWrprR::new(self.bits)
}
}
#[doc = "Write protection register\n\nYou can [`read`](crate::Reg::read) this register and get [`flash_wrpr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FlashWrprSpec;
impl crate::RegisterSpec for FlashWrprSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`flash_wrpr::R`](R) reader structure"]
impl crate::Readable for FlashWrprSpec {}
#[doc = "`reset()` method sets FLASH_WRPR to value 0"]
impl crate::Resettable for FlashWrprSpec {}
}
#[doc = "FLASH_CONFIG (r) register accessor: Flash configuratioin\n\nYou can [`read`](crate::Reg::read) this register and get [`flash_config::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flash_config`] module"]
#[doc(alias = "FLASH_CONFIG")]
pub type FlashConfig = crate::Reg<flash_config::FlashConfigSpec>;
#[doc = "Flash configuratioin"]
pub mod flash_config {
#[doc = "Register `FLASH_CONFIG` reader"]
pub type R = crate::R<FlashConfigSpec>;
#[doc = "Field `FLASH_CONFIG` reader - Flash configuratioin"]
pub type FlashConfigR = crate::FieldReader<u32>;
impl R {
#[doc = "Bits 0:31 - Flash configuratioin"]
#[inline(always)]
pub fn flash_config(&self) -> FlashConfigR {
FlashConfigR::new(self.bits)
}
}
#[doc = "Flash configuratioin\n\nYou can [`read`](crate::Reg::read) this register and get [`flash_config::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FlashConfigSpec;
impl crate::RegisterSpec for FlashConfigSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`flash_config::R`](R) reader structure"]
impl crate::Readable for FlashConfigSpec {}
#[doc = "`reset()` method sets FLASH_CONFIG to value 0"]
impl crate::Resettable for FlashConfigSpec {}
}
#[doc = "FLASH_DMA_DATA (w) register accessor: Flash dma data\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flash_dma_data::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flash_dma_data`] module"]
#[doc(alias = "FLASH_DMA_DATA")]
pub type FlashDmaData = crate::Reg<flash_dma_data::FlashDmaDataSpec>;
#[doc = "Flash dma data"]
pub mod flash_dma_data {
#[doc = "Register `FLASH_DMA_DATA` writer"]
pub type W = crate::W<FlashDmaDataSpec>;
#[doc = "Field `FLASH_DMA_DATA` writer - Flash dma data"]
pub type FlashDmaDataW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl W {
#[doc = "Bits 0:31 - Flash dma data"]
#[inline(always)]
pub fn flash_dma_data(&mut self) -> FlashDmaDataW<FlashDmaDataSpec> {
FlashDmaDataW::new(self, 0)
}
}
#[doc = "Flash dma data\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flash_dma_data::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FlashDmaDataSpec;
impl crate::RegisterSpec for FlashDmaDataSpec {
type Ux = u32;
}
#[doc = "`write(|w| ..)` method takes [`flash_dma_data::W`](W) writer structure"]
impl crate::Writable for FlashDmaDataSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets FLASH_DMA_DATA to value 0"]
impl crate::Resettable for FlashDmaDataSpec {}
}
#[doc = "FLASH_READ_CTRL (rw) register accessor: Flash read ctrl\n\nYou can [`read`](crate::Reg::read) this register and get [`flash_read_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flash_read_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flash_read_ctrl`] module"]
#[doc(alias = "FLASH_READ_CTRL")]
pub type FlashReadCtrl = crate::Reg<flash_read_ctrl::FlashReadCtrlSpec>;
#[doc = "Flash read ctrl"]
pub mod flash_read_ctrl {
#[doc = "Register `FLASH_READ_CTRL` reader"]
pub type R = crate::R<FlashReadCtrlSpec>;
#[doc = "Register `FLASH_READ_CTRL` writer"]
pub type W = crate::W<FlashReadCtrlSpec>;
#[doc = "Field `FLASH_READ_CTRL` reader - Flash read ctrl"]
pub type FlashReadCtrlR = crate::FieldReader<u32>;
#[doc = "Field `FLASH_READ_CTRL` writer - Flash read ctrl"]
pub type FlashReadCtrlW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - Flash read ctrl"]
#[inline(always)]
pub fn flash_read_ctrl(&self) -> FlashReadCtrlR {
FlashReadCtrlR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - Flash read ctrl"]
#[inline(always)]
pub fn flash_read_ctrl(&mut self) -> FlashReadCtrlW<FlashReadCtrlSpec> {
FlashReadCtrlW::new(self, 0)
}
}
#[doc = "Flash read ctrl\n\nYou can [`read`](crate::Reg::read) this register and get [`flash_read_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flash_read_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FlashReadCtrlSpec;
impl crate::RegisterSpec for FlashReadCtrlSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`flash_read_ctrl::R`](R) reader structure"]
impl crate::Readable for FlashReadCtrlSpec {}
#[doc = "`write(|w| ..)` method takes [`flash_read_ctrl::W`](W) writer structure"]
impl crate::Writable for FlashReadCtrlSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets FLASH_READ_CTRL to value 0"]
impl crate::Resettable for FlashReadCtrlSpec {}
}
#[doc = "FLASH_READ_DATA (r) register accessor: Flash read data\n\nYou can [`read`](crate::Reg::read) this register and get [`flash_read_data::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flash_read_data`] module"]
#[doc(alias = "FLASH_READ_DATA")]
pub type FlashReadData = crate::Reg<flash_read_data::FlashReadDataSpec>;
#[doc = "Flash read data"]
pub mod flash_read_data {
#[doc = "Register `FLASH_READ_DATA` reader"]
pub type R = crate::R<FlashReadDataSpec>;
#[doc = "Field `FLASH_READ_DATA` reader - Flash read data"]
pub type FlashReadDataR = crate::FieldReader<u32>;
impl R {
#[doc = "Bits 0:31 - Flash read data"]
#[inline(always)]
pub fn flash_read_data(&self) -> FlashReadDataR {
FlashReadDataR::new(self.bits)
}
}
#[doc = "Flash read data\n\nYou can [`read`](crate::Reg::read) this register and get [`flash_read_data::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FlashReadDataSpec;
impl crate::RegisterSpec for FlashReadDataSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`flash_read_data::R`](R) reader structure"]
impl crate::Readable for FlashReadDataSpec {}
#[doc = "`reset()` method sets FLASH_READ_DATA to value 0"]
impl crate::Resettable for FlashReadDataSpec {}
}
}
#[doc = "FCB registers"]
pub type Fcb0 = crate::Periph<fcb0::RegisterBlock, 0x4001_0000>;
impl core::fmt::Debug for Fcb0 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Fcb0").finish()
}
}
#[doc = "FCB registers"]
pub mod fcb0 {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
ctrl: Ctrl,
addr: Addr,
data: Data,
auto: Auto,
stat: Stat,
int: Int,
}
impl RegisterBlock {
#[doc = "0x00 - Control register"]
#[inline(always)]
pub const fn ctrl(&self) -> &Ctrl {
&self.ctrl
}
#[doc = "0x04 - Address register"]
#[inline(always)]
pub const fn addr(&self) -> &Addr {
&self.addr
}
#[doc = "0x08 - Data register"]
#[inline(always)]
pub const fn data(&self) -> &Data {
&self.data
}
#[doc = "0x0c - Auto configuration register"]
#[inline(always)]
pub const fn auto(&self) -> &Auto {
&self.auto
}
#[doc = "0x10 - Status register"]
#[inline(always)]
pub const fn stat(&self) -> &Stat {
&self.stat
}
#[doc = "0x14 - Interrupt register"]
#[inline(always)]
pub const fn int(&self) -> &Int {
&self.int
}
}
#[doc = "CTRL (rw) register accessor: Control register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`] module"]
#[doc(alias = "CTRL")]
pub type Ctrl = crate::Reg<ctrl::CtrlSpec>;
#[doc = "Control register"]
pub mod ctrl {
#[doc = "Register `CTRL` reader"]
pub type R = crate::R<CtrlSpec>;
#[doc = "Register `CTRL` writer"]
pub type W = crate::W<CtrlSpec>;
#[doc = "Field `INIT` reader - Initialize sram"]
pub type InitR = crate::BitReader;
#[doc = "Field `INIT` writer - Initialize sram"]
pub type InitW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `WRITE` reader - Write operation"]
pub type WriteR = crate::BitReader;
#[doc = "Field `WRITE` writer - Write operation"]
pub type WriteW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `READ` reader - Read operation"]
pub type ReadR = crate::BitReader;
#[doc = "Field `READ` writer - Read operation"]
pub type ReadW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UPDATE` reader - Update current chain"]
pub type UpdateR = crate::BitReader;
#[doc = "Field `UPDATE` writer - Update current chain"]
pub type UpdateW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ACTIVATE` reader - Activate the FPGA configuration"]
pub type ActivateR = crate::BitReader;
#[doc = "Field `ACTIVATE` writer - Activate the FPGA configuration"]
pub type ActivateW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DEACTIVATE` reader - De-activate the FPGA configuration"]
pub type DeactivateR = crate::BitReader;
#[doc = "Field `DEACTIVATE` writer - De-activate the FPGA configuration"]
pub type DeactivateW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `AUTO` reader - Reset auto configuration mode"]
pub type AutoR = crate::BitReader;
#[doc = "Field `AUTO` writer - Reset auto configuration mode"]
pub type AutoW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DMA` reader - Use FCB is tshe dma flow controller"]
pub type DmaR = crate::BitReader;
#[doc = "Field `DMA` writer - Use FCB is tshe dma flow controller"]
pub type DmaW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `INIT_EMB` reader - INIT_EMB"]
pub type InitEmbR = crate::BitReader;
#[doc = "Field `INIT_EMB` writer - INIT_EMB"]
pub type InitEmbW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CFGDONE` reader - CFGDONE"]
pub type CfgdoneR = crate::BitReader;
#[doc = "Field `CFGDONE` writer - CFGDONE"]
pub type CfgdoneW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CHIP_RSTB` reader - CHIP_RSTB"]
pub type ChipRstbR = crate::BitReader;
#[doc = "Field `CHIP_RSTB` writer - CHIP_RSTB"]
pub type ChipRstbW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DEVOE` reader - DEVOE"]
pub type DevoeR = crate::BitReader;
#[doc = "Field `DEVOE` writer - DEVOE"]
pub type DevoeW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - Initialize sram"]
#[inline(always)]
pub fn init(&self) -> InitR {
InitR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Write operation"]
#[inline(always)]
pub fn write(&self) -> WriteR {
WriteR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Read operation"]
#[inline(always)]
pub fn read(&self) -> ReadR {
ReadR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Update current chain"]
#[inline(always)]
pub fn update(&self) -> UpdateR {
UpdateR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Activate the FPGA configuration"]
#[inline(always)]
pub fn activate(&self) -> ActivateR {
ActivateR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - De-activate the FPGA configuration"]
#[inline(always)]
pub fn deactivate(&self) -> DeactivateR {
DeactivateR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Reset auto configuration mode"]
#[inline(always)]
pub fn auto(&self) -> AutoR {
AutoR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Use FCB is tshe dma flow controller"]
#[inline(always)]
pub fn dma(&self) -> DmaR {
DmaR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 16 - INIT_EMB"]
#[inline(always)]
pub fn init_emb(&self) -> InitEmbR {
InitEmbR::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 17 - CFGDONE"]
#[inline(always)]
pub fn cfgdone(&self) -> CfgdoneR {
CfgdoneR::new(((self.bits >> 17) & 1) != 0)
}
#[doc = "Bit 18 - CHIP_RSTB"]
#[inline(always)]
pub fn chip_rstb(&self) -> ChipRstbR {
ChipRstbR::new(((self.bits >> 18) & 1) != 0)
}
#[doc = "Bit 19 - DEVOE"]
#[inline(always)]
pub fn devoe(&self) -> DevoeR {
DevoeR::new(((self.bits >> 19) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Initialize sram"]
#[inline(always)]
pub fn init(&mut self) -> InitW<CtrlSpec> {
InitW::new(self, 0)
}
#[doc = "Bit 1 - Write operation"]
#[inline(always)]
pub fn write(&mut self) -> WriteW<CtrlSpec> {
WriteW::new(self, 1)
}
#[doc = "Bit 2 - Read operation"]
#[inline(always)]
pub fn read(&mut self) -> ReadW<CtrlSpec> {
ReadW::new(self, 2)
}
#[doc = "Bit 3 - Update current chain"]
#[inline(always)]
pub fn update(&mut self) -> UpdateW<CtrlSpec> {
UpdateW::new(self, 3)
}
#[doc = "Bit 4 - Activate the FPGA configuration"]
#[inline(always)]
pub fn activate(&mut self) -> ActivateW<CtrlSpec> {
ActivateW::new(self, 4)
}
#[doc = "Bit 5 - De-activate the FPGA configuration"]
#[inline(always)]
pub fn deactivate(&mut self) -> DeactivateW<CtrlSpec> {
DeactivateW::new(self, 5)
}
#[doc = "Bit 6 - Reset auto configuration mode"]
#[inline(always)]
pub fn auto(&mut self) -> AutoW<CtrlSpec> {
AutoW::new(self, 6)
}
#[doc = "Bit 7 - Use FCB is tshe dma flow controller"]
#[inline(always)]
pub fn dma(&mut self) -> DmaW<CtrlSpec> {
DmaW::new(self, 7)
}
#[doc = "Bit 16 - INIT_EMB"]
#[inline(always)]
pub fn init_emb(&mut self) -> InitEmbW<CtrlSpec> {
InitEmbW::new(self, 16)
}
#[doc = "Bit 17 - CFGDONE"]
#[inline(always)]
pub fn cfgdone(&mut self) -> CfgdoneW<CtrlSpec> {
CfgdoneW::new(self, 17)
}
#[doc = "Bit 18 - CHIP_RSTB"]
#[inline(always)]
pub fn chip_rstb(&mut self) -> ChipRstbW<CtrlSpec> {
ChipRstbW::new(self, 18)
}
#[doc = "Bit 19 - DEVOE"]
#[inline(always)]
pub fn devoe(&mut self) -> DevoeW<CtrlSpec> {
DevoeW::new(self, 19)
}
}
#[doc = "Control register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CtrlSpec;
impl crate::RegisterSpec for CtrlSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"]
impl crate::Readable for CtrlSpec {}
#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"]
impl crate::Writable for CtrlSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets CTRL to value 0"]
impl crate::Resettable for CtrlSpec {}
}
#[doc = "ADDR (rw) register accessor: Address register\n\nYou can [`read`](crate::Reg::read) this register and get [`addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@addr`] module"]
#[doc(alias = "ADDR")]
pub type Addr = crate::Reg<addr::AddrSpec>;
#[doc = "Address register"]
pub mod addr {
#[doc = "Register `ADDR` reader"]
pub type R = crate::R<AddrSpec>;
#[doc = "Register `ADDR` writer"]
pub type W = crate::W<AddrSpec>;
#[doc = "Field `ADDR` reader - Address register"]
pub type AddrR = crate::FieldReader<u32>;
#[doc = "Field `ADDR` writer - Address register"]
pub type AddrW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - Address register"]
#[inline(always)]
pub fn addr(&self) -> AddrR {
AddrR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - Address register"]
#[inline(always)]
pub fn addr(&mut self) -> AddrW<AddrSpec> {
AddrW::new(self, 0)
}
}
#[doc = "Address register\n\nYou can [`read`](crate::Reg::read) this register and get [`addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AddrSpec;
impl crate::RegisterSpec for AddrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`addr::R`](R) reader structure"]
impl crate::Readable for AddrSpec {}
#[doc = "`write(|w| ..)` method takes [`addr::W`](W) writer structure"]
impl crate::Writable for AddrSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ADDR to value 0"]
impl crate::Resettable for AddrSpec {}
}
#[doc = "DATA (rw) register accessor: Data register\n\nYou can [`read`](crate::Reg::read) this register and get [`data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data`] module"]
#[doc(alias = "DATA")]
pub type Data = crate::Reg<data::DataSpec>;
#[doc = "Data register"]
pub mod data {
#[doc = "Register `DATA` reader"]
pub type R = crate::R<DataSpec>;
#[doc = "Register `DATA` writer"]
pub type W = crate::W<DataSpec>;
#[doc = "Field `DATA` reader - Data register"]
pub type DataR = crate::FieldReader<u32>;
#[doc = "Field `DATA` writer - Data register"]
pub type DataW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - Data register"]
#[inline(always)]
pub fn data(&self) -> DataR {
DataR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - Data register"]
#[inline(always)]
pub fn data(&mut self) -> DataW<DataSpec> {
DataW::new(self, 0)
}
}
#[doc = "Data register\n\nYou can [`read`](crate::Reg::read) this register and get [`data::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DataSpec;
impl crate::RegisterSpec for DataSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`data::R`](R) reader structure"]
impl crate::Readable for DataSpec {}
#[doc = "`write(|w| ..)` method takes [`data::W`](W) writer structure"]
impl crate::Writable for DataSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets DATA to value 0"]
impl crate::Resettable for DataSpec {}
}
#[doc = "AUTO (rw) register accessor: Auto configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`auto::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`auto::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@auto`] module"]
#[doc(alias = "AUTO")]
pub type Auto = crate::Reg<auto::AutoSpec>;
#[doc = "Auto configuration register"]
pub mod auto {
#[doc = "Register `AUTO` reader"]
pub type R = crate::R<AutoSpec>;
#[doc = "Register `AUTO` writer"]
pub type W = crate::W<AutoSpec>;
#[doc = "Field `AUTO` reader - Auto configuration register"]
pub type AutoR = crate::FieldReader<u32>;
#[doc = "Field `AUTO` writer - Auto configuration register"]
pub type AutoW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - Auto configuration register"]
#[inline(always)]
pub fn auto(&self) -> AutoR {
AutoR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - Auto configuration register"]
#[inline(always)]
pub fn auto(&mut self) -> AutoW<AutoSpec> {
AutoW::new(self, 0)
}
}
#[doc = "Auto configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`auto::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`auto::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AutoSpec;
impl crate::RegisterSpec for AutoSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`auto::R`](R) reader structure"]
impl crate::Readable for AutoSpec {}
#[doc = "`write(|w| ..)` method takes [`auto::W`](W) writer structure"]
impl crate::Writable for AutoSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets AUTO to value 0"]
impl crate::Resettable for AutoSpec {}
}
#[doc = "STAT (r) register accessor: Status register\n\nYou can [`read`](crate::Reg::read) this register and get [`stat::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stat`] module"]
#[doc(alias = "STAT")]
pub type Stat = crate::Reg<stat::StatSpec>;
#[doc = "Status register"]
pub mod stat {
#[doc = "Register `STAT` reader"]
pub type R = crate::R<StatSpec>;
#[doc = "Field `INIT` reader - Sram initialization"]
pub type InitR = crate::BitReader;
#[doc = "Field `ACTIVE` reader - FPGA active"]
pub type ActiveR = crate::BitReader;
#[doc = "Field `ERR_ID` reader - ID error"]
pub type ErrIdR = crate::BitReader;
#[doc = "Field `ERR_HEADER` reader - Header error"]
pub type ErrHeaderR = crate::BitReader;
#[doc = "Field `ERR_CRC` reader - CRC error"]
pub type ErrCrcR = crate::BitReader;
#[doc = "Field `INIT_EMB` reader - INIT_EMB"]
pub type InitEmbR = crate::BitReader;
#[doc = "Field `CFGDONE` reader - CFGDONE"]
pub type CfgdoneR = crate::BitReader;
#[doc = "Field `CHIP_RSTB` reader - CHIP_RSTB"]
pub type ChipRstbR = crate::BitReader;
#[doc = "Field `DEVOE` reader - DEVOE"]
pub type DevoeR = crate::BitReader;
impl R {
#[doc = "Bit 0 - Sram initialization"]
#[inline(always)]
pub fn init(&self) -> InitR {
InitR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - FPGA active"]
#[inline(always)]
pub fn active(&self) -> ActiveR {
ActiveR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 4 - ID error"]
#[inline(always)]
pub fn err_id(&self) -> ErrIdR {
ErrIdR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Header error"]
#[inline(always)]
pub fn err_header(&self) -> ErrHeaderR {
ErrHeaderR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - CRC error"]
#[inline(always)]
pub fn err_crc(&self) -> ErrCrcR {
ErrCrcR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 16 - INIT_EMB"]
#[inline(always)]
pub fn init_emb(&self) -> InitEmbR {
InitEmbR::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 17 - CFGDONE"]
#[inline(always)]
pub fn cfgdone(&self) -> CfgdoneR {
CfgdoneR::new(((self.bits >> 17) & 1) != 0)
}
#[doc = "Bit 18 - CHIP_RSTB"]
#[inline(always)]
pub fn chip_rstb(&self) -> ChipRstbR {
ChipRstbR::new(((self.bits >> 18) & 1) != 0)
}
#[doc = "Bit 19 - DEVOE"]
#[inline(always)]
pub fn devoe(&self) -> DevoeR {
DevoeR::new(((self.bits >> 19) & 1) != 0)
}
}
#[doc = "Status register\n\nYou can [`read`](crate::Reg::read) this register and get [`stat::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct StatSpec;
impl crate::RegisterSpec for StatSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`stat::R`](R) reader structure"]
impl crate::Readable for StatSpec {}
#[doc = "`reset()` method sets STAT to value 0"]
impl crate::Resettable for StatSpec {}
}
#[doc = "INT (rw) register accessor: Interrupt register\n\nYou can [`read`](crate::Reg::read) this register and get [`int::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int`] module"]
#[doc(alias = "INT")]
pub type Int = crate::Reg<int::IntSpec>;
#[doc = "Interrupt register"]
pub mod int {
#[doc = "Register `INT` reader"]
pub type R = crate::R<IntSpec>;
#[doc = "Register `INT` writer"]
pub type W = crate::W<IntSpec>;
#[doc = "Field `INIT_EN` reader - Sram initialization interrupt enable"]
pub type InitEnR = crate::BitReader;
#[doc = "Field `INIT_EN` writer - Sram initialization interrupt enable"]
pub type InitEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ACTIVE_EN` reader - FPGA active interrupt enable"]
pub type ActiveEnR = crate::BitReader;
#[doc = "Field `ACTIVE_EN` writer - FPGA active interrupt enable"]
pub type ActiveEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ERR_ID_EN` reader - ID error interrupt enable"]
pub type ErrIdEnR = crate::BitReader;
#[doc = "Field `ERR_ID_EN` writer - ID error interrupt enable"]
pub type ErrIdEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ERR_HEADER_EN` reader - Header error interrupt enable"]
pub type ErrHeaderEnR = crate::BitReader;
#[doc = "Field `ERR_HEADER_EN` writer - Header error interrupt enable"]
pub type ErrHeaderEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ERR_CRC_EN` reader - CRC error interrupt enable"]
pub type ErrCrcEnR = crate::BitReader;
#[doc = "Field `ERR_CRC_EN` writer - CRC error interrupt enable"]
pub type ErrCrcEnW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - Sram initialization interrupt enable"]
#[inline(always)]
pub fn init_en(&self) -> InitEnR {
InitEnR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - FPGA active interrupt enable"]
#[inline(always)]
pub fn active_en(&self) -> ActiveEnR {
ActiveEnR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 4 - ID error interrupt enable"]
#[inline(always)]
pub fn err_id_en(&self) -> ErrIdEnR {
ErrIdEnR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Header error interrupt enable"]
#[inline(always)]
pub fn err_header_en(&self) -> ErrHeaderEnR {
ErrHeaderEnR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - CRC error interrupt enable"]
#[inline(always)]
pub fn err_crc_en(&self) -> ErrCrcEnR {
ErrCrcEnR::new(((self.bits >> 6) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Sram initialization interrupt enable"]
#[inline(always)]
pub fn init_en(&mut self) -> InitEnW<IntSpec> {
InitEnW::new(self, 0)
}
#[doc = "Bit 1 - FPGA active interrupt enable"]
#[inline(always)]
pub fn active_en(&mut self) -> ActiveEnW<IntSpec> {
ActiveEnW::new(self, 1)
}
#[doc = "Bit 4 - ID error interrupt enable"]
#[inline(always)]
pub fn err_id_en(&mut self) -> ErrIdEnW<IntSpec> {
ErrIdEnW::new(self, 4)
}
#[doc = "Bit 5 - Header error interrupt enable"]
#[inline(always)]
pub fn err_header_en(&mut self) -> ErrHeaderEnW<IntSpec> {
ErrHeaderEnW::new(self, 5)
}
#[doc = "Bit 6 - CRC error interrupt enable"]
#[inline(always)]
pub fn err_crc_en(&mut self) -> ErrCrcEnW<IntSpec> {
ErrCrcEnW::new(self, 6)
}
}
#[doc = "Interrupt register\n\nYou can [`read`](crate::Reg::read) this register and get [`int::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntSpec;
impl crate::RegisterSpec for IntSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`int::R`](R) reader structure"]
impl crate::Readable for IntSpec {}
#[doc = "`write(|w| ..)` method takes [`int::W`](W) writer structure"]
impl crate::Writable for IntSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets INT to value 0"]
impl crate::Resettable for IntSpec {}
}
}
#[doc = "WATCHDOG registers"]
pub type Watchdog0 = crate::Periph<watchdog0::RegisterBlock, 0x4001_1000>;
impl core::fmt::Debug for Watchdog0 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Watchdog0").finish()
}
}
#[doc = "WATCHDOG registers"]
pub mod watchdog0 {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
wdog_load: WdogLoad,
wdog_value: WdogValue,
wdog_control: WdogControl,
wdog_int_clr: WdogIntClr,
wdog_ris: WdogRis,
wdog_mis: WdogMis,
_reserved6: [u8; 0x0be8],
wdog_lock: WdogLock,
}
impl RegisterBlock {
#[doc = "0x00 - Load Register"]
#[inline(always)]
pub const fn wdog_load(&self) -> &WdogLoad {
&self.wdog_load
}
#[doc = "0x04 - Value Register"]
#[inline(always)]
pub const fn wdog_value(&self) -> &WdogValue {
&self.wdog_value
}
#[doc = "0x08 - Control register"]
#[inline(always)]
pub const fn wdog_control(&self) -> &WdogControl {
&self.wdog_control
}
#[doc = "0x0c - Interrupt Clear Register"]
#[inline(always)]
pub const fn wdog_int_clr(&self) -> &WdogIntClr {
&self.wdog_int_clr
}
#[doc = "0x10 - Raw Interrupt Status Register"]
#[inline(always)]
pub const fn wdog_ris(&self) -> &WdogRis {
&self.wdog_ris
}
#[doc = "0x14 - Masked Interrupt Status Register"]
#[inline(always)]
pub const fn wdog_mis(&self) -> &WdogMis {
&self.wdog_mis
}
#[doc = "0xc00 - Lock Register"]
#[inline(always)]
pub const fn wdog_lock(&self) -> &WdogLock {
&self.wdog_lock
}
}
#[doc = "WdogLoad (rw) register accessor: Load Register\n\nYou can [`read`](crate::Reg::read) this register and get [`wdog_load::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdog_load::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdog_load`] module"]
pub type WdogLoad = crate::Reg<wdog_load::WdogLoadSpec>;
#[doc = "Load Register"]
pub mod wdog_load {
#[doc = "Register `WdogLoad` reader"]
pub type R = crate::R<WdogLoadSpec>;
#[doc = "Register `WdogLoad` writer"]
pub type W = crate::W<WdogLoadSpec>;
#[doc = "Field `WdogLoad` reader - Load Register"]
pub type WdogLoadR = crate::FieldReader<u32>;
#[doc = "Field `WdogLoad` writer - Load Register"]
pub type WdogLoadW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - Load Register"]
#[inline(always)]
pub fn wdog_load(&self) -> WdogLoadR {
WdogLoadR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - Load Register"]
#[inline(always)]
pub fn wdog_load(&mut self) -> WdogLoadW<WdogLoadSpec> {
WdogLoadW::new(self, 0)
}
}
#[doc = "Load Register\n\nYou can [`read`](crate::Reg::read) this register and get [`wdog_load::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdog_load::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct WdogLoadSpec;
impl crate::RegisterSpec for WdogLoadSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`wdog_load::R`](R) reader structure"]
impl crate::Readable for WdogLoadSpec {}
#[doc = "`write(|w| ..)` method takes [`wdog_load::W`](W) writer structure"]
impl crate::Writable for WdogLoadSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets WdogLoad to value 0"]
impl crate::Resettable for WdogLoadSpec {}
}
#[doc = "WdogValue (r) register accessor: Value Register\n\nYou can [`read`](crate::Reg::read) this register and get [`wdog_value::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdog_value`] module"]
pub type WdogValue = crate::Reg<wdog_value::WdogValueSpec>;
#[doc = "Value Register"]
pub mod wdog_value {
#[doc = "Register `WdogValue` reader"]
pub type R = crate::R<WdogValueSpec>;
#[doc = "Field `WdogValue` reader - Value Register"]
pub type WdogValueR = crate::FieldReader<u32>;
impl R {
#[doc = "Bits 0:31 - Value Register"]
#[inline(always)]
pub fn wdog_value(&self) -> WdogValueR {
WdogValueR::new(self.bits)
}
}
#[doc = "Value Register\n\nYou can [`read`](crate::Reg::read) this register and get [`wdog_value::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct WdogValueSpec;
impl crate::RegisterSpec for WdogValueSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`wdog_value::R`](R) reader structure"]
impl crate::Readable for WdogValueSpec {}
#[doc = "`reset()` method sets WdogValue to value 0"]
impl crate::Resettable for WdogValueSpec {}
}
#[doc = "WdogControl (rw) register accessor: Control register\n\nYou can [`read`](crate::Reg::read) this register and get [`wdog_control::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdog_control::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdog_control`] module"]
pub type WdogControl = crate::Reg<wdog_control::WdogControlSpec>;
#[doc = "Control register"]
pub mod wdog_control {
#[doc = "Register `WdogControl` reader"]
pub type R = crate::R<WdogControlSpec>;
#[doc = "Register `WdogControl` writer"]
pub type W = crate::W<WdogControlSpec>;
#[doc = "Field `INTEN` reader - Interrupt enable"]
pub type IntenR = crate::BitReader;
#[doc = "Field `INTEN` writer - Interrupt enable"]
pub type IntenW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RESEN` reader - Reset enable"]
pub type ResenR = crate::BitReader;
#[doc = "Field `RESEN` writer - Reset enable"]
pub type ResenW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - Interrupt enable"]
#[inline(always)]
pub fn inten(&self) -> IntenR {
IntenR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Reset enable"]
#[inline(always)]
pub fn resen(&self) -> ResenR {
ResenR::new(((self.bits >> 1) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Interrupt enable"]
#[inline(always)]
pub fn inten(&mut self) -> IntenW<WdogControlSpec> {
IntenW::new(self, 0)
}
#[doc = "Bit 1 - Reset enable"]
#[inline(always)]
pub fn resen(&mut self) -> ResenW<WdogControlSpec> {
ResenW::new(self, 1)
}
}
#[doc = "Control register\n\nYou can [`read`](crate::Reg::read) this register and get [`wdog_control::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdog_control::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct WdogControlSpec;
impl crate::RegisterSpec for WdogControlSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`wdog_control::R`](R) reader structure"]
impl crate::Readable for WdogControlSpec {}
#[doc = "`write(|w| ..)` method takes [`wdog_control::W`](W) writer structure"]
impl crate::Writable for WdogControlSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets WdogControl to value 0"]
impl crate::Resettable for WdogControlSpec {}
}
#[doc = "WdogIntClr (w) register accessor: Interrupt Clear Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdog_int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdog_int_clr`] module"]
pub type WdogIntClr = crate::Reg<wdog_int_clr::WdogIntClrSpec>;
#[doc = "Interrupt Clear Register"]
pub mod wdog_int_clr {
#[doc = "Register `WdogIntClr` writer"]
pub type W = crate::W<WdogIntClrSpec>;
#[doc = "Field `WdogIntClr` writer - Interrupt Clear Register"]
pub type WdogIntClrW<'a, REG> = crate::BitWriter<'a, REG>;
impl W {
#[doc = "Bit 0 - Interrupt Clear Register"]
#[inline(always)]
pub fn wdog_int_clr(&mut self) -> WdogIntClrW<WdogIntClrSpec> {
WdogIntClrW::new(self, 0)
}
}
#[doc = "Interrupt Clear Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdog_int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct WdogIntClrSpec;
impl crate::RegisterSpec for WdogIntClrSpec {
type Ux = u32;
}
#[doc = "`write(|w| ..)` method takes [`wdog_int_clr::W`](W) writer structure"]
impl crate::Writable for WdogIntClrSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets WdogIntClr to value 0"]
impl crate::Resettable for WdogIntClrSpec {}
}
#[doc = "WdogRIS (r) register accessor: Raw Interrupt Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`wdog_ris::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdog_ris`] module"]
#[doc(alias = "WdogRIS")]
pub type WdogRis = crate::Reg<wdog_ris::WdogRisSpec>;
#[doc = "Raw Interrupt Status Register"]
pub mod wdog_ris {
#[doc = "Register `WdogRIS` reader"]
pub type R = crate::R<WdogRisSpec>;
#[doc = "Field `WdogRIS` reader - Raw Interrupt Status Register"]
pub type WdogRisR = crate::BitReader;
impl R {
#[doc = "Bit 0 - Raw Interrupt Status Register"]
#[inline(always)]
pub fn wdog_ris(&self) -> WdogRisR {
WdogRisR::new((self.bits & 1) != 0)
}
}
#[doc = "Raw Interrupt Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`wdog_ris::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct WdogRisSpec;
impl crate::RegisterSpec for WdogRisSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`wdog_ris::R`](R) reader structure"]
impl crate::Readable for WdogRisSpec {}
#[doc = "`reset()` method sets WdogRIS to value 0"]
impl crate::Resettable for WdogRisSpec {}
}
#[doc = "WdogMIS (r) register accessor: Masked Interrupt Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`wdog_mis::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdog_mis`] module"]
#[doc(alias = "WdogMIS")]
pub type WdogMis = crate::Reg<wdog_mis::WdogMisSpec>;
#[doc = "Masked Interrupt Status Register"]
pub mod wdog_mis {
#[doc = "Register `WdogMIS` reader"]
pub type R = crate::R<WdogMisSpec>;
#[doc = "Field `WdogMIS` reader - Masked Interrupt Status Register"]
pub type WdogMisR = crate::BitReader;
impl R {
#[doc = "Bit 0 - Masked Interrupt Status Register"]
#[inline(always)]
pub fn wdog_mis(&self) -> WdogMisR {
WdogMisR::new((self.bits & 1) != 0)
}
}
#[doc = "Masked Interrupt Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`wdog_mis::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct WdogMisSpec;
impl crate::RegisterSpec for WdogMisSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`wdog_mis::R`](R) reader structure"]
impl crate::Readable for WdogMisSpec {}
#[doc = "`reset()` method sets WdogMIS to value 0"]
impl crate::Resettable for WdogMisSpec {}
}
#[doc = "WdogLock (rw) register accessor: Lock Register\n\nYou can [`read`](crate::Reg::read) this register and get [`wdog_lock::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdog_lock::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdog_lock`] module"]
pub type WdogLock = crate::Reg<wdog_lock::WdogLockSpec>;
#[doc = "Lock Register"]
pub mod wdog_lock {
#[doc = "Register `WdogLock` reader"]
pub type R = crate::R<WdogLockSpec>;
#[doc = "Register `WdogLock` writer"]
pub type W = crate::W<WdogLockSpec>;
#[doc = "Field `WdogLock` reader - Lock Register"]
pub type WdogLockR = crate::FieldReader<u32>;
#[doc = "Field `WdogLock` writer - Lock Register"]
pub type WdogLockW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - Lock Register"]
#[inline(always)]
pub fn wdog_lock(&self) -> WdogLockR {
WdogLockR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - Lock Register"]
#[inline(always)]
pub fn wdog_lock(&mut self) -> WdogLockW<WdogLockSpec> {
WdogLockW::new(self, 0)
}
}
#[doc = "Lock Register\n\nYou can [`read`](crate::Reg::read) this register and get [`wdog_lock::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdog_lock::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct WdogLockSpec;
impl crate::RegisterSpec for WdogLockSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`wdog_lock::R`](R) reader structure"]
impl crate::Readable for WdogLockSpec {}
#[doc = "`write(|w| ..)` method takes [`wdog_lock::W`](W) writer structure"]
impl crate::Writable for WdogLockSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets WdogLock to value 0"]
impl crate::Resettable for WdogLockSpec {}
}
}
#[doc = "SPI registers"]
pub type Spi0 = crate::Periph<spi0::RegisterBlock, 0x4001_2000>;
impl core::fmt::Debug for Spi0 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Spi0").finish()
}
}
#[doc = "SPI registers"]
pub mod spi0 {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
ctrl: Ctrl,
_reserved1: [u8; 0x0c],
phase_ctrl0: PhaseCtrl0,
phase_ctrl1: PhaseCtrl1,
phase_ctrl2: PhaseCtrl2,
phase_ctrl3: PhaseCtrl3,
phase_ctrl4: PhaseCtrl4,
phase_ctrl5: PhaseCtrl5,
phase_ctrl6: PhaseCtrl6,
phase_ctrl7: PhaseCtrl7,
phase_data0: PhaseData0,
phase_data1: PhaseData1,
phase_data2: PhaseData2,
phase_data3: PhaseData3,
phase_data4: PhaseData4,
phase_data5: PhaseData5,
phase_data6: PhaseData6,
phase_data7: PhaseData7,
}
impl RegisterBlock {
#[doc = "0x00 - Control register"]
#[inline(always)]
pub const fn ctrl(&self) -> &Ctrl {
&self.ctrl
}
#[doc = "0x10 - Phase control 0"]
#[inline(always)]
pub const fn phase_ctrl0(&self) -> &PhaseCtrl0 {
&self.phase_ctrl0
}
#[doc = "0x14 - Phase control 1"]
#[inline(always)]
pub const fn phase_ctrl1(&self) -> &PhaseCtrl1 {
&self.phase_ctrl1
}
#[doc = "0x18 - Phase control 2"]
#[inline(always)]
pub const fn phase_ctrl2(&self) -> &PhaseCtrl2 {
&self.phase_ctrl2
}
#[doc = "0x1c - Phase control 3"]
#[inline(always)]
pub const fn phase_ctrl3(&self) -> &PhaseCtrl3 {
&self.phase_ctrl3
}
#[doc = "0x20 - Phase control 4"]
#[inline(always)]
pub const fn phase_ctrl4(&self) -> &PhaseCtrl4 {
&self.phase_ctrl4
}
#[doc = "0x24 - Phase control 5"]
#[inline(always)]
pub const fn phase_ctrl5(&self) -> &PhaseCtrl5 {
&self.phase_ctrl5
}
#[doc = "0x28 - Phase control 6"]
#[inline(always)]
pub const fn phase_ctrl6(&self) -> &PhaseCtrl6 {
&self.phase_ctrl6
}
#[doc = "0x2c - Phase control 7"]
#[inline(always)]
pub const fn phase_ctrl7(&self) -> &PhaseCtrl7 {
&self.phase_ctrl7
}
#[doc = "0x30 - Phase data 0"]
#[inline(always)]
pub const fn phase_data0(&self) -> &PhaseData0 {
&self.phase_data0
}
#[doc = "0x34 - Phase data 1"]
#[inline(always)]
pub const fn phase_data1(&self) -> &PhaseData1 {
&self.phase_data1
}
#[doc = "0x38 - Phase data 2"]
#[inline(always)]
pub const fn phase_data2(&self) -> &PhaseData2 {
&self.phase_data2
}
#[doc = "0x3c - Phase data 3"]
#[inline(always)]
pub const fn phase_data3(&self) -> &PhaseData3 {
&self.phase_data3
}
#[doc = "0x40 - Phase data 4"]
#[inline(always)]
pub const fn phase_data4(&self) -> &PhaseData4 {
&self.phase_data4
}
#[doc = "0x44 - Phase data 5"]
#[inline(always)]
pub const fn phase_data5(&self) -> &PhaseData5 {
&self.phase_data5
}
#[doc = "0x48 - Phase data 6"]
#[inline(always)]
pub const fn phase_data6(&self) -> &PhaseData6 {
&self.phase_data6
}
#[doc = "0x4c - Phase data 7"]
#[inline(always)]
pub const fn phase_data7(&self) -> &PhaseData7 {
&self.phase_data7
}
}
#[doc = "CTRL (rw) register accessor: Control register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`] module"]
#[doc(alias = "CTRL")]
pub type Ctrl = crate::Reg<ctrl::CtrlSpec>;
#[doc = "Control register"]
pub mod ctrl {
#[doc = "Register `CTRL` reader"]
pub type R = crate::R<CtrlSpec>;
#[doc = "Register `CTRL` writer"]
pub type W = crate::W<CtrlSpec>;
#[doc = "Field `SPI_START` reader - SPI start operation"]
pub type SpiStartR = crate::BitReader;
#[doc = "Field `SPI_START` writer - SPI start operation"]
pub type SpiStartW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SPI_DONE` reader - SPI operation done"]
pub type SpiDoneR = crate::BitReader;
#[doc = "Field `SPI_DONE` writer - SPI operation done"]
pub type SpiDoneW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SPI_ERROR` reader - SPI operation error"]
pub type SpiErrorR = crate::BitReader;
#[doc = "Field `SPI_ERROR` writer - SPI operation error"]
pub type SpiErrorW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `INT_CLR` reader - Interrupt clear"]
pub type IntClrR = crate::BitReader;
#[doc = "Field `INT_CLR` writer - Interrupt clear"]
pub type IntClrW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PHASE_CNT` reader - Phase count"]
pub type PhaseCntR = crate::FieldReader;
#[doc = "Field `PHASE_CNT` writer - Phase count"]
pub type PhaseCntW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `DMA_EN` reader - DMA enable for last phase"]
pub type DmaEnR = crate::BitReader;
#[doc = "Field `DMA_EN` writer - DMA enable for last phase"]
pub type DmaEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `WP_EN` reader - WP enable"]
pub type WpEnR = crate::BitReader;
#[doc = "Field `WP_EN` writer - WP enable"]
pub type WpEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Endian select\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Endian {
#[doc = "0: BE"]
Be = 0,
#[doc = "1: LE"]
Le = 1,
}
impl From<Endian> for bool {
#[inline(always)]
fn from(variant: Endian) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `ENDIAN` reader - Endian select"]
pub type EndianR = crate::BitReader<Endian>;
impl EndianR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Endian {
match self.bits {
false => Endian::Be,
true => Endian::Le,
}
}
#[doc = "BE"]
#[inline(always)]
pub fn is_be(&self) -> bool {
*self == Endian::Be
}
#[doc = "LE"]
#[inline(always)]
pub fn is_le(&self) -> bool {
*self == Endian::Le
}
}
#[doc = "Field `ENDIAN` writer - Endian select"]
pub type EndianW<'a, REG> = crate::BitWriter<'a, REG, Endian>;
impl<'a, REG> EndianW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "BE"]
#[inline(always)]
pub fn be(self) -> &'a mut crate::W<REG> {
self.variant(Endian::Be)
}
#[doc = "LE"]
#[inline(always)]
pub fn le(self) -> &'a mut crate::W<REG> {
self.variant(Endian::Le)
}
}
#[doc = "Sclk divider\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum SclkDiv {
#[doc = "2: Div 2"]
Div2 = 2,
#[doc = "4: Div 4"]
Div4 = 4,
#[doc = "8: Div 8"]
Div8 = 8,
#[doc = "16: Div 16"]
Div16 = 16,
#[doc = "32: Div 32"]
Div32 = 32,
#[doc = "64: Div 64"]
Div64 = 64,
#[doc = "128: Div 128"]
Div128 = 128,
#[doc = "0: Div 256"]
Div256 = 0,
}
impl From<SclkDiv> for u8 {
#[inline(always)]
fn from(variant: SclkDiv) -> Self {
variant as _
}
}
impl crate::FieldSpec for SclkDiv {
type Ux = u8;
}
impl crate::IsEnum for SclkDiv {}
#[doc = "Field `SCLK_DIV` reader - Sclk divider"]
pub type SclkDivR = crate::FieldReader<SclkDiv>;
impl SclkDivR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<SclkDiv> {
match self.bits {
2 => Some(SclkDiv::Div2),
4 => Some(SclkDiv::Div4),
8 => Some(SclkDiv::Div8),
16 => Some(SclkDiv::Div16),
32 => Some(SclkDiv::Div32),
64 => Some(SclkDiv::Div64),
128 => Some(SclkDiv::Div128),
0 => Some(SclkDiv::Div256),
_ => None,
}
}
#[doc = "Div 2"]
#[inline(always)]
pub fn is_div2(&self) -> bool {
*self == SclkDiv::Div2
}
#[doc = "Div 4"]
#[inline(always)]
pub fn is_div4(&self) -> bool {
*self == SclkDiv::Div4
}
#[doc = "Div 8"]
#[inline(always)]
pub fn is_div8(&self) -> bool {
*self == SclkDiv::Div8
}
#[doc = "Div 16"]
#[inline(always)]
pub fn is_div16(&self) -> bool {
*self == SclkDiv::Div16
}
#[doc = "Div 32"]
#[inline(always)]
pub fn is_div32(&self) -> bool {
*self == SclkDiv::Div32
}
#[doc = "Div 64"]
#[inline(always)]
pub fn is_div64(&self) -> bool {
*self == SclkDiv::Div64
}
#[doc = "Div 128"]
#[inline(always)]
pub fn is_div128(&self) -> bool {
*self == SclkDiv::Div128
}
#[doc = "Div 256"]
#[inline(always)]
pub fn is_div256(&self) -> bool {
*self == SclkDiv::Div256
}
}
#[doc = "Field `SCLK_DIV` writer - Sclk divider"]
pub type SclkDivW<'a, REG> = crate::FieldWriter<'a, REG, 8, SclkDiv>;
impl<'a, REG> SclkDivW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Div 2"]
#[inline(always)]
pub fn div2(self) -> &'a mut crate::W<REG> {
self.variant(SclkDiv::Div2)
}
#[doc = "Div 4"]
#[inline(always)]
pub fn div4(self) -> &'a mut crate::W<REG> {
self.variant(SclkDiv::Div4)
}
#[doc = "Div 8"]
#[inline(always)]
pub fn div8(self) -> &'a mut crate::W<REG> {
self.variant(SclkDiv::Div8)
}
#[doc = "Div 16"]
#[inline(always)]
pub fn div16(self) -> &'a mut crate::W<REG> {
self.variant(SclkDiv::Div16)
}
#[doc = "Div 32"]
#[inline(always)]
pub fn div32(self) -> &'a mut crate::W<REG> {
self.variant(SclkDiv::Div32)
}
#[doc = "Div 64"]
#[inline(always)]
pub fn div64(self) -> &'a mut crate::W<REG> {
self.variant(SclkDiv::Div64)
}
#[doc = "Div 128"]
#[inline(always)]
pub fn div128(self) -> &'a mut crate::W<REG> {
self.variant(SclkDiv::Div128)
}
#[doc = "Div 256"]
#[inline(always)]
pub fn div256(self) -> &'a mut crate::W<REG> {
self.variant(SclkDiv::Div256)
}
}
#[doc = "Field `INT_EN` reader - Interrupt enable"]
pub type IntEnR = crate::BitReader;
#[doc = "Field `INT_EN` writer - Interrupt enable"]
pub type IntEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SPI_RESET` reader - SPI reset"]
pub type SpiResetR = crate::BitReader;
#[doc = "Field `SPI_RESET` writer - SPI reset"]
pub type SpiResetW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - SPI start operation"]
#[inline(always)]
pub fn spi_start(&self) -> SpiStartR {
SpiStartR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - SPI operation done"]
#[inline(always)]
pub fn spi_done(&self) -> SpiDoneR {
SpiDoneR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - SPI operation error"]
#[inline(always)]
pub fn spi_error(&self) -> SpiErrorR {
SpiErrorR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Interrupt clear"]
#[inline(always)]
pub fn int_clr(&self) -> IntClrR {
IntClrR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bits 4:6 - Phase count"]
#[inline(always)]
pub fn phase_cnt(&self) -> PhaseCntR {
PhaseCntR::new(((self.bits >> 4) & 7) as u8)
}
#[doc = "Bit 8 - DMA enable for last phase"]
#[inline(always)]
pub fn dma_en(&self) -> DmaEnR {
DmaEnR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - WP enable"]
#[inline(always)]
pub fn wp_en(&self) -> WpEnR {
WpEnR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - Endian select"]
#[inline(always)]
pub fn endian(&self) -> EndianR {
EndianR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bits 12:19 - Sclk divider"]
#[inline(always)]
pub fn sclk_div(&self) -> SclkDivR {
SclkDivR::new(((self.bits >> 12) & 0xff) as u8)
}
#[doc = "Bit 20 - Interrupt enable"]
#[inline(always)]
pub fn int_en(&self) -> IntEnR {
IntEnR::new(((self.bits >> 20) & 1) != 0)
}
#[doc = "Bit 31 - SPI reset"]
#[inline(always)]
pub fn spi_reset(&self) -> SpiResetR {
SpiResetR::new(((self.bits >> 31) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - SPI start operation"]
#[inline(always)]
pub fn spi_start(&mut self) -> SpiStartW<CtrlSpec> {
SpiStartW::new(self, 0)
}
#[doc = "Bit 1 - SPI operation done"]
#[inline(always)]
pub fn spi_done(&mut self) -> SpiDoneW<CtrlSpec> {
SpiDoneW::new(self, 1)
}
#[doc = "Bit 2 - SPI operation error"]
#[inline(always)]
pub fn spi_error(&mut self) -> SpiErrorW<CtrlSpec> {
SpiErrorW::new(self, 2)
}
#[doc = "Bit 3 - Interrupt clear"]
#[inline(always)]
pub fn int_clr(&mut self) -> IntClrW<CtrlSpec> {
IntClrW::new(self, 3)
}
#[doc = "Bits 4:6 - Phase count"]
#[inline(always)]
pub fn phase_cnt(&mut self) -> PhaseCntW<CtrlSpec> {
PhaseCntW::new(self, 4)
}
#[doc = "Bit 8 - DMA enable for last phase"]
#[inline(always)]
pub fn dma_en(&mut self) -> DmaEnW<CtrlSpec> {
DmaEnW::new(self, 8)
}
#[doc = "Bit 9 - WP enable"]
#[inline(always)]
pub fn wp_en(&mut self) -> WpEnW<CtrlSpec> {
WpEnW::new(self, 9)
}
#[doc = "Bit 10 - Endian select"]
#[inline(always)]
pub fn endian(&mut self) -> EndianW<CtrlSpec> {
EndianW::new(self, 10)
}
#[doc = "Bits 12:19 - Sclk divider"]
#[inline(always)]
pub fn sclk_div(&mut self) -> SclkDivW<CtrlSpec> {
SclkDivW::new(self, 12)
}
#[doc = "Bit 20 - Interrupt enable"]
#[inline(always)]
pub fn int_en(&mut self) -> IntEnW<CtrlSpec> {
IntEnW::new(self, 20)
}
#[doc = "Bit 31 - SPI reset"]
#[inline(always)]
pub fn spi_reset(&mut self) -> SpiResetW<CtrlSpec> {
SpiResetW::new(self, 31)
}
}
#[doc = "Control register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CtrlSpec;
impl crate::RegisterSpec for CtrlSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"]
impl crate::Readable for CtrlSpec {}
#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"]
impl crate::Writable for CtrlSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets CTRL to value 0"]
impl crate::Resettable for CtrlSpec {}
}
#[doc = "PHASE_CTRL[0] (rw) register accessor: Phase control 0\n\nYou can [`read`](crate::Reg::read) this register and get [`phase_ctrl0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`phase_ctrl0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@phase_ctrl0`] module"]
#[doc(alias = "PHASE_CTRL[0]")]
pub type PhaseCtrl0 = crate::Reg<phase_ctrl0::PhaseCtrl0Spec>;
#[doc = "Phase control 0"]
pub mod phase_ctrl0 {
#[doc = "Register `PHASE_CTRL[0]` reader"]
pub type R = crate::R<PhaseCtrl0Spec>;
#[doc = "Register `PHASE_CTRL[0]` writer"]
pub type W = crate::W<PhaseCtrl0Spec>;
#[doc = "Field `PHASE_START` reader - Phase start"]
pub type PhaseStartR = crate::BitReader;
#[doc = "Field `PHASE_DONE` reader - Phase done"]
pub type PhaseDoneR = crate::BitReader;
#[doc = "Field `PHASE_ERROR` reader - Phase error"]
pub type PhaseErrorR = crate::BitReader;
#[doc = "Phase action\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum PhaseAction {
#[doc = "0: TX"]
Tx = 0,
#[doc = "1: Dummy TX"]
DummyTx = 1,
#[doc = "2: RX"]
Rx = 2,
#[doc = "3: Poll"]
Poll = 3,
}
impl From<PhaseAction> for u8 {
#[inline(always)]
fn from(variant: PhaseAction) -> Self {
variant as _
}
}
impl crate::FieldSpec for PhaseAction {
type Ux = u8;
}
impl crate::IsEnum for PhaseAction {}
#[doc = "Field `PHASE_ACTION` reader - Phase action"]
pub type PhaseActionR = crate::FieldReader<PhaseAction>;
impl PhaseActionR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> PhaseAction {
match self.bits {
0 => PhaseAction::Tx,
1 => PhaseAction::DummyTx,
2 => PhaseAction::Rx,
3 => PhaseAction::Poll,
_ => unreachable!(),
}
}
#[doc = "TX"]
#[inline(always)]
pub fn is_tx(&self) -> bool {
*self == PhaseAction::Tx
}
#[doc = "Dummy TX"]
#[inline(always)]
pub fn is_dummy_tx(&self) -> bool {
*self == PhaseAction::DummyTx
}
#[doc = "RX"]
#[inline(always)]
pub fn is_rx(&self) -> bool {
*self == PhaseAction::Rx
}
#[doc = "Poll"]
#[inline(always)]
pub fn is_poll(&self) -> bool {
*self == PhaseAction::Poll
}
}
#[doc = "Field `PHASE_ACTION` writer - Phase action"]
pub type PhaseActionW<'a, REG> = crate::FieldWriter<'a, REG, 2, PhaseAction, crate::Safe>;
impl<'a, REG> PhaseActionW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "TX"]
#[inline(always)]
pub fn tx(self) -> &'a mut crate::W<REG> {
self.variant(PhaseAction::Tx)
}
#[doc = "Dummy TX"]
#[inline(always)]
pub fn dummy_tx(self) -> &'a mut crate::W<REG> {
self.variant(PhaseAction::DummyTx)
}
#[doc = "RX"]
#[inline(always)]
pub fn rx(self) -> &'a mut crate::W<REG> {
self.variant(PhaseAction::Rx)
}
#[doc = "Poll"]
#[inline(always)]
pub fn poll(self) -> &'a mut crate::W<REG> {
self.variant(PhaseAction::Poll)
}
}
#[doc = "Field `BYTE_CNT` reader - Phase byte count"]
pub type ByteCntR = crate::FieldReader<u16>;
#[doc = "Field `BYTE_CNT` writer - Phase byte count"]
pub type ByteCntW<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
#[doc = "SPI mode\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum SpiMode {
#[doc = "0: Single"]
Single = 0,
#[doc = "1: Dual"]
Dual = 1,
#[doc = "2: Quad"]
Quad = 2,
}
impl From<SpiMode> for u8 {
#[inline(always)]
fn from(variant: SpiMode) -> Self {
variant as _
}
}
impl crate::FieldSpec for SpiMode {
type Ux = u8;
}
impl crate::IsEnum for SpiMode {}
#[doc = "Field `SPI_MODE` reader - SPI mode"]
pub type SpiModeR = crate::FieldReader<SpiMode>;
impl SpiModeR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<SpiMode> {
match self.bits {
0 => Some(SpiMode::Single),
1 => Some(SpiMode::Dual),
2 => Some(SpiMode::Quad),
_ => None,
}
}
#[doc = "Single"]
#[inline(always)]
pub fn is_single(&self) -> bool {
*self == SpiMode::Single
}
#[doc = "Dual"]
#[inline(always)]
pub fn is_dual(&self) -> bool {
*self == SpiMode::Dual
}
#[doc = "Quad"]
#[inline(always)]
pub fn is_quad(&self) -> bool {
*self == SpiMode::Quad
}
}
#[doc = "Field `SPI_MODE` writer - SPI mode"]
pub type SpiModeW<'a, REG> = crate::FieldWriter<'a, REG, 2, SpiMode>;
impl<'a, REG> SpiModeW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Single"]
#[inline(always)]
pub fn single(self) -> &'a mut crate::W<REG> {
self.variant(SpiMode::Single)
}
#[doc = "Dual"]
#[inline(always)]
pub fn dual(self) -> &'a mut crate::W<REG> {
self.variant(SpiMode::Dual)
}
#[doc = "Quad"]
#[inline(always)]
pub fn quad(self) -> &'a mut crate::W<REG> {
self.variant(SpiMode::Quad)
}
}
impl R {
#[doc = "Bit 0 - Phase start"]
#[inline(always)]
pub fn phase_start(&self) -> PhaseStartR {
PhaseStartR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Phase done"]
#[inline(always)]
pub fn phase_done(&self) -> PhaseDoneR {
PhaseDoneR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Phase error"]
#[inline(always)]
pub fn phase_error(&self) -> PhaseErrorR {
PhaseErrorR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bits 4:5 - Phase action"]
#[inline(always)]
pub fn phase_action(&self) -> PhaseActionR {
PhaseActionR::new(((self.bits >> 4) & 3) as u8)
}
#[doc = "Bits 8:19 - Phase byte count"]
#[inline(always)]
pub fn byte_cnt(&self) -> ByteCntR {
ByteCntR::new(((self.bits >> 8) & 0x0fff) as u16)
}
#[doc = "Bits 20:21 - SPI mode"]
#[inline(always)]
pub fn spi_mode(&self) -> SpiModeR {
SpiModeR::new(((self.bits >> 20) & 3) as u8)
}
}
impl W {
#[doc = "Bits 4:5 - Phase action"]
#[inline(always)]
pub fn phase_action(&mut self) -> PhaseActionW<PhaseCtrl0Spec> {
PhaseActionW::new(self, 4)
}
#[doc = "Bits 8:19 - Phase byte count"]
#[inline(always)]
pub fn byte_cnt(&mut self) -> ByteCntW<PhaseCtrl0Spec> {
ByteCntW::new(self, 8)
}
#[doc = "Bits 20:21 - SPI mode"]
#[inline(always)]
pub fn spi_mode(&mut self) -> SpiModeW<PhaseCtrl0Spec> {
SpiModeW::new(self, 20)
}
}
#[doc = "Phase control 0\n\nYou can [`read`](crate::Reg::read) this register and get [`phase_ctrl0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`phase_ctrl0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PhaseCtrl0Spec;
impl crate::RegisterSpec for PhaseCtrl0Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`phase_ctrl0::R`](R) reader structure"]
impl crate::Readable for PhaseCtrl0Spec {}
#[doc = "`write(|w| ..)` method takes [`phase_ctrl0::W`](W) writer structure"]
impl crate::Writable for PhaseCtrl0Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets PHASE_CTRL[0] to value 0"]
impl crate::Resettable for PhaseCtrl0Spec {}
}
#[doc = "PHASE_CTRL[1] (rw) register accessor: Phase control 1\n\nYou can [`read`](crate::Reg::read) this register and get [`phase_ctrl1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`phase_ctrl1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@phase_ctrl1`] module"]
#[doc(alias = "PHASE_CTRL[1]")]
pub type PhaseCtrl1 = crate::Reg<phase_ctrl1::PhaseCtrl1Spec>;
#[doc = "Phase control 1"]
pub mod phase_ctrl1 {
#[doc = "Register `PHASE_CTRL[1]` reader"]
pub type R = crate::R<PhaseCtrl1Spec>;
#[doc = "Register `PHASE_CTRL[1]` writer"]
pub type W = crate::W<PhaseCtrl1Spec>;
#[doc = "Field `PHASE_START` reader - Phase start"]
pub type PhaseStartR = crate::BitReader;
#[doc = "Field `PHASE_DONE` reader - Phase done"]
pub type PhaseDoneR = crate::BitReader;
#[doc = "Field `PHASE_ERROR` reader - Phase error"]
pub type PhaseErrorR = crate::BitReader;
#[doc = "Phase action\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum PhaseAction {
#[doc = "0: TX"]
Tx = 0,
#[doc = "1: Dummy TX"]
DummyTx = 1,
#[doc = "2: RX"]
Rx = 2,
#[doc = "3: Poll"]
Poll = 3,
}
impl From<PhaseAction> for u8 {
#[inline(always)]
fn from(variant: PhaseAction) -> Self {
variant as _
}
}
impl crate::FieldSpec for PhaseAction {
type Ux = u8;
}
impl crate::IsEnum for PhaseAction {}
#[doc = "Field `PHASE_ACTION` reader - Phase action"]
pub type PhaseActionR = crate::FieldReader<PhaseAction>;
impl PhaseActionR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> PhaseAction {
match self.bits {
0 => PhaseAction::Tx,
1 => PhaseAction::DummyTx,
2 => PhaseAction::Rx,
3 => PhaseAction::Poll,
_ => unreachable!(),
}
}
#[doc = "TX"]
#[inline(always)]
pub fn is_tx(&self) -> bool {
*self == PhaseAction::Tx
}
#[doc = "Dummy TX"]
#[inline(always)]
pub fn is_dummy_tx(&self) -> bool {
*self == PhaseAction::DummyTx
}
#[doc = "RX"]
#[inline(always)]
pub fn is_rx(&self) -> bool {
*self == PhaseAction::Rx
}
#[doc = "Poll"]
#[inline(always)]
pub fn is_poll(&self) -> bool {
*self == PhaseAction::Poll
}
}
#[doc = "Field `PHASE_ACTION` writer - Phase action"]
pub type PhaseActionW<'a, REG> = crate::FieldWriter<'a, REG, 2, PhaseAction, crate::Safe>;
impl<'a, REG> PhaseActionW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "TX"]
#[inline(always)]
pub fn tx(self) -> &'a mut crate::W<REG> {
self.variant(PhaseAction::Tx)
}
#[doc = "Dummy TX"]
#[inline(always)]
pub fn dummy_tx(self) -> &'a mut crate::W<REG> {
self.variant(PhaseAction::DummyTx)
}
#[doc = "RX"]
#[inline(always)]
pub fn rx(self) -> &'a mut crate::W<REG> {
self.variant(PhaseAction::Rx)
}
#[doc = "Poll"]
#[inline(always)]
pub fn poll(self) -> &'a mut crate::W<REG> {
self.variant(PhaseAction::Poll)
}
}
#[doc = "Field `BYTE_CNT` reader - Phase byte count"]
pub type ByteCntR = crate::FieldReader<u16>;
#[doc = "Field `BYTE_CNT` writer - Phase byte count"]
pub type ByteCntW<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
#[doc = "SPI mode\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum SpiMode {
#[doc = "0: Single"]
Single = 0,
#[doc = "1: Dual"]
Dual = 1,
#[doc = "2: Quad"]
Quad = 2,
}
impl From<SpiMode> for u8 {
#[inline(always)]
fn from(variant: SpiMode) -> Self {
variant as _
}
}
impl crate::FieldSpec for SpiMode {
type Ux = u8;
}
impl crate::IsEnum for SpiMode {}
#[doc = "Field `SPI_MODE` reader - SPI mode"]
pub type SpiModeR = crate::FieldReader<SpiMode>;
impl SpiModeR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<SpiMode> {
match self.bits {
0 => Some(SpiMode::Single),
1 => Some(SpiMode::Dual),
2 => Some(SpiMode::Quad),
_ => None,
}
}
#[doc = "Single"]
#[inline(always)]
pub fn is_single(&self) -> bool {
*self == SpiMode::Single
}
#[doc = "Dual"]
#[inline(always)]
pub fn is_dual(&self) -> bool {
*self == SpiMode::Dual
}
#[doc = "Quad"]
#[inline(always)]
pub fn is_quad(&self) -> bool {
*self == SpiMode::Quad
}
}
#[doc = "Field `SPI_MODE` writer - SPI mode"]
pub type SpiModeW<'a, REG> = crate::FieldWriter<'a, REG, 2, SpiMode>;
impl<'a, REG> SpiModeW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Single"]
#[inline(always)]
pub fn single(self) -> &'a mut crate::W<REG> {
self.variant(SpiMode::Single)
}
#[doc = "Dual"]
#[inline(always)]
pub fn dual(self) -> &'a mut crate::W<REG> {
self.variant(SpiMode::Dual)
}
#[doc = "Quad"]
#[inline(always)]
pub fn quad(self) -> &'a mut crate::W<REG> {
self.variant(SpiMode::Quad)
}
}
impl R {
#[doc = "Bit 0 - Phase start"]
#[inline(always)]
pub fn phase_start(&self) -> PhaseStartR {
PhaseStartR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Phase done"]
#[inline(always)]
pub fn phase_done(&self) -> PhaseDoneR {
PhaseDoneR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Phase error"]
#[inline(always)]
pub fn phase_error(&self) -> PhaseErrorR {
PhaseErrorR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bits 4:5 - Phase action"]
#[inline(always)]
pub fn phase_action(&self) -> PhaseActionR {
PhaseActionR::new(((self.bits >> 4) & 3) as u8)
}
#[doc = "Bits 8:19 - Phase byte count"]
#[inline(always)]
pub fn byte_cnt(&self) -> ByteCntR {
ByteCntR::new(((self.bits >> 8) & 0x0fff) as u16)
}
#[doc = "Bits 20:21 - SPI mode"]
#[inline(always)]
pub fn spi_mode(&self) -> SpiModeR {
SpiModeR::new(((self.bits >> 20) & 3) as u8)
}
}
impl W {
#[doc = "Bits 4:5 - Phase action"]
#[inline(always)]
pub fn phase_action(&mut self) -> PhaseActionW<PhaseCtrl1Spec> {
PhaseActionW::new(self, 4)
}
#[doc = "Bits 8:19 - Phase byte count"]
#[inline(always)]
pub fn byte_cnt(&mut self) -> ByteCntW<PhaseCtrl1Spec> {
ByteCntW::new(self, 8)
}
#[doc = "Bits 20:21 - SPI mode"]
#[inline(always)]
pub fn spi_mode(&mut self) -> SpiModeW<PhaseCtrl1Spec> {
SpiModeW::new(self, 20)
}
}
#[doc = "Phase control 1\n\nYou can [`read`](crate::Reg::read) this register and get [`phase_ctrl1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`phase_ctrl1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PhaseCtrl1Spec;
impl crate::RegisterSpec for PhaseCtrl1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`phase_ctrl1::R`](R) reader structure"]
impl crate::Readable for PhaseCtrl1Spec {}
#[doc = "`write(|w| ..)` method takes [`phase_ctrl1::W`](W) writer structure"]
impl crate::Writable for PhaseCtrl1Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets PHASE_CTRL[1] to value 0"]
impl crate::Resettable for PhaseCtrl1Spec {}
}
#[doc = "PHASE_CTRL[2] (rw) register accessor: Phase control 2\n\nYou can [`read`](crate::Reg::read) this register and get [`phase_ctrl2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`phase_ctrl2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@phase_ctrl2`] module"]
#[doc(alias = "PHASE_CTRL[2]")]
pub type PhaseCtrl2 = crate::Reg<phase_ctrl2::PhaseCtrl2Spec>;
#[doc = "Phase control 2"]
pub mod phase_ctrl2 {
#[doc = "Register `PHASE_CTRL[2]` reader"]
pub type R = crate::R<PhaseCtrl2Spec>;
#[doc = "Register `PHASE_CTRL[2]` writer"]
pub type W = crate::W<PhaseCtrl2Spec>;
#[doc = "Field `PHASE_START` reader - Phase start"]
pub type PhaseStartR = crate::BitReader;
#[doc = "Field `PHASE_DONE` reader - Phase done"]
pub type PhaseDoneR = crate::BitReader;
#[doc = "Field `PHASE_ERROR` reader - Phase error"]
pub type PhaseErrorR = crate::BitReader;
#[doc = "Phase action\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum PhaseAction {
#[doc = "0: TX"]
Tx = 0,
#[doc = "1: Dummy TX"]
DummyTx = 1,
#[doc = "2: RX"]
Rx = 2,
#[doc = "3: Poll"]
Poll = 3,
}
impl From<PhaseAction> for u8 {
#[inline(always)]
fn from(variant: PhaseAction) -> Self {
variant as _
}
}
impl crate::FieldSpec for PhaseAction {
type Ux = u8;
}
impl crate::IsEnum for PhaseAction {}
#[doc = "Field `PHASE_ACTION` reader - Phase action"]
pub type PhaseActionR = crate::FieldReader<PhaseAction>;
impl PhaseActionR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> PhaseAction {
match self.bits {
0 => PhaseAction::Tx,
1 => PhaseAction::DummyTx,
2 => PhaseAction::Rx,
3 => PhaseAction::Poll,
_ => unreachable!(),
}
}
#[doc = "TX"]
#[inline(always)]
pub fn is_tx(&self) -> bool {
*self == PhaseAction::Tx
}
#[doc = "Dummy TX"]
#[inline(always)]
pub fn is_dummy_tx(&self) -> bool {
*self == PhaseAction::DummyTx
}
#[doc = "RX"]
#[inline(always)]
pub fn is_rx(&self) -> bool {
*self == PhaseAction::Rx
}
#[doc = "Poll"]
#[inline(always)]
pub fn is_poll(&self) -> bool {
*self == PhaseAction::Poll
}
}
#[doc = "Field `PHASE_ACTION` writer - Phase action"]
pub type PhaseActionW<'a, REG> = crate::FieldWriter<'a, REG, 2, PhaseAction, crate::Safe>;
impl<'a, REG> PhaseActionW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "TX"]
#[inline(always)]
pub fn tx(self) -> &'a mut crate::W<REG> {
self.variant(PhaseAction::Tx)
}
#[doc = "Dummy TX"]
#[inline(always)]
pub fn dummy_tx(self) -> &'a mut crate::W<REG> {
self.variant(PhaseAction::DummyTx)
}
#[doc = "RX"]
#[inline(always)]
pub fn rx(self) -> &'a mut crate::W<REG> {
self.variant(PhaseAction::Rx)
}
#[doc = "Poll"]
#[inline(always)]
pub fn poll(self) -> &'a mut crate::W<REG> {
self.variant(PhaseAction::Poll)
}
}
#[doc = "Field `BYTE_CNT` reader - Phase byte count"]
pub type ByteCntR = crate::FieldReader<u16>;
#[doc = "Field `BYTE_CNT` writer - Phase byte count"]
pub type ByteCntW<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
#[doc = "SPI mode\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum SpiMode {
#[doc = "0: Single"]
Single = 0,
#[doc = "1: Dual"]
Dual = 1,
#[doc = "2: Quad"]
Quad = 2,
}
impl From<SpiMode> for u8 {
#[inline(always)]
fn from(variant: SpiMode) -> Self {
variant as _
}
}
impl crate::FieldSpec for SpiMode {
type Ux = u8;
}
impl crate::IsEnum for SpiMode {}
#[doc = "Field `SPI_MODE` reader - SPI mode"]
pub type SpiModeR = crate::FieldReader<SpiMode>;
impl SpiModeR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<SpiMode> {
match self.bits {
0 => Some(SpiMode::Single),
1 => Some(SpiMode::Dual),
2 => Some(SpiMode::Quad),
_ => None,
}
}
#[doc = "Single"]
#[inline(always)]
pub fn is_single(&self) -> bool {
*self == SpiMode::Single
}
#[doc = "Dual"]
#[inline(always)]
pub fn is_dual(&self) -> bool {
*self == SpiMode::Dual
}
#[doc = "Quad"]
#[inline(always)]
pub fn is_quad(&self) -> bool {
*self == SpiMode::Quad
}
}
#[doc = "Field `SPI_MODE` writer - SPI mode"]
pub type SpiModeW<'a, REG> = crate::FieldWriter<'a, REG, 2, SpiMode>;
impl<'a, REG> SpiModeW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Single"]
#[inline(always)]
pub fn single(self) -> &'a mut crate::W<REG> {
self.variant(SpiMode::Single)
}
#[doc = "Dual"]
#[inline(always)]
pub fn dual(self) -> &'a mut crate::W<REG> {
self.variant(SpiMode::Dual)
}
#[doc = "Quad"]
#[inline(always)]
pub fn quad(self) -> &'a mut crate::W<REG> {
self.variant(SpiMode::Quad)
}
}
impl R {
#[doc = "Bit 0 - Phase start"]
#[inline(always)]
pub fn phase_start(&self) -> PhaseStartR {
PhaseStartR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Phase done"]
#[inline(always)]
pub fn phase_done(&self) -> PhaseDoneR {
PhaseDoneR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Phase error"]
#[inline(always)]
pub fn phase_error(&self) -> PhaseErrorR {
PhaseErrorR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bits 4:5 - Phase action"]
#[inline(always)]
pub fn phase_action(&self) -> PhaseActionR {
PhaseActionR::new(((self.bits >> 4) & 3) as u8)
}
#[doc = "Bits 8:19 - Phase byte count"]
#[inline(always)]
pub fn byte_cnt(&self) -> ByteCntR {
ByteCntR::new(((self.bits >> 8) & 0x0fff) as u16)
}
#[doc = "Bits 20:21 - SPI mode"]
#[inline(always)]
pub fn spi_mode(&self) -> SpiModeR {
SpiModeR::new(((self.bits >> 20) & 3) as u8)
}
}
impl W {
#[doc = "Bits 4:5 - Phase action"]
#[inline(always)]
pub fn phase_action(&mut self) -> PhaseActionW<PhaseCtrl2Spec> {
PhaseActionW::new(self, 4)
}
#[doc = "Bits 8:19 - Phase byte count"]
#[inline(always)]
pub fn byte_cnt(&mut self) -> ByteCntW<PhaseCtrl2Spec> {
ByteCntW::new(self, 8)
}
#[doc = "Bits 20:21 - SPI mode"]
#[inline(always)]
pub fn spi_mode(&mut self) -> SpiModeW<PhaseCtrl2Spec> {
SpiModeW::new(self, 20)
}
}
#[doc = "Phase control 2\n\nYou can [`read`](crate::Reg::read) this register and get [`phase_ctrl2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`phase_ctrl2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PhaseCtrl2Spec;
impl crate::RegisterSpec for PhaseCtrl2Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`phase_ctrl2::R`](R) reader structure"]
impl crate::Readable for PhaseCtrl2Spec {}
#[doc = "`write(|w| ..)` method takes [`phase_ctrl2::W`](W) writer structure"]
impl crate::Writable for PhaseCtrl2Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets PHASE_CTRL[2] to value 0"]
impl crate::Resettable for PhaseCtrl2Spec {}
}
#[doc = "PHASE_CTRL[3] (rw) register accessor: Phase control 3\n\nYou can [`read`](crate::Reg::read) this register and get [`phase_ctrl3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`phase_ctrl3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@phase_ctrl3`] module"]
#[doc(alias = "PHASE_CTRL[3]")]
pub type PhaseCtrl3 = crate::Reg<phase_ctrl3::PhaseCtrl3Spec>;
#[doc = "Phase control 3"]
pub mod phase_ctrl3 {
#[doc = "Register `PHASE_CTRL[3]` reader"]
pub type R = crate::R<PhaseCtrl3Spec>;
#[doc = "Register `PHASE_CTRL[3]` writer"]
pub type W = crate::W<PhaseCtrl3Spec>;
#[doc = "Field `PHASE_START` reader - Phase start"]
pub type PhaseStartR = crate::BitReader;
#[doc = "Field `PHASE_DONE` reader - Phase done"]
pub type PhaseDoneR = crate::BitReader;
#[doc = "Field `PHASE_ERROR` reader - Phase error"]
pub type PhaseErrorR = crate::BitReader;
#[doc = "Phase action\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum PhaseAction {
#[doc = "0: TX"]
Tx = 0,
#[doc = "1: Dummy TX"]
DummyTx = 1,
#[doc = "2: RX"]
Rx = 2,
#[doc = "3: Poll"]
Poll = 3,
}
impl From<PhaseAction> for u8 {
#[inline(always)]
fn from(variant: PhaseAction) -> Self {
variant as _
}
}
impl crate::FieldSpec for PhaseAction {
type Ux = u8;
}
impl crate::IsEnum for PhaseAction {}
#[doc = "Field `PHASE_ACTION` reader - Phase action"]
pub type PhaseActionR = crate::FieldReader<PhaseAction>;
impl PhaseActionR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> PhaseAction {
match self.bits {
0 => PhaseAction::Tx,
1 => PhaseAction::DummyTx,
2 => PhaseAction::Rx,
3 => PhaseAction::Poll,
_ => unreachable!(),
}
}
#[doc = "TX"]
#[inline(always)]
pub fn is_tx(&self) -> bool {
*self == PhaseAction::Tx
}
#[doc = "Dummy TX"]
#[inline(always)]
pub fn is_dummy_tx(&self) -> bool {
*self == PhaseAction::DummyTx
}
#[doc = "RX"]
#[inline(always)]
pub fn is_rx(&self) -> bool {
*self == PhaseAction::Rx
}
#[doc = "Poll"]
#[inline(always)]
pub fn is_poll(&self) -> bool {
*self == PhaseAction::Poll
}
}
#[doc = "Field `PHASE_ACTION` writer - Phase action"]
pub type PhaseActionW<'a, REG> = crate::FieldWriter<'a, REG, 2, PhaseAction, crate::Safe>;
impl<'a, REG> PhaseActionW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "TX"]
#[inline(always)]
pub fn tx(self) -> &'a mut crate::W<REG> {
self.variant(PhaseAction::Tx)
}
#[doc = "Dummy TX"]
#[inline(always)]
pub fn dummy_tx(self) -> &'a mut crate::W<REG> {
self.variant(PhaseAction::DummyTx)
}
#[doc = "RX"]
#[inline(always)]
pub fn rx(self) -> &'a mut crate::W<REG> {
self.variant(PhaseAction::Rx)
}
#[doc = "Poll"]
#[inline(always)]
pub fn poll(self) -> &'a mut crate::W<REG> {
self.variant(PhaseAction::Poll)
}
}
#[doc = "Field `BYTE_CNT` reader - Phase byte count"]
pub type ByteCntR = crate::FieldReader<u16>;
#[doc = "Field `BYTE_CNT` writer - Phase byte count"]
pub type ByteCntW<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
#[doc = "SPI mode\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum SpiMode {
#[doc = "0: Single"]
Single = 0,
#[doc = "1: Dual"]
Dual = 1,
#[doc = "2: Quad"]
Quad = 2,
}
impl From<SpiMode> for u8 {
#[inline(always)]
fn from(variant: SpiMode) -> Self {
variant as _
}
}
impl crate::FieldSpec for SpiMode {
type Ux = u8;
}
impl crate::IsEnum for SpiMode {}
#[doc = "Field `SPI_MODE` reader - SPI mode"]
pub type SpiModeR = crate::FieldReader<SpiMode>;
impl SpiModeR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<SpiMode> {
match self.bits {
0 => Some(SpiMode::Single),
1 => Some(SpiMode::Dual),
2 => Some(SpiMode::Quad),
_ => None,
}
}
#[doc = "Single"]
#[inline(always)]
pub fn is_single(&self) -> bool {
*self == SpiMode::Single
}
#[doc = "Dual"]
#[inline(always)]
pub fn is_dual(&self) -> bool {
*self == SpiMode::Dual
}
#[doc = "Quad"]
#[inline(always)]
pub fn is_quad(&self) -> bool {
*self == SpiMode::Quad
}
}
#[doc = "Field `SPI_MODE` writer - SPI mode"]
pub type SpiModeW<'a, REG> = crate::FieldWriter<'a, REG, 2, SpiMode>;
impl<'a, REG> SpiModeW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Single"]
#[inline(always)]
pub fn single(self) -> &'a mut crate::W<REG> {
self.variant(SpiMode::Single)
}
#[doc = "Dual"]
#[inline(always)]
pub fn dual(self) -> &'a mut crate::W<REG> {
self.variant(SpiMode::Dual)
}
#[doc = "Quad"]
#[inline(always)]
pub fn quad(self) -> &'a mut crate::W<REG> {
self.variant(SpiMode::Quad)
}
}
impl R {
#[doc = "Bit 0 - Phase start"]
#[inline(always)]
pub fn phase_start(&self) -> PhaseStartR {
PhaseStartR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Phase done"]
#[inline(always)]
pub fn phase_done(&self) -> PhaseDoneR {
PhaseDoneR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Phase error"]
#[inline(always)]
pub fn phase_error(&self) -> PhaseErrorR {
PhaseErrorR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bits 4:5 - Phase action"]
#[inline(always)]
pub fn phase_action(&self) -> PhaseActionR {
PhaseActionR::new(((self.bits >> 4) & 3) as u8)
}
#[doc = "Bits 8:19 - Phase byte count"]
#[inline(always)]
pub fn byte_cnt(&self) -> ByteCntR {
ByteCntR::new(((self.bits >> 8) & 0x0fff) as u16)
}
#[doc = "Bits 20:21 - SPI mode"]
#[inline(always)]
pub fn spi_mode(&self) -> SpiModeR {
SpiModeR::new(((self.bits >> 20) & 3) as u8)
}
}
impl W {
#[doc = "Bits 4:5 - Phase action"]
#[inline(always)]
pub fn phase_action(&mut self) -> PhaseActionW<PhaseCtrl3Spec> {
PhaseActionW::new(self, 4)
}
#[doc = "Bits 8:19 - Phase byte count"]
#[inline(always)]
pub fn byte_cnt(&mut self) -> ByteCntW<PhaseCtrl3Spec> {
ByteCntW::new(self, 8)
}
#[doc = "Bits 20:21 - SPI mode"]
#[inline(always)]
pub fn spi_mode(&mut self) -> SpiModeW<PhaseCtrl3Spec> {
SpiModeW::new(self, 20)
}
}
#[doc = "Phase control 3\n\nYou can [`read`](crate::Reg::read) this register and get [`phase_ctrl3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`phase_ctrl3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PhaseCtrl3Spec;
impl crate::RegisterSpec for PhaseCtrl3Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`phase_ctrl3::R`](R) reader structure"]
impl crate::Readable for PhaseCtrl3Spec {}
#[doc = "`write(|w| ..)` method takes [`phase_ctrl3::W`](W) writer structure"]
impl crate::Writable for PhaseCtrl3Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets PHASE_CTRL[3] to value 0"]
impl crate::Resettable for PhaseCtrl3Spec {}
}
#[doc = "PHASE_CTRL[4] (rw) register accessor: Phase control 4\n\nYou can [`read`](crate::Reg::read) this register and get [`phase_ctrl4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`phase_ctrl4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@phase_ctrl4`] module"]
#[doc(alias = "PHASE_CTRL[4]")]
pub type PhaseCtrl4 = crate::Reg<phase_ctrl4::PhaseCtrl4Spec>;
#[doc = "Phase control 4"]
pub mod phase_ctrl4 {
#[doc = "Register `PHASE_CTRL[4]` reader"]
pub type R = crate::R<PhaseCtrl4Spec>;
#[doc = "Register `PHASE_CTRL[4]` writer"]
pub type W = crate::W<PhaseCtrl4Spec>;
#[doc = "Field `PHASE_START` reader - Phase start"]
pub type PhaseStartR = crate::BitReader;
#[doc = "Field `PHASE_DONE` reader - Phase done"]
pub type PhaseDoneR = crate::BitReader;
#[doc = "Field `PHASE_ERROR` reader - Phase error"]
pub type PhaseErrorR = crate::BitReader;
#[doc = "Phase action\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum PhaseAction {
#[doc = "0: TX"]
Tx = 0,
#[doc = "1: Dummy TX"]
DummyTx = 1,
#[doc = "2: RX"]
Rx = 2,
#[doc = "3: Poll"]
Poll = 3,
}
impl From<PhaseAction> for u8 {
#[inline(always)]
fn from(variant: PhaseAction) -> Self {
variant as _
}
}
impl crate::FieldSpec for PhaseAction {
type Ux = u8;
}
impl crate::IsEnum for PhaseAction {}
#[doc = "Field `PHASE_ACTION` reader - Phase action"]
pub type PhaseActionR = crate::FieldReader<PhaseAction>;
impl PhaseActionR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> PhaseAction {
match self.bits {
0 => PhaseAction::Tx,
1 => PhaseAction::DummyTx,
2 => PhaseAction::Rx,
3 => PhaseAction::Poll,
_ => unreachable!(),
}
}
#[doc = "TX"]
#[inline(always)]
pub fn is_tx(&self) -> bool {
*self == PhaseAction::Tx
}
#[doc = "Dummy TX"]
#[inline(always)]
pub fn is_dummy_tx(&self) -> bool {
*self == PhaseAction::DummyTx
}
#[doc = "RX"]
#[inline(always)]
pub fn is_rx(&self) -> bool {
*self == PhaseAction::Rx
}
#[doc = "Poll"]
#[inline(always)]
pub fn is_poll(&self) -> bool {
*self == PhaseAction::Poll
}
}
#[doc = "Field `PHASE_ACTION` writer - Phase action"]
pub type PhaseActionW<'a, REG> = crate::FieldWriter<'a, REG, 2, PhaseAction, crate::Safe>;
impl<'a, REG> PhaseActionW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "TX"]
#[inline(always)]
pub fn tx(self) -> &'a mut crate::W<REG> {
self.variant(PhaseAction::Tx)
}
#[doc = "Dummy TX"]
#[inline(always)]
pub fn dummy_tx(self) -> &'a mut crate::W<REG> {
self.variant(PhaseAction::DummyTx)
}
#[doc = "RX"]
#[inline(always)]
pub fn rx(self) -> &'a mut crate::W<REG> {
self.variant(PhaseAction::Rx)
}
#[doc = "Poll"]
#[inline(always)]
pub fn poll(self) -> &'a mut crate::W<REG> {
self.variant(PhaseAction::Poll)
}
}
#[doc = "Field `BYTE_CNT` reader - Phase byte count"]
pub type ByteCntR = crate::FieldReader<u16>;
#[doc = "Field `BYTE_CNT` writer - Phase byte count"]
pub type ByteCntW<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
#[doc = "SPI mode\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum SpiMode {
#[doc = "0: Single"]
Single = 0,
#[doc = "1: Dual"]
Dual = 1,
#[doc = "2: Quad"]
Quad = 2,
}
impl From<SpiMode> for u8 {
#[inline(always)]
fn from(variant: SpiMode) -> Self {
variant as _
}
}
impl crate::FieldSpec for SpiMode {
type Ux = u8;
}
impl crate::IsEnum for SpiMode {}
#[doc = "Field `SPI_MODE` reader - SPI mode"]
pub type SpiModeR = crate::FieldReader<SpiMode>;
impl SpiModeR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<SpiMode> {
match self.bits {
0 => Some(SpiMode::Single),
1 => Some(SpiMode::Dual),
2 => Some(SpiMode::Quad),
_ => None,
}
}
#[doc = "Single"]
#[inline(always)]
pub fn is_single(&self) -> bool {
*self == SpiMode::Single
}
#[doc = "Dual"]
#[inline(always)]
pub fn is_dual(&self) -> bool {
*self == SpiMode::Dual
}
#[doc = "Quad"]
#[inline(always)]
pub fn is_quad(&self) -> bool {
*self == SpiMode::Quad
}
}
#[doc = "Field `SPI_MODE` writer - SPI mode"]
pub type SpiModeW<'a, REG> = crate::FieldWriter<'a, REG, 2, SpiMode>;
impl<'a, REG> SpiModeW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Single"]
#[inline(always)]
pub fn single(self) -> &'a mut crate::W<REG> {
self.variant(SpiMode::Single)
}
#[doc = "Dual"]
#[inline(always)]
pub fn dual(self) -> &'a mut crate::W<REG> {
self.variant(SpiMode::Dual)
}
#[doc = "Quad"]
#[inline(always)]
pub fn quad(self) -> &'a mut crate::W<REG> {
self.variant(SpiMode::Quad)
}
}
impl R {
#[doc = "Bit 0 - Phase start"]
#[inline(always)]
pub fn phase_start(&self) -> PhaseStartR {
PhaseStartR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Phase done"]
#[inline(always)]
pub fn phase_done(&self) -> PhaseDoneR {
PhaseDoneR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Phase error"]
#[inline(always)]
pub fn phase_error(&self) -> PhaseErrorR {
PhaseErrorR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bits 4:5 - Phase action"]
#[inline(always)]
pub fn phase_action(&self) -> PhaseActionR {
PhaseActionR::new(((self.bits >> 4) & 3) as u8)
}
#[doc = "Bits 8:19 - Phase byte count"]
#[inline(always)]
pub fn byte_cnt(&self) -> ByteCntR {
ByteCntR::new(((self.bits >> 8) & 0x0fff) as u16)
}
#[doc = "Bits 20:21 - SPI mode"]
#[inline(always)]
pub fn spi_mode(&self) -> SpiModeR {
SpiModeR::new(((self.bits >> 20) & 3) as u8)
}
}
impl W {
#[doc = "Bits 4:5 - Phase action"]
#[inline(always)]
pub fn phase_action(&mut self) -> PhaseActionW<PhaseCtrl4Spec> {
PhaseActionW::new(self, 4)
}
#[doc = "Bits 8:19 - Phase byte count"]
#[inline(always)]
pub fn byte_cnt(&mut self) -> ByteCntW<PhaseCtrl4Spec> {
ByteCntW::new(self, 8)
}
#[doc = "Bits 20:21 - SPI mode"]
#[inline(always)]
pub fn spi_mode(&mut self) -> SpiModeW<PhaseCtrl4Spec> {
SpiModeW::new(self, 20)
}
}
#[doc = "Phase control 4\n\nYou can [`read`](crate::Reg::read) this register and get [`phase_ctrl4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`phase_ctrl4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PhaseCtrl4Spec;
impl crate::RegisterSpec for PhaseCtrl4Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`phase_ctrl4::R`](R) reader structure"]
impl crate::Readable for PhaseCtrl4Spec {}
#[doc = "`write(|w| ..)` method takes [`phase_ctrl4::W`](W) writer structure"]
impl crate::Writable for PhaseCtrl4Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets PHASE_CTRL[4] to value 0"]
impl crate::Resettable for PhaseCtrl4Spec {}
}
#[doc = "PHASE_CTRL[5] (rw) register accessor: Phase control 5\n\nYou can [`read`](crate::Reg::read) this register and get [`phase_ctrl5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`phase_ctrl5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@phase_ctrl5`] module"]
#[doc(alias = "PHASE_CTRL[5]")]
pub type PhaseCtrl5 = crate::Reg<phase_ctrl5::PhaseCtrl5Spec>;
#[doc = "Phase control 5"]
pub mod phase_ctrl5 {
#[doc = "Register `PHASE_CTRL[5]` reader"]
pub type R = crate::R<PhaseCtrl5Spec>;
#[doc = "Register `PHASE_CTRL[5]` writer"]
pub type W = crate::W<PhaseCtrl5Spec>;
#[doc = "Field `PHASE_START` reader - Phase start"]
pub type PhaseStartR = crate::BitReader;
#[doc = "Field `PHASE_DONE` reader - Phase done"]
pub type PhaseDoneR = crate::BitReader;
#[doc = "Field `PHASE_ERROR` reader - Phase error"]
pub type PhaseErrorR = crate::BitReader;
#[doc = "Phase action\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum PhaseAction {
#[doc = "0: TX"]
Tx = 0,
#[doc = "1: Dummy TX"]
DummyTx = 1,
#[doc = "2: RX"]
Rx = 2,
#[doc = "3: Poll"]
Poll = 3,
}
impl From<PhaseAction> for u8 {
#[inline(always)]
fn from(variant: PhaseAction) -> Self {
variant as _
}
}
impl crate::FieldSpec for PhaseAction {
type Ux = u8;
}
impl crate::IsEnum for PhaseAction {}
#[doc = "Field `PHASE_ACTION` reader - Phase action"]
pub type PhaseActionR = crate::FieldReader<PhaseAction>;
impl PhaseActionR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> PhaseAction {
match self.bits {
0 => PhaseAction::Tx,
1 => PhaseAction::DummyTx,
2 => PhaseAction::Rx,
3 => PhaseAction::Poll,
_ => unreachable!(),
}
}
#[doc = "TX"]
#[inline(always)]
pub fn is_tx(&self) -> bool {
*self == PhaseAction::Tx
}
#[doc = "Dummy TX"]
#[inline(always)]
pub fn is_dummy_tx(&self) -> bool {
*self == PhaseAction::DummyTx
}
#[doc = "RX"]
#[inline(always)]
pub fn is_rx(&self) -> bool {
*self == PhaseAction::Rx
}
#[doc = "Poll"]
#[inline(always)]
pub fn is_poll(&self) -> bool {
*self == PhaseAction::Poll
}
}
#[doc = "Field `PHASE_ACTION` writer - Phase action"]
pub type PhaseActionW<'a, REG> = crate::FieldWriter<'a, REG, 2, PhaseAction, crate::Safe>;
impl<'a, REG> PhaseActionW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "TX"]
#[inline(always)]
pub fn tx(self) -> &'a mut crate::W<REG> {
self.variant(PhaseAction::Tx)
}
#[doc = "Dummy TX"]
#[inline(always)]
pub fn dummy_tx(self) -> &'a mut crate::W<REG> {
self.variant(PhaseAction::DummyTx)
}
#[doc = "RX"]
#[inline(always)]
pub fn rx(self) -> &'a mut crate::W<REG> {
self.variant(PhaseAction::Rx)
}
#[doc = "Poll"]
#[inline(always)]
pub fn poll(self) -> &'a mut crate::W<REG> {
self.variant(PhaseAction::Poll)
}
}
#[doc = "Field `BYTE_CNT` reader - Phase byte count"]
pub type ByteCntR = crate::FieldReader<u16>;
#[doc = "Field `BYTE_CNT` writer - Phase byte count"]
pub type ByteCntW<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
#[doc = "SPI mode\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum SpiMode {
#[doc = "0: Single"]
Single = 0,
#[doc = "1: Dual"]
Dual = 1,
#[doc = "2: Quad"]
Quad = 2,
}
impl From<SpiMode> for u8 {
#[inline(always)]
fn from(variant: SpiMode) -> Self {
variant as _
}
}
impl crate::FieldSpec for SpiMode {
type Ux = u8;
}
impl crate::IsEnum for SpiMode {}
#[doc = "Field `SPI_MODE` reader - SPI mode"]
pub type SpiModeR = crate::FieldReader<SpiMode>;
impl SpiModeR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<SpiMode> {
match self.bits {
0 => Some(SpiMode::Single),
1 => Some(SpiMode::Dual),
2 => Some(SpiMode::Quad),
_ => None,
}
}
#[doc = "Single"]
#[inline(always)]
pub fn is_single(&self) -> bool {
*self == SpiMode::Single
}
#[doc = "Dual"]
#[inline(always)]
pub fn is_dual(&self) -> bool {
*self == SpiMode::Dual
}
#[doc = "Quad"]
#[inline(always)]
pub fn is_quad(&self) -> bool {
*self == SpiMode::Quad
}
}
#[doc = "Field `SPI_MODE` writer - SPI mode"]
pub type SpiModeW<'a, REG> = crate::FieldWriter<'a, REG, 2, SpiMode>;
impl<'a, REG> SpiModeW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Single"]
#[inline(always)]
pub fn single(self) -> &'a mut crate::W<REG> {
self.variant(SpiMode::Single)
}
#[doc = "Dual"]
#[inline(always)]
pub fn dual(self) -> &'a mut crate::W<REG> {
self.variant(SpiMode::Dual)
}
#[doc = "Quad"]
#[inline(always)]
pub fn quad(self) -> &'a mut crate::W<REG> {
self.variant(SpiMode::Quad)
}
}
impl R {
#[doc = "Bit 0 - Phase start"]
#[inline(always)]
pub fn phase_start(&self) -> PhaseStartR {
PhaseStartR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Phase done"]
#[inline(always)]
pub fn phase_done(&self) -> PhaseDoneR {
PhaseDoneR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Phase error"]
#[inline(always)]
pub fn phase_error(&self) -> PhaseErrorR {
PhaseErrorR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bits 4:5 - Phase action"]
#[inline(always)]
pub fn phase_action(&self) -> PhaseActionR {
PhaseActionR::new(((self.bits >> 4) & 3) as u8)
}
#[doc = "Bits 8:19 - Phase byte count"]
#[inline(always)]
pub fn byte_cnt(&self) -> ByteCntR {
ByteCntR::new(((self.bits >> 8) & 0x0fff) as u16)
}
#[doc = "Bits 20:21 - SPI mode"]
#[inline(always)]
pub fn spi_mode(&self) -> SpiModeR {
SpiModeR::new(((self.bits >> 20) & 3) as u8)
}
}
impl W {
#[doc = "Bits 4:5 - Phase action"]
#[inline(always)]
pub fn phase_action(&mut self) -> PhaseActionW<PhaseCtrl5Spec> {
PhaseActionW::new(self, 4)
}
#[doc = "Bits 8:19 - Phase byte count"]
#[inline(always)]
pub fn byte_cnt(&mut self) -> ByteCntW<PhaseCtrl5Spec> {
ByteCntW::new(self, 8)
}
#[doc = "Bits 20:21 - SPI mode"]
#[inline(always)]
pub fn spi_mode(&mut self) -> SpiModeW<PhaseCtrl5Spec> {
SpiModeW::new(self, 20)
}
}
#[doc = "Phase control 5\n\nYou can [`read`](crate::Reg::read) this register and get [`phase_ctrl5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`phase_ctrl5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PhaseCtrl5Spec;
impl crate::RegisterSpec for PhaseCtrl5Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`phase_ctrl5::R`](R) reader structure"]
impl crate::Readable for PhaseCtrl5Spec {}
#[doc = "`write(|w| ..)` method takes [`phase_ctrl5::W`](W) writer structure"]
impl crate::Writable for PhaseCtrl5Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets PHASE_CTRL[5] to value 0"]
impl crate::Resettable for PhaseCtrl5Spec {}
}
#[doc = "PHASE_CTRL[6] (rw) register accessor: Phase control 6\n\nYou can [`read`](crate::Reg::read) this register and get [`phase_ctrl6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`phase_ctrl6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@phase_ctrl6`] module"]
#[doc(alias = "PHASE_CTRL[6]")]
pub type PhaseCtrl6 = crate::Reg<phase_ctrl6::PhaseCtrl6Spec>;
#[doc = "Phase control 6"]
pub mod phase_ctrl6 {
#[doc = "Register `PHASE_CTRL[6]` reader"]
pub type R = crate::R<PhaseCtrl6Spec>;
#[doc = "Register `PHASE_CTRL[6]` writer"]
pub type W = crate::W<PhaseCtrl6Spec>;
#[doc = "Field `PHASE_START` reader - Phase start"]
pub type PhaseStartR = crate::BitReader;
#[doc = "Field `PHASE_DONE` reader - Phase done"]
pub type PhaseDoneR = crate::BitReader;
#[doc = "Field `PHASE_ERROR` reader - Phase error"]
pub type PhaseErrorR = crate::BitReader;
#[doc = "Phase action\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum PhaseAction {
#[doc = "0: TX"]
Tx = 0,
#[doc = "1: Dummy TX"]
DummyTx = 1,
#[doc = "2: RX"]
Rx = 2,
#[doc = "3: Poll"]
Poll = 3,
}
impl From<PhaseAction> for u8 {
#[inline(always)]
fn from(variant: PhaseAction) -> Self {
variant as _
}
}
impl crate::FieldSpec for PhaseAction {
type Ux = u8;
}
impl crate::IsEnum for PhaseAction {}
#[doc = "Field `PHASE_ACTION` reader - Phase action"]
pub type PhaseActionR = crate::FieldReader<PhaseAction>;
impl PhaseActionR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> PhaseAction {
match self.bits {
0 => PhaseAction::Tx,
1 => PhaseAction::DummyTx,
2 => PhaseAction::Rx,
3 => PhaseAction::Poll,
_ => unreachable!(),
}
}
#[doc = "TX"]
#[inline(always)]
pub fn is_tx(&self) -> bool {
*self == PhaseAction::Tx
}
#[doc = "Dummy TX"]
#[inline(always)]
pub fn is_dummy_tx(&self) -> bool {
*self == PhaseAction::DummyTx
}
#[doc = "RX"]
#[inline(always)]
pub fn is_rx(&self) -> bool {
*self == PhaseAction::Rx
}
#[doc = "Poll"]
#[inline(always)]
pub fn is_poll(&self) -> bool {
*self == PhaseAction::Poll
}
}
#[doc = "Field `PHASE_ACTION` writer - Phase action"]
pub type PhaseActionW<'a, REG> = crate::FieldWriter<'a, REG, 2, PhaseAction, crate::Safe>;
impl<'a, REG> PhaseActionW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "TX"]
#[inline(always)]
pub fn tx(self) -> &'a mut crate::W<REG> {
self.variant(PhaseAction::Tx)
}
#[doc = "Dummy TX"]
#[inline(always)]
pub fn dummy_tx(self) -> &'a mut crate::W<REG> {
self.variant(PhaseAction::DummyTx)
}
#[doc = "RX"]
#[inline(always)]
pub fn rx(self) -> &'a mut crate::W<REG> {
self.variant(PhaseAction::Rx)
}
#[doc = "Poll"]
#[inline(always)]
pub fn poll(self) -> &'a mut crate::W<REG> {
self.variant(PhaseAction::Poll)
}
}
#[doc = "Field `BYTE_CNT` reader - Phase byte count"]
pub type ByteCntR = crate::FieldReader<u16>;
#[doc = "Field `BYTE_CNT` writer - Phase byte count"]
pub type ByteCntW<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
#[doc = "SPI mode\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum SpiMode {
#[doc = "0: Single"]
Single = 0,
#[doc = "1: Dual"]
Dual = 1,
#[doc = "2: Quad"]
Quad = 2,
}
impl From<SpiMode> for u8 {
#[inline(always)]
fn from(variant: SpiMode) -> Self {
variant as _
}
}
impl crate::FieldSpec for SpiMode {
type Ux = u8;
}
impl crate::IsEnum for SpiMode {}
#[doc = "Field `SPI_MODE` reader - SPI mode"]
pub type SpiModeR = crate::FieldReader<SpiMode>;
impl SpiModeR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<SpiMode> {
match self.bits {
0 => Some(SpiMode::Single),
1 => Some(SpiMode::Dual),
2 => Some(SpiMode::Quad),
_ => None,
}
}
#[doc = "Single"]
#[inline(always)]
pub fn is_single(&self) -> bool {
*self == SpiMode::Single
}
#[doc = "Dual"]
#[inline(always)]
pub fn is_dual(&self) -> bool {
*self == SpiMode::Dual
}
#[doc = "Quad"]
#[inline(always)]
pub fn is_quad(&self) -> bool {
*self == SpiMode::Quad
}
}
#[doc = "Field `SPI_MODE` writer - SPI mode"]
pub type SpiModeW<'a, REG> = crate::FieldWriter<'a, REG, 2, SpiMode>;
impl<'a, REG> SpiModeW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Single"]
#[inline(always)]
pub fn single(self) -> &'a mut crate::W<REG> {
self.variant(SpiMode::Single)
}
#[doc = "Dual"]
#[inline(always)]
pub fn dual(self) -> &'a mut crate::W<REG> {
self.variant(SpiMode::Dual)
}
#[doc = "Quad"]
#[inline(always)]
pub fn quad(self) -> &'a mut crate::W<REG> {
self.variant(SpiMode::Quad)
}
}
impl R {
#[doc = "Bit 0 - Phase start"]
#[inline(always)]
pub fn phase_start(&self) -> PhaseStartR {
PhaseStartR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Phase done"]
#[inline(always)]
pub fn phase_done(&self) -> PhaseDoneR {
PhaseDoneR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Phase error"]
#[inline(always)]
pub fn phase_error(&self) -> PhaseErrorR {
PhaseErrorR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bits 4:5 - Phase action"]
#[inline(always)]
pub fn phase_action(&self) -> PhaseActionR {
PhaseActionR::new(((self.bits >> 4) & 3) as u8)
}
#[doc = "Bits 8:19 - Phase byte count"]
#[inline(always)]
pub fn byte_cnt(&self) -> ByteCntR {
ByteCntR::new(((self.bits >> 8) & 0x0fff) as u16)
}
#[doc = "Bits 20:21 - SPI mode"]
#[inline(always)]
pub fn spi_mode(&self) -> SpiModeR {
SpiModeR::new(((self.bits >> 20) & 3) as u8)
}
}
impl W {
#[doc = "Bits 4:5 - Phase action"]
#[inline(always)]
pub fn phase_action(&mut self) -> PhaseActionW<PhaseCtrl6Spec> {
PhaseActionW::new(self, 4)
}
#[doc = "Bits 8:19 - Phase byte count"]
#[inline(always)]
pub fn byte_cnt(&mut self) -> ByteCntW<PhaseCtrl6Spec> {
ByteCntW::new(self, 8)
}
#[doc = "Bits 20:21 - SPI mode"]
#[inline(always)]
pub fn spi_mode(&mut self) -> SpiModeW<PhaseCtrl6Spec> {
SpiModeW::new(self, 20)
}
}
#[doc = "Phase control 6\n\nYou can [`read`](crate::Reg::read) this register and get [`phase_ctrl6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`phase_ctrl6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PhaseCtrl6Spec;
impl crate::RegisterSpec for PhaseCtrl6Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`phase_ctrl6::R`](R) reader structure"]
impl crate::Readable for PhaseCtrl6Spec {}
#[doc = "`write(|w| ..)` method takes [`phase_ctrl6::W`](W) writer structure"]
impl crate::Writable for PhaseCtrl6Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets PHASE_CTRL[6] to value 0"]
impl crate::Resettable for PhaseCtrl6Spec {}
}
#[doc = "PHASE_CTRL[7] (rw) register accessor: Phase control 7\n\nYou can [`read`](crate::Reg::read) this register and get [`phase_ctrl7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`phase_ctrl7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@phase_ctrl7`] module"]
#[doc(alias = "PHASE_CTRL[7]")]
pub type PhaseCtrl7 = crate::Reg<phase_ctrl7::PhaseCtrl7Spec>;
#[doc = "Phase control 7"]
pub mod phase_ctrl7 {
#[doc = "Register `PHASE_CTRL[7]` reader"]
pub type R = crate::R<PhaseCtrl7Spec>;
#[doc = "Register `PHASE_CTRL[7]` writer"]
pub type W = crate::W<PhaseCtrl7Spec>;
#[doc = "Field `PHASE_START` reader - Phase start"]
pub type PhaseStartR = crate::BitReader;
#[doc = "Field `PHASE_DONE` reader - Phase done"]
pub type PhaseDoneR = crate::BitReader;
#[doc = "Field `PHASE_ERROR` reader - Phase error"]
pub type PhaseErrorR = crate::BitReader;
#[doc = "Phase action\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum PhaseAction {
#[doc = "0: TX"]
Tx = 0,
#[doc = "1: Dummy TX"]
DummyTx = 1,
#[doc = "2: RX"]
Rx = 2,
#[doc = "3: Poll"]
Poll = 3,
}
impl From<PhaseAction> for u8 {
#[inline(always)]
fn from(variant: PhaseAction) -> Self {
variant as _
}
}
impl crate::FieldSpec for PhaseAction {
type Ux = u8;
}
impl crate::IsEnum for PhaseAction {}
#[doc = "Field `PHASE_ACTION` reader - Phase action"]
pub type PhaseActionR = crate::FieldReader<PhaseAction>;
impl PhaseActionR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> PhaseAction {
match self.bits {
0 => PhaseAction::Tx,
1 => PhaseAction::DummyTx,
2 => PhaseAction::Rx,
3 => PhaseAction::Poll,
_ => unreachable!(),
}
}
#[doc = "TX"]
#[inline(always)]
pub fn is_tx(&self) -> bool {
*self == PhaseAction::Tx
}
#[doc = "Dummy TX"]
#[inline(always)]
pub fn is_dummy_tx(&self) -> bool {
*self == PhaseAction::DummyTx
}
#[doc = "RX"]
#[inline(always)]
pub fn is_rx(&self) -> bool {
*self == PhaseAction::Rx
}
#[doc = "Poll"]
#[inline(always)]
pub fn is_poll(&self) -> bool {
*self == PhaseAction::Poll
}
}
#[doc = "Field `PHASE_ACTION` writer - Phase action"]
pub type PhaseActionW<'a, REG> = crate::FieldWriter<'a, REG, 2, PhaseAction, crate::Safe>;
impl<'a, REG> PhaseActionW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "TX"]
#[inline(always)]
pub fn tx(self) -> &'a mut crate::W<REG> {
self.variant(PhaseAction::Tx)
}
#[doc = "Dummy TX"]
#[inline(always)]
pub fn dummy_tx(self) -> &'a mut crate::W<REG> {
self.variant(PhaseAction::DummyTx)
}
#[doc = "RX"]
#[inline(always)]
pub fn rx(self) -> &'a mut crate::W<REG> {
self.variant(PhaseAction::Rx)
}
#[doc = "Poll"]
#[inline(always)]
pub fn poll(self) -> &'a mut crate::W<REG> {
self.variant(PhaseAction::Poll)
}
}
#[doc = "Field `BYTE_CNT` reader - Phase byte count"]
pub type ByteCntR = crate::FieldReader<u16>;
#[doc = "Field `BYTE_CNT` writer - Phase byte count"]
pub type ByteCntW<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
#[doc = "SPI mode\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum SpiMode {
#[doc = "0: Single"]
Single = 0,
#[doc = "1: Dual"]
Dual = 1,
#[doc = "2: Quad"]
Quad = 2,
}
impl From<SpiMode> for u8 {
#[inline(always)]
fn from(variant: SpiMode) -> Self {
variant as _
}
}
impl crate::FieldSpec for SpiMode {
type Ux = u8;
}
impl crate::IsEnum for SpiMode {}
#[doc = "Field `SPI_MODE` reader - SPI mode"]
pub type SpiModeR = crate::FieldReader<SpiMode>;
impl SpiModeR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<SpiMode> {
match self.bits {
0 => Some(SpiMode::Single),
1 => Some(SpiMode::Dual),
2 => Some(SpiMode::Quad),
_ => None,
}
}
#[doc = "Single"]
#[inline(always)]
pub fn is_single(&self) -> bool {
*self == SpiMode::Single
}
#[doc = "Dual"]
#[inline(always)]
pub fn is_dual(&self) -> bool {
*self == SpiMode::Dual
}
#[doc = "Quad"]
#[inline(always)]
pub fn is_quad(&self) -> bool {
*self == SpiMode::Quad
}
}
#[doc = "Field `SPI_MODE` writer - SPI mode"]
pub type SpiModeW<'a, REG> = crate::FieldWriter<'a, REG, 2, SpiMode>;
impl<'a, REG> SpiModeW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Single"]
#[inline(always)]
pub fn single(self) -> &'a mut crate::W<REG> {
self.variant(SpiMode::Single)
}
#[doc = "Dual"]
#[inline(always)]
pub fn dual(self) -> &'a mut crate::W<REG> {
self.variant(SpiMode::Dual)
}
#[doc = "Quad"]
#[inline(always)]
pub fn quad(self) -> &'a mut crate::W<REG> {
self.variant(SpiMode::Quad)
}
}
impl R {
#[doc = "Bit 0 - Phase start"]
#[inline(always)]
pub fn phase_start(&self) -> PhaseStartR {
PhaseStartR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Phase done"]
#[inline(always)]
pub fn phase_done(&self) -> PhaseDoneR {
PhaseDoneR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Phase error"]
#[inline(always)]
pub fn phase_error(&self) -> PhaseErrorR {
PhaseErrorR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bits 4:5 - Phase action"]
#[inline(always)]
pub fn phase_action(&self) -> PhaseActionR {
PhaseActionR::new(((self.bits >> 4) & 3) as u8)
}
#[doc = "Bits 8:19 - Phase byte count"]
#[inline(always)]
pub fn byte_cnt(&self) -> ByteCntR {
ByteCntR::new(((self.bits >> 8) & 0x0fff) as u16)
}
#[doc = "Bits 20:21 - SPI mode"]
#[inline(always)]
pub fn spi_mode(&self) -> SpiModeR {
SpiModeR::new(((self.bits >> 20) & 3) as u8)
}
}
impl W {
#[doc = "Bits 4:5 - Phase action"]
#[inline(always)]
pub fn phase_action(&mut self) -> PhaseActionW<PhaseCtrl7Spec> {
PhaseActionW::new(self, 4)
}
#[doc = "Bits 8:19 - Phase byte count"]
#[inline(always)]
pub fn byte_cnt(&mut self) -> ByteCntW<PhaseCtrl7Spec> {
ByteCntW::new(self, 8)
}
#[doc = "Bits 20:21 - SPI mode"]
#[inline(always)]
pub fn spi_mode(&mut self) -> SpiModeW<PhaseCtrl7Spec> {
SpiModeW::new(self, 20)
}
}
#[doc = "Phase control 7\n\nYou can [`read`](crate::Reg::read) this register and get [`phase_ctrl7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`phase_ctrl7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PhaseCtrl7Spec;
impl crate::RegisterSpec for PhaseCtrl7Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`phase_ctrl7::R`](R) reader structure"]
impl crate::Readable for PhaseCtrl7Spec {}
#[doc = "`write(|w| ..)` method takes [`phase_ctrl7::W`](W) writer structure"]
impl crate::Writable for PhaseCtrl7Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets PHASE_CTRL[7] to value 0"]
impl crate::Resettable for PhaseCtrl7Spec {}
}
#[doc = "PHASE_DATA[0] (rw) register accessor: Phase data 0\n\nYou can [`read`](crate::Reg::read) this register and get [`phase_data0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`phase_data0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@phase_data0`] module"]
#[doc(alias = "PHASE_DATA[0]")]
pub type PhaseData0 = crate::Reg<phase_data0::PhaseData0Spec>;
#[doc = "Phase data 0"]
pub mod phase_data0 {
#[doc = "Register `PHASE_DATA[0]` reader"]
pub type R = crate::R<PhaseData0Spec>;
#[doc = "Register `PHASE_DATA[0]` writer"]
pub type W = crate::W<PhaseData0Spec>;
#[doc = "Field `POLL_READ` reader - Poll read value"]
pub type PollReadR = crate::FieldReader;
#[doc = "Field `POLL_READ` writer - Poll read value"]
pub type PollReadW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `POLL_EXPECT` reader - Poll expected value"]
pub type PollExpectR = crate::FieldReader;
#[doc = "Field `POLL_EXPECT` writer - Poll expected value"]
pub type PollExpectW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `POLL_MASK` reader - Poll mask"]
pub type PollMaskR = crate::FieldReader;
#[doc = "Field `POLL_MASK` writer - Poll mask"]
pub type PollMaskW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `POLL_LIMIT` reader - Poll limit"]
pub type PollLimitR = crate::FieldReader;
#[doc = "Field `POLL_LIMIT` writer - Poll limit"]
pub type PollLimitW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:7 - Poll read value"]
#[inline(always)]
pub fn poll_read(&self) -> PollReadR {
PollReadR::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:15 - Poll expected value"]
#[inline(always)]
pub fn poll_expect(&self) -> PollExpectR {
PollExpectR::new(((self.bits >> 8) & 0xff) as u8)
}
#[doc = "Bits 16:23 - Poll mask"]
#[inline(always)]
pub fn poll_mask(&self) -> PollMaskR {
PollMaskR::new(((self.bits >> 16) & 0xff) as u8)
}
#[doc = "Bits 24:31 - Poll limit"]
#[inline(always)]
pub fn poll_limit(&self) -> PollLimitR {
PollLimitR::new(((self.bits >> 24) & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:7 - Poll read value"]
#[inline(always)]
pub fn poll_read(&mut self) -> PollReadW<PhaseData0Spec> {
PollReadW::new(self, 0)
}
#[doc = "Bits 8:15 - Poll expected value"]
#[inline(always)]
pub fn poll_expect(&mut self) -> PollExpectW<PhaseData0Spec> {
PollExpectW::new(self, 8)
}
#[doc = "Bits 16:23 - Poll mask"]
#[inline(always)]
pub fn poll_mask(&mut self) -> PollMaskW<PhaseData0Spec> {
PollMaskW::new(self, 16)
}
#[doc = "Bits 24:31 - Poll limit"]
#[inline(always)]
pub fn poll_limit(&mut self) -> PollLimitW<PhaseData0Spec> {
PollLimitW::new(self, 24)
}
}
#[doc = "Phase data 0\n\nYou can [`read`](crate::Reg::read) this register and get [`phase_data0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`phase_data0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PhaseData0Spec;
impl crate::RegisterSpec for PhaseData0Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`phase_data0::R`](R) reader structure"]
impl crate::Readable for PhaseData0Spec {}
#[doc = "`write(|w| ..)` method takes [`phase_data0::W`](W) writer structure"]
impl crate::Writable for PhaseData0Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets PHASE_DATA[0] to value 0"]
impl crate::Resettable for PhaseData0Spec {}
}
#[doc = "PHASE_DATA[1] (rw) register accessor: Phase data 1\n\nYou can [`read`](crate::Reg::read) this register and get [`phase_data1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`phase_data1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@phase_data1`] module"]
#[doc(alias = "PHASE_DATA[1]")]
pub type PhaseData1 = crate::Reg<phase_data1::PhaseData1Spec>;
#[doc = "Phase data 1"]
pub mod phase_data1 {
#[doc = "Register `PHASE_DATA[1]` reader"]
pub type R = crate::R<PhaseData1Spec>;
#[doc = "Register `PHASE_DATA[1]` writer"]
pub type W = crate::W<PhaseData1Spec>;
#[doc = "Field `POLL_READ` reader - Poll read value"]
pub type PollReadR = crate::FieldReader;
#[doc = "Field `POLL_READ` writer - Poll read value"]
pub type PollReadW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `POLL_EXPECT` reader - Poll expected value"]
pub type PollExpectR = crate::FieldReader;
#[doc = "Field `POLL_EXPECT` writer - Poll expected value"]
pub type PollExpectW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `POLL_MASK` reader - Poll mask"]
pub type PollMaskR = crate::FieldReader;
#[doc = "Field `POLL_MASK` writer - Poll mask"]
pub type PollMaskW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `POLL_LIMIT` reader - Poll limit"]
pub type PollLimitR = crate::FieldReader;
#[doc = "Field `POLL_LIMIT` writer - Poll limit"]
pub type PollLimitW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:7 - Poll read value"]
#[inline(always)]
pub fn poll_read(&self) -> PollReadR {
PollReadR::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:15 - Poll expected value"]
#[inline(always)]
pub fn poll_expect(&self) -> PollExpectR {
PollExpectR::new(((self.bits >> 8) & 0xff) as u8)
}
#[doc = "Bits 16:23 - Poll mask"]
#[inline(always)]
pub fn poll_mask(&self) -> PollMaskR {
PollMaskR::new(((self.bits >> 16) & 0xff) as u8)
}
#[doc = "Bits 24:31 - Poll limit"]
#[inline(always)]
pub fn poll_limit(&self) -> PollLimitR {
PollLimitR::new(((self.bits >> 24) & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:7 - Poll read value"]
#[inline(always)]
pub fn poll_read(&mut self) -> PollReadW<PhaseData1Spec> {
PollReadW::new(self, 0)
}
#[doc = "Bits 8:15 - Poll expected value"]
#[inline(always)]
pub fn poll_expect(&mut self) -> PollExpectW<PhaseData1Spec> {
PollExpectW::new(self, 8)
}
#[doc = "Bits 16:23 - Poll mask"]
#[inline(always)]
pub fn poll_mask(&mut self) -> PollMaskW<PhaseData1Spec> {
PollMaskW::new(self, 16)
}
#[doc = "Bits 24:31 - Poll limit"]
#[inline(always)]
pub fn poll_limit(&mut self) -> PollLimitW<PhaseData1Spec> {
PollLimitW::new(self, 24)
}
}
#[doc = "Phase data 1\n\nYou can [`read`](crate::Reg::read) this register and get [`phase_data1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`phase_data1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PhaseData1Spec;
impl crate::RegisterSpec for PhaseData1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`phase_data1::R`](R) reader structure"]
impl crate::Readable for PhaseData1Spec {}
#[doc = "`write(|w| ..)` method takes [`phase_data1::W`](W) writer structure"]
impl crate::Writable for PhaseData1Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets PHASE_DATA[1] to value 0"]
impl crate::Resettable for PhaseData1Spec {}
}
#[doc = "PHASE_DATA[2] (rw) register accessor: Phase data 2\n\nYou can [`read`](crate::Reg::read) this register and get [`phase_data2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`phase_data2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@phase_data2`] module"]
#[doc(alias = "PHASE_DATA[2]")]
pub type PhaseData2 = crate::Reg<phase_data2::PhaseData2Spec>;
#[doc = "Phase data 2"]
pub mod phase_data2 {
#[doc = "Register `PHASE_DATA[2]` reader"]
pub type R = crate::R<PhaseData2Spec>;
#[doc = "Register `PHASE_DATA[2]` writer"]
pub type W = crate::W<PhaseData2Spec>;
#[doc = "Field `POLL_READ` reader - Poll read value"]
pub type PollReadR = crate::FieldReader;
#[doc = "Field `POLL_READ` writer - Poll read value"]
pub type PollReadW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `POLL_EXPECT` reader - Poll expected value"]
pub type PollExpectR = crate::FieldReader;
#[doc = "Field `POLL_EXPECT` writer - Poll expected value"]
pub type PollExpectW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `POLL_MASK` reader - Poll mask"]
pub type PollMaskR = crate::FieldReader;
#[doc = "Field `POLL_MASK` writer - Poll mask"]
pub type PollMaskW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `POLL_LIMIT` reader - Poll limit"]
pub type PollLimitR = crate::FieldReader;
#[doc = "Field `POLL_LIMIT` writer - Poll limit"]
pub type PollLimitW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:7 - Poll read value"]
#[inline(always)]
pub fn poll_read(&self) -> PollReadR {
PollReadR::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:15 - Poll expected value"]
#[inline(always)]
pub fn poll_expect(&self) -> PollExpectR {
PollExpectR::new(((self.bits >> 8) & 0xff) as u8)
}
#[doc = "Bits 16:23 - Poll mask"]
#[inline(always)]
pub fn poll_mask(&self) -> PollMaskR {
PollMaskR::new(((self.bits >> 16) & 0xff) as u8)
}
#[doc = "Bits 24:31 - Poll limit"]
#[inline(always)]
pub fn poll_limit(&self) -> PollLimitR {
PollLimitR::new(((self.bits >> 24) & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:7 - Poll read value"]
#[inline(always)]
pub fn poll_read(&mut self) -> PollReadW<PhaseData2Spec> {
PollReadW::new(self, 0)
}
#[doc = "Bits 8:15 - Poll expected value"]
#[inline(always)]
pub fn poll_expect(&mut self) -> PollExpectW<PhaseData2Spec> {
PollExpectW::new(self, 8)
}
#[doc = "Bits 16:23 - Poll mask"]
#[inline(always)]
pub fn poll_mask(&mut self) -> PollMaskW<PhaseData2Spec> {
PollMaskW::new(self, 16)
}
#[doc = "Bits 24:31 - Poll limit"]
#[inline(always)]
pub fn poll_limit(&mut self) -> PollLimitW<PhaseData2Spec> {
PollLimitW::new(self, 24)
}
}
#[doc = "Phase data 2\n\nYou can [`read`](crate::Reg::read) this register and get [`phase_data2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`phase_data2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PhaseData2Spec;
impl crate::RegisterSpec for PhaseData2Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`phase_data2::R`](R) reader structure"]
impl crate::Readable for PhaseData2Spec {}
#[doc = "`write(|w| ..)` method takes [`phase_data2::W`](W) writer structure"]
impl crate::Writable for PhaseData2Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets PHASE_DATA[2] to value 0"]
impl crate::Resettable for PhaseData2Spec {}
}
#[doc = "PHASE_DATA[3] (rw) register accessor: Phase data 3\n\nYou can [`read`](crate::Reg::read) this register and get [`phase_data3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`phase_data3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@phase_data3`] module"]
#[doc(alias = "PHASE_DATA[3]")]
pub type PhaseData3 = crate::Reg<phase_data3::PhaseData3Spec>;
#[doc = "Phase data 3"]
pub mod phase_data3 {
#[doc = "Register `PHASE_DATA[3]` reader"]
pub type R = crate::R<PhaseData3Spec>;
#[doc = "Register `PHASE_DATA[3]` writer"]
pub type W = crate::W<PhaseData3Spec>;
#[doc = "Field `POLL_READ` reader - Poll read value"]
pub type PollReadR = crate::FieldReader;
#[doc = "Field `POLL_READ` writer - Poll read value"]
pub type PollReadW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `POLL_EXPECT` reader - Poll expected value"]
pub type PollExpectR = crate::FieldReader;
#[doc = "Field `POLL_EXPECT` writer - Poll expected value"]
pub type PollExpectW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `POLL_MASK` reader - Poll mask"]
pub type PollMaskR = crate::FieldReader;
#[doc = "Field `POLL_MASK` writer - Poll mask"]
pub type PollMaskW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `POLL_LIMIT` reader - Poll limit"]
pub type PollLimitR = crate::FieldReader;
#[doc = "Field `POLL_LIMIT` writer - Poll limit"]
pub type PollLimitW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:7 - Poll read value"]
#[inline(always)]
pub fn poll_read(&self) -> PollReadR {
PollReadR::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:15 - Poll expected value"]
#[inline(always)]
pub fn poll_expect(&self) -> PollExpectR {
PollExpectR::new(((self.bits >> 8) & 0xff) as u8)
}
#[doc = "Bits 16:23 - Poll mask"]
#[inline(always)]
pub fn poll_mask(&self) -> PollMaskR {
PollMaskR::new(((self.bits >> 16) & 0xff) as u8)
}
#[doc = "Bits 24:31 - Poll limit"]
#[inline(always)]
pub fn poll_limit(&self) -> PollLimitR {
PollLimitR::new(((self.bits >> 24) & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:7 - Poll read value"]
#[inline(always)]
pub fn poll_read(&mut self) -> PollReadW<PhaseData3Spec> {
PollReadW::new(self, 0)
}
#[doc = "Bits 8:15 - Poll expected value"]
#[inline(always)]
pub fn poll_expect(&mut self) -> PollExpectW<PhaseData3Spec> {
PollExpectW::new(self, 8)
}
#[doc = "Bits 16:23 - Poll mask"]
#[inline(always)]
pub fn poll_mask(&mut self) -> PollMaskW<PhaseData3Spec> {
PollMaskW::new(self, 16)
}
#[doc = "Bits 24:31 - Poll limit"]
#[inline(always)]
pub fn poll_limit(&mut self) -> PollLimitW<PhaseData3Spec> {
PollLimitW::new(self, 24)
}
}
#[doc = "Phase data 3\n\nYou can [`read`](crate::Reg::read) this register and get [`phase_data3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`phase_data3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PhaseData3Spec;
impl crate::RegisterSpec for PhaseData3Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`phase_data3::R`](R) reader structure"]
impl crate::Readable for PhaseData3Spec {}
#[doc = "`write(|w| ..)` method takes [`phase_data3::W`](W) writer structure"]
impl crate::Writable for PhaseData3Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets PHASE_DATA[3] to value 0"]
impl crate::Resettable for PhaseData3Spec {}
}
#[doc = "PHASE_DATA[4] (rw) register accessor: Phase data 4\n\nYou can [`read`](crate::Reg::read) this register and get [`phase_data4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`phase_data4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@phase_data4`] module"]
#[doc(alias = "PHASE_DATA[4]")]
pub type PhaseData4 = crate::Reg<phase_data4::PhaseData4Spec>;
#[doc = "Phase data 4"]
pub mod phase_data4 {
#[doc = "Register `PHASE_DATA[4]` reader"]
pub type R = crate::R<PhaseData4Spec>;
#[doc = "Register `PHASE_DATA[4]` writer"]
pub type W = crate::W<PhaseData4Spec>;
#[doc = "Field `POLL_READ` reader - Poll read value"]
pub type PollReadR = crate::FieldReader;
#[doc = "Field `POLL_READ` writer - Poll read value"]
pub type PollReadW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `POLL_EXPECT` reader - Poll expected value"]
pub type PollExpectR = crate::FieldReader;
#[doc = "Field `POLL_EXPECT` writer - Poll expected value"]
pub type PollExpectW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `POLL_MASK` reader - Poll mask"]
pub type PollMaskR = crate::FieldReader;
#[doc = "Field `POLL_MASK` writer - Poll mask"]
pub type PollMaskW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `POLL_LIMIT` reader - Poll limit"]
pub type PollLimitR = crate::FieldReader;
#[doc = "Field `POLL_LIMIT` writer - Poll limit"]
pub type PollLimitW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:7 - Poll read value"]
#[inline(always)]
pub fn poll_read(&self) -> PollReadR {
PollReadR::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:15 - Poll expected value"]
#[inline(always)]
pub fn poll_expect(&self) -> PollExpectR {
PollExpectR::new(((self.bits >> 8) & 0xff) as u8)
}
#[doc = "Bits 16:23 - Poll mask"]
#[inline(always)]
pub fn poll_mask(&self) -> PollMaskR {
PollMaskR::new(((self.bits >> 16) & 0xff) as u8)
}
#[doc = "Bits 24:31 - Poll limit"]
#[inline(always)]
pub fn poll_limit(&self) -> PollLimitR {
PollLimitR::new(((self.bits >> 24) & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:7 - Poll read value"]
#[inline(always)]
pub fn poll_read(&mut self) -> PollReadW<PhaseData4Spec> {
PollReadW::new(self, 0)
}
#[doc = "Bits 8:15 - Poll expected value"]
#[inline(always)]
pub fn poll_expect(&mut self) -> PollExpectW<PhaseData4Spec> {
PollExpectW::new(self, 8)
}
#[doc = "Bits 16:23 - Poll mask"]
#[inline(always)]
pub fn poll_mask(&mut self) -> PollMaskW<PhaseData4Spec> {
PollMaskW::new(self, 16)
}
#[doc = "Bits 24:31 - Poll limit"]
#[inline(always)]
pub fn poll_limit(&mut self) -> PollLimitW<PhaseData4Spec> {
PollLimitW::new(self, 24)
}
}
#[doc = "Phase data 4\n\nYou can [`read`](crate::Reg::read) this register and get [`phase_data4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`phase_data4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PhaseData4Spec;
impl crate::RegisterSpec for PhaseData4Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`phase_data4::R`](R) reader structure"]
impl crate::Readable for PhaseData4Spec {}
#[doc = "`write(|w| ..)` method takes [`phase_data4::W`](W) writer structure"]
impl crate::Writable for PhaseData4Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets PHASE_DATA[4] to value 0"]
impl crate::Resettable for PhaseData4Spec {}
}
#[doc = "PHASE_DATA[5] (rw) register accessor: Phase data 5\n\nYou can [`read`](crate::Reg::read) this register and get [`phase_data5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`phase_data5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@phase_data5`] module"]
#[doc(alias = "PHASE_DATA[5]")]
pub type PhaseData5 = crate::Reg<phase_data5::PhaseData5Spec>;
#[doc = "Phase data 5"]
pub mod phase_data5 {
#[doc = "Register `PHASE_DATA[5]` reader"]
pub type R = crate::R<PhaseData5Spec>;
#[doc = "Register `PHASE_DATA[5]` writer"]
pub type W = crate::W<PhaseData5Spec>;
#[doc = "Field `POLL_READ` reader - Poll read value"]
pub type PollReadR = crate::FieldReader;
#[doc = "Field `POLL_READ` writer - Poll read value"]
pub type PollReadW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `POLL_EXPECT` reader - Poll expected value"]
pub type PollExpectR = crate::FieldReader;
#[doc = "Field `POLL_EXPECT` writer - Poll expected value"]
pub type PollExpectW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `POLL_MASK` reader - Poll mask"]
pub type PollMaskR = crate::FieldReader;
#[doc = "Field `POLL_MASK` writer - Poll mask"]
pub type PollMaskW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `POLL_LIMIT` reader - Poll limit"]
pub type PollLimitR = crate::FieldReader;
#[doc = "Field `POLL_LIMIT` writer - Poll limit"]
pub type PollLimitW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:7 - Poll read value"]
#[inline(always)]
pub fn poll_read(&self) -> PollReadR {
PollReadR::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:15 - Poll expected value"]
#[inline(always)]
pub fn poll_expect(&self) -> PollExpectR {
PollExpectR::new(((self.bits >> 8) & 0xff) as u8)
}
#[doc = "Bits 16:23 - Poll mask"]
#[inline(always)]
pub fn poll_mask(&self) -> PollMaskR {
PollMaskR::new(((self.bits >> 16) & 0xff) as u8)
}
#[doc = "Bits 24:31 - Poll limit"]
#[inline(always)]
pub fn poll_limit(&self) -> PollLimitR {
PollLimitR::new(((self.bits >> 24) & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:7 - Poll read value"]
#[inline(always)]
pub fn poll_read(&mut self) -> PollReadW<PhaseData5Spec> {
PollReadW::new(self, 0)
}
#[doc = "Bits 8:15 - Poll expected value"]
#[inline(always)]
pub fn poll_expect(&mut self) -> PollExpectW<PhaseData5Spec> {
PollExpectW::new(self, 8)
}
#[doc = "Bits 16:23 - Poll mask"]
#[inline(always)]
pub fn poll_mask(&mut self) -> PollMaskW<PhaseData5Spec> {
PollMaskW::new(self, 16)
}
#[doc = "Bits 24:31 - Poll limit"]
#[inline(always)]
pub fn poll_limit(&mut self) -> PollLimitW<PhaseData5Spec> {
PollLimitW::new(self, 24)
}
}
#[doc = "Phase data 5\n\nYou can [`read`](crate::Reg::read) this register and get [`phase_data5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`phase_data5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PhaseData5Spec;
impl crate::RegisterSpec for PhaseData5Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`phase_data5::R`](R) reader structure"]
impl crate::Readable for PhaseData5Spec {}
#[doc = "`write(|w| ..)` method takes [`phase_data5::W`](W) writer structure"]
impl crate::Writable for PhaseData5Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets PHASE_DATA[5] to value 0"]
impl crate::Resettable for PhaseData5Spec {}
}
#[doc = "PHASE_DATA[6] (rw) register accessor: Phase data 6\n\nYou can [`read`](crate::Reg::read) this register and get [`phase_data6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`phase_data6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@phase_data6`] module"]
#[doc(alias = "PHASE_DATA[6]")]
pub type PhaseData6 = crate::Reg<phase_data6::PhaseData6Spec>;
#[doc = "Phase data 6"]
pub mod phase_data6 {
#[doc = "Register `PHASE_DATA[6]` reader"]
pub type R = crate::R<PhaseData6Spec>;
#[doc = "Register `PHASE_DATA[6]` writer"]
pub type W = crate::W<PhaseData6Spec>;
#[doc = "Field `POLL_READ` reader - Poll read value"]
pub type PollReadR = crate::FieldReader;
#[doc = "Field `POLL_READ` writer - Poll read value"]
pub type PollReadW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `POLL_EXPECT` reader - Poll expected value"]
pub type PollExpectR = crate::FieldReader;
#[doc = "Field `POLL_EXPECT` writer - Poll expected value"]
pub type PollExpectW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `POLL_MASK` reader - Poll mask"]
pub type PollMaskR = crate::FieldReader;
#[doc = "Field `POLL_MASK` writer - Poll mask"]
pub type PollMaskW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `POLL_LIMIT` reader - Poll limit"]
pub type PollLimitR = crate::FieldReader;
#[doc = "Field `POLL_LIMIT` writer - Poll limit"]
pub type PollLimitW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:7 - Poll read value"]
#[inline(always)]
pub fn poll_read(&self) -> PollReadR {
PollReadR::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:15 - Poll expected value"]
#[inline(always)]
pub fn poll_expect(&self) -> PollExpectR {
PollExpectR::new(((self.bits >> 8) & 0xff) as u8)
}
#[doc = "Bits 16:23 - Poll mask"]
#[inline(always)]
pub fn poll_mask(&self) -> PollMaskR {
PollMaskR::new(((self.bits >> 16) & 0xff) as u8)
}
#[doc = "Bits 24:31 - Poll limit"]
#[inline(always)]
pub fn poll_limit(&self) -> PollLimitR {
PollLimitR::new(((self.bits >> 24) & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:7 - Poll read value"]
#[inline(always)]
pub fn poll_read(&mut self) -> PollReadW<PhaseData6Spec> {
PollReadW::new(self, 0)
}
#[doc = "Bits 8:15 - Poll expected value"]
#[inline(always)]
pub fn poll_expect(&mut self) -> PollExpectW<PhaseData6Spec> {
PollExpectW::new(self, 8)
}
#[doc = "Bits 16:23 - Poll mask"]
#[inline(always)]
pub fn poll_mask(&mut self) -> PollMaskW<PhaseData6Spec> {
PollMaskW::new(self, 16)
}
#[doc = "Bits 24:31 - Poll limit"]
#[inline(always)]
pub fn poll_limit(&mut self) -> PollLimitW<PhaseData6Spec> {
PollLimitW::new(self, 24)
}
}
#[doc = "Phase data 6\n\nYou can [`read`](crate::Reg::read) this register and get [`phase_data6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`phase_data6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PhaseData6Spec;
impl crate::RegisterSpec for PhaseData6Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`phase_data6::R`](R) reader structure"]
impl crate::Readable for PhaseData6Spec {}
#[doc = "`write(|w| ..)` method takes [`phase_data6::W`](W) writer structure"]
impl crate::Writable for PhaseData6Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets PHASE_DATA[6] to value 0"]
impl crate::Resettable for PhaseData6Spec {}
}
#[doc = "PHASE_DATA[7] (rw) register accessor: Phase data 7\n\nYou can [`read`](crate::Reg::read) this register and get [`phase_data7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`phase_data7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@phase_data7`] module"]
#[doc(alias = "PHASE_DATA[7]")]
pub type PhaseData7 = crate::Reg<phase_data7::PhaseData7Spec>;
#[doc = "Phase data 7"]
pub mod phase_data7 {
#[doc = "Register `PHASE_DATA[7]` reader"]
pub type R = crate::R<PhaseData7Spec>;
#[doc = "Register `PHASE_DATA[7]` writer"]
pub type W = crate::W<PhaseData7Spec>;
#[doc = "Field `POLL_READ` reader - Poll read value"]
pub type PollReadR = crate::FieldReader;
#[doc = "Field `POLL_READ` writer - Poll read value"]
pub type PollReadW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `POLL_EXPECT` reader - Poll expected value"]
pub type PollExpectR = crate::FieldReader;
#[doc = "Field `POLL_EXPECT` writer - Poll expected value"]
pub type PollExpectW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `POLL_MASK` reader - Poll mask"]
pub type PollMaskR = crate::FieldReader;
#[doc = "Field `POLL_MASK` writer - Poll mask"]
pub type PollMaskW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `POLL_LIMIT` reader - Poll limit"]
pub type PollLimitR = crate::FieldReader;
#[doc = "Field `POLL_LIMIT` writer - Poll limit"]
pub type PollLimitW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:7 - Poll read value"]
#[inline(always)]
pub fn poll_read(&self) -> PollReadR {
PollReadR::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:15 - Poll expected value"]
#[inline(always)]
pub fn poll_expect(&self) -> PollExpectR {
PollExpectR::new(((self.bits >> 8) & 0xff) as u8)
}
#[doc = "Bits 16:23 - Poll mask"]
#[inline(always)]
pub fn poll_mask(&self) -> PollMaskR {
PollMaskR::new(((self.bits >> 16) & 0xff) as u8)
}
#[doc = "Bits 24:31 - Poll limit"]
#[inline(always)]
pub fn poll_limit(&self) -> PollLimitR {
PollLimitR::new(((self.bits >> 24) & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:7 - Poll read value"]
#[inline(always)]
pub fn poll_read(&mut self) -> PollReadW<PhaseData7Spec> {
PollReadW::new(self, 0)
}
#[doc = "Bits 8:15 - Poll expected value"]
#[inline(always)]
pub fn poll_expect(&mut self) -> PollExpectW<PhaseData7Spec> {
PollExpectW::new(self, 8)
}
#[doc = "Bits 16:23 - Poll mask"]
#[inline(always)]
pub fn poll_mask(&mut self) -> PollMaskW<PhaseData7Spec> {
PollMaskW::new(self, 16)
}
#[doc = "Bits 24:31 - Poll limit"]
#[inline(always)]
pub fn poll_limit(&mut self) -> PollLimitW<PhaseData7Spec> {
PollLimitW::new(self, 24)
}
}
#[doc = "Phase data 7\n\nYou can [`read`](crate::Reg::read) this register and get [`phase_data7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`phase_data7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PhaseData7Spec;
impl crate::RegisterSpec for PhaseData7Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`phase_data7::R`](R) reader structure"]
impl crate::Readable for PhaseData7Spec {}
#[doc = "`write(|w| ..)` method takes [`phase_data7::W`](W) writer structure"]
impl crate::Writable for PhaseData7Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets PHASE_DATA[7] to value 0"]
impl crate::Resettable for PhaseData7Spec {}
}
}
#[doc = "SPI registers"]
pub type Spi1 = crate::Periph<spi0::RegisterBlock, 0x4001_3000>;
impl core::fmt::Debug for Spi1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Spi1").finish()
}
}
#[doc = "SPI registers"]
pub use self::spi0 as spi1;
#[doc = "GPIO registers"]
pub type Gpio0 = crate::Periph<gpio0::RegisterBlock, 0x4001_4000>;
impl core::fmt::Debug for Gpio0 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Gpio0").finish()
}
}
#[doc = "GPIO registers"]
pub mod gpio0 {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
_reserved0: [u8; 0x03fc],
data: Data,
dir: Dir,
is: Is,
ibe: Ibe,
iev: Iev,
ie: Ie,
ris: Ris,
mis: Mis,
ic: Ic,
afsel: Afsel,
}
impl RegisterBlock {
#[doc = "0x3fc - Data register"]
#[inline(always)]
pub const fn data(&self) -> &Data {
&self.data
}
#[doc = "0x400 - Data direction register"]
#[inline(always)]
pub const fn dir(&self) -> &Dir {
&self.dir
}
#[doc = "0x404 - Interrupt sense register"]
#[inline(always)]
pub const fn is(&self) -> &Is {
&self.is
}
#[doc = "0x408 - Interrupt both-edges register"]
#[inline(always)]
pub const fn ibe(&self) -> &Ibe {
&self.ibe
}
#[doc = "0x40c - Interrupt event register"]
#[inline(always)]
pub const fn iev(&self) -> &Iev {
&self.iev
}
#[doc = "0x410 - Interrupt mask register"]
#[inline(always)]
pub const fn ie(&self) -> &Ie {
&self.ie
}
#[doc = "0x414 - Raw interrupt status register"]
#[inline(always)]
pub const fn ris(&self) -> &Ris {
&self.ris
}
#[doc = "0x418 - Masked interrupt status register"]
#[inline(always)]
pub const fn mis(&self) -> &Mis {
&self.mis
}
#[doc = "0x41c - Interrupt clear register"]
#[inline(always)]
pub const fn ic(&self) -> &Ic {
&self.ic
}
#[doc = "0x420 - Mode control select register"]
#[inline(always)]
pub const fn afsel(&self) -> &Afsel {
&self.afsel
}
}
#[doc = "DATA (rw) register accessor: Data register\n\nYou can [`read`](crate::Reg::read) this register and get [`data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data`] module"]
#[doc(alias = "DATA")]
pub type Data = crate::Reg<data::DataSpec>;
#[doc = "Data register"]
pub mod data {
#[doc = "Register `DATA` reader"]
pub type R = crate::R<DataSpec>;
#[doc = "Register `DATA` writer"]
pub type W = crate::W<DataSpec>;
#[doc = "Field `DATA0` reader - Data register bit 0"]
pub type Data0R = crate::BitReader;
#[doc = "Field `DATA0` writer - Data register bit 0"]
pub type Data0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DATA1` reader - Data register bit 1"]
pub type Data1R = crate::BitReader;
#[doc = "Field `DATA1` writer - Data register bit 1"]
pub type Data1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DATA2` reader - Data register bit 2"]
pub type Data2R = crate::BitReader;
#[doc = "Field `DATA2` writer - Data register bit 2"]
pub type Data2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DATA3` reader - Data register bit 3"]
pub type Data3R = crate::BitReader;
#[doc = "Field `DATA3` writer - Data register bit 3"]
pub type Data3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DATA4` reader - Data register bit 4"]
pub type Data4R = crate::BitReader;
#[doc = "Field `DATA4` writer - Data register bit 4"]
pub type Data4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DATA5` reader - Data register bit 5"]
pub type Data5R = crate::BitReader;
#[doc = "Field `DATA5` writer - Data register bit 5"]
pub type Data5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DATA6` reader - Data register bit 6"]
pub type Data6R = crate::BitReader;
#[doc = "Field `DATA6` writer - Data register bit 6"]
pub type Data6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DATA7` reader - Data register bit 7"]
pub type Data7R = crate::BitReader;
#[doc = "Field `DATA7` writer - Data register bit 7"]
pub type Data7W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - Data register bit 0"]
#[inline(always)]
pub fn data0(&self) -> Data0R {
Data0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Data register bit 1"]
#[inline(always)]
pub fn data1(&self) -> Data1R {
Data1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Data register bit 2"]
#[inline(always)]
pub fn data2(&self) -> Data2R {
Data2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Data register bit 3"]
#[inline(always)]
pub fn data3(&self) -> Data3R {
Data3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Data register bit 4"]
#[inline(always)]
pub fn data4(&self) -> Data4R {
Data4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Data register bit 5"]
#[inline(always)]
pub fn data5(&self) -> Data5R {
Data5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Data register bit 6"]
#[inline(always)]
pub fn data6(&self) -> Data6R {
Data6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Data register bit 7"]
#[inline(always)]
pub fn data7(&self) -> Data7R {
Data7R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Data register bit 0"]
#[inline(always)]
pub fn data0(&mut self) -> Data0W<DataSpec> {
Data0W::new(self, 0)
}
#[doc = "Bit 1 - Data register bit 1"]
#[inline(always)]
pub fn data1(&mut self) -> Data1W<DataSpec> {
Data1W::new(self, 1)
}
#[doc = "Bit 2 - Data register bit 2"]
#[inline(always)]
pub fn data2(&mut self) -> Data2W<DataSpec> {
Data2W::new(self, 2)
}
#[doc = "Bit 3 - Data register bit 3"]
#[inline(always)]
pub fn data3(&mut self) -> Data3W<DataSpec> {
Data3W::new(self, 3)
}
#[doc = "Bit 4 - Data register bit 4"]
#[inline(always)]
pub fn data4(&mut self) -> Data4W<DataSpec> {
Data4W::new(self, 4)
}
#[doc = "Bit 5 - Data register bit 5"]
#[inline(always)]
pub fn data5(&mut self) -> Data5W<DataSpec> {
Data5W::new(self, 5)
}
#[doc = "Bit 6 - Data register bit 6"]
#[inline(always)]
pub fn data6(&mut self) -> Data6W<DataSpec> {
Data6W::new(self, 6)
}
#[doc = "Bit 7 - Data register bit 7"]
#[inline(always)]
pub fn data7(&mut self) -> Data7W<DataSpec> {
Data7W::new(self, 7)
}
}
#[doc = "Data register\n\nYou can [`read`](crate::Reg::read) this register and get [`data::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DataSpec;
impl crate::RegisterSpec for DataSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`data::R`](R) reader structure"]
impl crate::Readable for DataSpec {}
#[doc = "`write(|w| ..)` method takes [`data::W`](W) writer structure"]
impl crate::Writable for DataSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets DATA to value 0"]
impl crate::Resettable for DataSpec {}
}
#[doc = "DIR (rw) register accessor: Data direction register\n\nYou can [`read`](crate::Reg::read) this register and get [`dir::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dir::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dir`] module"]
#[doc(alias = "DIR")]
pub type Dir = crate::Reg<dir::DirSpec>;
#[doc = "Data direction register"]
pub mod dir {
#[doc = "Register `DIR` reader"]
pub type R = crate::R<DirSpec>;
#[doc = "Register `DIR` writer"]
pub type W = crate::W<DirSpec>;
#[doc = "Data direction bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Dir0 {
#[doc = "0: Input"]
Input = 0,
#[doc = "1: Output"]
Output = 1,
}
impl From<Dir0> for bool {
#[inline(always)]
fn from(variant: Dir0) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `DIR0` reader - Data direction bit 0"]
pub type Dir0R = crate::BitReader<Dir0>;
impl Dir0R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Dir0 {
match self.bits {
false => Dir0::Input,
true => Dir0::Output,
}
}
#[doc = "Input"]
#[inline(always)]
pub fn is_input(&self) -> bool {
*self == Dir0::Input
}
#[doc = "Output"]
#[inline(always)]
pub fn is_output(&self) -> bool {
*self == Dir0::Output
}
}
#[doc = "Field `DIR0` writer - Data direction bit 0"]
pub type Dir0W<'a, REG> = crate::BitWriter<'a, REG, Dir0>;
impl<'a, REG> Dir0W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Input"]
#[inline(always)]
pub fn input(self) -> &'a mut crate::W<REG> {
self.variant(Dir0::Input)
}
#[doc = "Output"]
#[inline(always)]
pub fn output(self) -> &'a mut crate::W<REG> {
self.variant(Dir0::Output)
}
}
#[doc = "Data direction bit 1\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Dir1 {
#[doc = "0: Input"]
Input = 0,
#[doc = "1: Output"]
Output = 1,
}
impl From<Dir1> for bool {
#[inline(always)]
fn from(variant: Dir1) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `DIR1` reader - Data direction bit 1"]
pub type Dir1R = crate::BitReader<Dir1>;
impl Dir1R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Dir1 {
match self.bits {
false => Dir1::Input,
true => Dir1::Output,
}
}
#[doc = "Input"]
#[inline(always)]
pub fn is_input(&self) -> bool {
*self == Dir1::Input
}
#[doc = "Output"]
#[inline(always)]
pub fn is_output(&self) -> bool {
*self == Dir1::Output
}
}
#[doc = "Field `DIR1` writer - Data direction bit 1"]
pub type Dir1W<'a, REG> = crate::BitWriter<'a, REG, Dir1>;
impl<'a, REG> Dir1W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Input"]
#[inline(always)]
pub fn input(self) -> &'a mut crate::W<REG> {
self.variant(Dir1::Input)
}
#[doc = "Output"]
#[inline(always)]
pub fn output(self) -> &'a mut crate::W<REG> {
self.variant(Dir1::Output)
}
}
#[doc = "Data direction bit 2\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Dir2 {
#[doc = "0: Input"]
Input = 0,
#[doc = "1: Output"]
Output = 1,
}
impl From<Dir2> for bool {
#[inline(always)]
fn from(variant: Dir2) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `DIR2` reader - Data direction bit 2"]
pub type Dir2R = crate::BitReader<Dir2>;
impl Dir2R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Dir2 {
match self.bits {
false => Dir2::Input,
true => Dir2::Output,
}
}
#[doc = "Input"]
#[inline(always)]
pub fn is_input(&self) -> bool {
*self == Dir2::Input
}
#[doc = "Output"]
#[inline(always)]
pub fn is_output(&self) -> bool {
*self == Dir2::Output
}
}
#[doc = "Field `DIR2` writer - Data direction bit 2"]
pub type Dir2W<'a, REG> = crate::BitWriter<'a, REG, Dir2>;
impl<'a, REG> Dir2W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Input"]
#[inline(always)]
pub fn input(self) -> &'a mut crate::W<REG> {
self.variant(Dir2::Input)
}
#[doc = "Output"]
#[inline(always)]
pub fn output(self) -> &'a mut crate::W<REG> {
self.variant(Dir2::Output)
}
}
#[doc = "Data direction bit 3\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Dir3 {
#[doc = "0: Input"]
Input = 0,
#[doc = "1: Output"]
Output = 1,
}
impl From<Dir3> for bool {
#[inline(always)]
fn from(variant: Dir3) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `DIR3` reader - Data direction bit 3"]
pub type Dir3R = crate::BitReader<Dir3>;
impl Dir3R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Dir3 {
match self.bits {
false => Dir3::Input,
true => Dir3::Output,
}
}
#[doc = "Input"]
#[inline(always)]
pub fn is_input(&self) -> bool {
*self == Dir3::Input
}
#[doc = "Output"]
#[inline(always)]
pub fn is_output(&self) -> bool {
*self == Dir3::Output
}
}
#[doc = "Field `DIR3` writer - Data direction bit 3"]
pub type Dir3W<'a, REG> = crate::BitWriter<'a, REG, Dir3>;
impl<'a, REG> Dir3W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Input"]
#[inline(always)]
pub fn input(self) -> &'a mut crate::W<REG> {
self.variant(Dir3::Input)
}
#[doc = "Output"]
#[inline(always)]
pub fn output(self) -> &'a mut crate::W<REG> {
self.variant(Dir3::Output)
}
}
#[doc = "Data direction bit 4\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Dir4 {
#[doc = "0: Input"]
Input = 0,
#[doc = "1: Output"]
Output = 1,
}
impl From<Dir4> for bool {
#[inline(always)]
fn from(variant: Dir4) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `DIR4` reader - Data direction bit 4"]
pub type Dir4R = crate::BitReader<Dir4>;
impl Dir4R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Dir4 {
match self.bits {
false => Dir4::Input,
true => Dir4::Output,
}
}
#[doc = "Input"]
#[inline(always)]
pub fn is_input(&self) -> bool {
*self == Dir4::Input
}
#[doc = "Output"]
#[inline(always)]
pub fn is_output(&self) -> bool {
*self == Dir4::Output
}
}
#[doc = "Field `DIR4` writer - Data direction bit 4"]
pub type Dir4W<'a, REG> = crate::BitWriter<'a, REG, Dir4>;
impl<'a, REG> Dir4W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Input"]
#[inline(always)]
pub fn input(self) -> &'a mut crate::W<REG> {
self.variant(Dir4::Input)
}
#[doc = "Output"]
#[inline(always)]
pub fn output(self) -> &'a mut crate::W<REG> {
self.variant(Dir4::Output)
}
}
#[doc = "Data direction bit 5\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Dir5 {
#[doc = "0: Input"]
Input = 0,
#[doc = "1: Output"]
Output = 1,
}
impl From<Dir5> for bool {
#[inline(always)]
fn from(variant: Dir5) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `DIR5` reader - Data direction bit 5"]
pub type Dir5R = crate::BitReader<Dir5>;
impl Dir5R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Dir5 {
match self.bits {
false => Dir5::Input,
true => Dir5::Output,
}
}
#[doc = "Input"]
#[inline(always)]
pub fn is_input(&self) -> bool {
*self == Dir5::Input
}
#[doc = "Output"]
#[inline(always)]
pub fn is_output(&self) -> bool {
*self == Dir5::Output
}
}
#[doc = "Field `DIR5` writer - Data direction bit 5"]
pub type Dir5W<'a, REG> = crate::BitWriter<'a, REG, Dir5>;
impl<'a, REG> Dir5W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Input"]
#[inline(always)]
pub fn input(self) -> &'a mut crate::W<REG> {
self.variant(Dir5::Input)
}
#[doc = "Output"]
#[inline(always)]
pub fn output(self) -> &'a mut crate::W<REG> {
self.variant(Dir5::Output)
}
}
#[doc = "Data direction bit 6\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Dir6 {
#[doc = "0: Input"]
Input = 0,
#[doc = "1: Output"]
Output = 1,
}
impl From<Dir6> for bool {
#[inline(always)]
fn from(variant: Dir6) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `DIR6` reader - Data direction bit 6"]
pub type Dir6R = crate::BitReader<Dir6>;
impl Dir6R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Dir6 {
match self.bits {
false => Dir6::Input,
true => Dir6::Output,
}
}
#[doc = "Input"]
#[inline(always)]
pub fn is_input(&self) -> bool {
*self == Dir6::Input
}
#[doc = "Output"]
#[inline(always)]
pub fn is_output(&self) -> bool {
*self == Dir6::Output
}
}
#[doc = "Field `DIR6` writer - Data direction bit 6"]
pub type Dir6W<'a, REG> = crate::BitWriter<'a, REG, Dir6>;
impl<'a, REG> Dir6W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Input"]
#[inline(always)]
pub fn input(self) -> &'a mut crate::W<REG> {
self.variant(Dir6::Input)
}
#[doc = "Output"]
#[inline(always)]
pub fn output(self) -> &'a mut crate::W<REG> {
self.variant(Dir6::Output)
}
}
#[doc = "Data direction bit 7\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Dir7 {
#[doc = "0: Input"]
Input = 0,
#[doc = "1: Output"]
Output = 1,
}
impl From<Dir7> for bool {
#[inline(always)]
fn from(variant: Dir7) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `DIR7` reader - Data direction bit 7"]
pub type Dir7R = crate::BitReader<Dir7>;
impl Dir7R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Dir7 {
match self.bits {
false => Dir7::Input,
true => Dir7::Output,
}
}
#[doc = "Input"]
#[inline(always)]
pub fn is_input(&self) -> bool {
*self == Dir7::Input
}
#[doc = "Output"]
#[inline(always)]
pub fn is_output(&self) -> bool {
*self == Dir7::Output
}
}
#[doc = "Field `DIR7` writer - Data direction bit 7"]
pub type Dir7W<'a, REG> = crate::BitWriter<'a, REG, Dir7>;
impl<'a, REG> Dir7W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Input"]
#[inline(always)]
pub fn input(self) -> &'a mut crate::W<REG> {
self.variant(Dir7::Input)
}
#[doc = "Output"]
#[inline(always)]
pub fn output(self) -> &'a mut crate::W<REG> {
self.variant(Dir7::Output)
}
}
impl R {
#[doc = "Bit 0 - Data direction bit 0"]
#[inline(always)]
pub fn dir0(&self) -> Dir0R {
Dir0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Data direction bit 1"]
#[inline(always)]
pub fn dir1(&self) -> Dir1R {
Dir1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Data direction bit 2"]
#[inline(always)]
pub fn dir2(&self) -> Dir2R {
Dir2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Data direction bit 3"]
#[inline(always)]
pub fn dir3(&self) -> Dir3R {
Dir3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Data direction bit 4"]
#[inline(always)]
pub fn dir4(&self) -> Dir4R {
Dir4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Data direction bit 5"]
#[inline(always)]
pub fn dir5(&self) -> Dir5R {
Dir5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Data direction bit 6"]
#[inline(always)]
pub fn dir6(&self) -> Dir6R {
Dir6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Data direction bit 7"]
#[inline(always)]
pub fn dir7(&self) -> Dir7R {
Dir7R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Data direction bit 0"]
#[inline(always)]
pub fn dir0(&mut self) -> Dir0W<DirSpec> {
Dir0W::new(self, 0)
}
#[doc = "Bit 1 - Data direction bit 1"]
#[inline(always)]
pub fn dir1(&mut self) -> Dir1W<DirSpec> {
Dir1W::new(self, 1)
}
#[doc = "Bit 2 - Data direction bit 2"]
#[inline(always)]
pub fn dir2(&mut self) -> Dir2W<DirSpec> {
Dir2W::new(self, 2)
}
#[doc = "Bit 3 - Data direction bit 3"]
#[inline(always)]
pub fn dir3(&mut self) -> Dir3W<DirSpec> {
Dir3W::new(self, 3)
}
#[doc = "Bit 4 - Data direction bit 4"]
#[inline(always)]
pub fn dir4(&mut self) -> Dir4W<DirSpec> {
Dir4W::new(self, 4)
}
#[doc = "Bit 5 - Data direction bit 5"]
#[inline(always)]
pub fn dir5(&mut self) -> Dir5W<DirSpec> {
Dir5W::new(self, 5)
}
#[doc = "Bit 6 - Data direction bit 6"]
#[inline(always)]
pub fn dir6(&mut self) -> Dir6W<DirSpec> {
Dir6W::new(self, 6)
}
#[doc = "Bit 7 - Data direction bit 7"]
#[inline(always)]
pub fn dir7(&mut self) -> Dir7W<DirSpec> {
Dir7W::new(self, 7)
}
}
#[doc = "Data direction register\n\nYou can [`read`](crate::Reg::read) this register and get [`dir::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dir::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DirSpec;
impl crate::RegisterSpec for DirSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`dir::R`](R) reader structure"]
impl crate::Readable for DirSpec {}
#[doc = "`write(|w| ..)` method takes [`dir::W`](W) writer structure"]
impl crate::Writable for DirSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets DIR to value 0"]
impl crate::Resettable for DirSpec {}
}
#[doc = "IS (rw) register accessor: Interrupt sense register\n\nYou can [`read`](crate::Reg::read) this register and get [`is::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`is::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@is`] module"]
#[doc(alias = "IS")]
pub type Is = crate::Reg<is::IsSpec>;
#[doc = "Interrupt sense register"]
pub mod is {
#[doc = "Register `IS` reader"]
pub type R = crate::R<IsSpec>;
#[doc = "Register `IS` writer"]
pub type W = crate::W<IsSpec>;
#[doc = "Interrupt sense bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Is0 {
#[doc = "0: Edge"]
Edge = 0,
#[doc = "1: Level"]
Level = 1,
}
impl From<Is0> for bool {
#[inline(always)]
fn from(variant: Is0) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `IS0` reader - Interrupt sense bit 0"]
pub type Is0R = crate::BitReader<Is0>;
impl Is0R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Is0 {
match self.bits {
false => Is0::Edge,
true => Is0::Level,
}
}
#[doc = "Edge"]
#[inline(always)]
pub fn is_edge(&self) -> bool {
*self == Is0::Edge
}
#[doc = "Level"]
#[inline(always)]
pub fn is_level(&self) -> bool {
*self == Is0::Level
}
}
#[doc = "Field `IS0` writer - Interrupt sense bit 0"]
pub type Is0W<'a, REG> = crate::BitWriter<'a, REG, Is0>;
impl<'a, REG> Is0W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Edge"]
#[inline(always)]
pub fn edge(self) -> &'a mut crate::W<REG> {
self.variant(Is0::Edge)
}
#[doc = "Level"]
#[inline(always)]
pub fn level(self) -> &'a mut crate::W<REG> {
self.variant(Is0::Level)
}
}
#[doc = "Interrupt sense bit 1\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Is1 {
#[doc = "0: Edge"]
Edge = 0,
#[doc = "1: Level"]
Level = 1,
}
impl From<Is1> for bool {
#[inline(always)]
fn from(variant: Is1) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `IS1` reader - Interrupt sense bit 1"]
pub type Is1R = crate::BitReader<Is1>;
impl Is1R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Is1 {
match self.bits {
false => Is1::Edge,
true => Is1::Level,
}
}
#[doc = "Edge"]
#[inline(always)]
pub fn is_edge(&self) -> bool {
*self == Is1::Edge
}
#[doc = "Level"]
#[inline(always)]
pub fn is_level(&self) -> bool {
*self == Is1::Level
}
}
#[doc = "Field `IS1` writer - Interrupt sense bit 1"]
pub type Is1W<'a, REG> = crate::BitWriter<'a, REG, Is1>;
impl<'a, REG> Is1W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Edge"]
#[inline(always)]
pub fn edge(self) -> &'a mut crate::W<REG> {
self.variant(Is1::Edge)
}
#[doc = "Level"]
#[inline(always)]
pub fn level(self) -> &'a mut crate::W<REG> {
self.variant(Is1::Level)
}
}
#[doc = "Interrupt sense bit 2\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Is2 {
#[doc = "0: Edge"]
Edge = 0,
#[doc = "1: Level"]
Level = 1,
}
impl From<Is2> for bool {
#[inline(always)]
fn from(variant: Is2) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `IS2` reader - Interrupt sense bit 2"]
pub type Is2R = crate::BitReader<Is2>;
impl Is2R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Is2 {
match self.bits {
false => Is2::Edge,
true => Is2::Level,
}
}
#[doc = "Edge"]
#[inline(always)]
pub fn is_edge(&self) -> bool {
*self == Is2::Edge
}
#[doc = "Level"]
#[inline(always)]
pub fn is_level(&self) -> bool {
*self == Is2::Level
}
}
#[doc = "Field `IS2` writer - Interrupt sense bit 2"]
pub type Is2W<'a, REG> = crate::BitWriter<'a, REG, Is2>;
impl<'a, REG> Is2W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Edge"]
#[inline(always)]
pub fn edge(self) -> &'a mut crate::W<REG> {
self.variant(Is2::Edge)
}
#[doc = "Level"]
#[inline(always)]
pub fn level(self) -> &'a mut crate::W<REG> {
self.variant(Is2::Level)
}
}
#[doc = "Interrupt sense bit 3\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Is3 {
#[doc = "0: Edge"]
Edge = 0,
#[doc = "1: Level"]
Level = 1,
}
impl From<Is3> for bool {
#[inline(always)]
fn from(variant: Is3) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `IS3` reader - Interrupt sense bit 3"]
pub type Is3R = crate::BitReader<Is3>;
impl Is3R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Is3 {
match self.bits {
false => Is3::Edge,
true => Is3::Level,
}
}
#[doc = "Edge"]
#[inline(always)]
pub fn is_edge(&self) -> bool {
*self == Is3::Edge
}
#[doc = "Level"]
#[inline(always)]
pub fn is_level(&self) -> bool {
*self == Is3::Level
}
}
#[doc = "Field `IS3` writer - Interrupt sense bit 3"]
pub type Is3W<'a, REG> = crate::BitWriter<'a, REG, Is3>;
impl<'a, REG> Is3W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Edge"]
#[inline(always)]
pub fn edge(self) -> &'a mut crate::W<REG> {
self.variant(Is3::Edge)
}
#[doc = "Level"]
#[inline(always)]
pub fn level(self) -> &'a mut crate::W<REG> {
self.variant(Is3::Level)
}
}
#[doc = "Interrupt sense bit 4\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Is4 {
#[doc = "0: Edge"]
Edge = 0,
#[doc = "1: Level"]
Level = 1,
}
impl From<Is4> for bool {
#[inline(always)]
fn from(variant: Is4) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `IS4` reader - Interrupt sense bit 4"]
pub type Is4R = crate::BitReader<Is4>;
impl Is4R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Is4 {
match self.bits {
false => Is4::Edge,
true => Is4::Level,
}
}
#[doc = "Edge"]
#[inline(always)]
pub fn is_edge(&self) -> bool {
*self == Is4::Edge
}
#[doc = "Level"]
#[inline(always)]
pub fn is_level(&self) -> bool {
*self == Is4::Level
}
}
#[doc = "Field `IS4` writer - Interrupt sense bit 4"]
pub type Is4W<'a, REG> = crate::BitWriter<'a, REG, Is4>;
impl<'a, REG> Is4W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Edge"]
#[inline(always)]
pub fn edge(self) -> &'a mut crate::W<REG> {
self.variant(Is4::Edge)
}
#[doc = "Level"]
#[inline(always)]
pub fn level(self) -> &'a mut crate::W<REG> {
self.variant(Is4::Level)
}
}
#[doc = "Interrupt sense bit 5\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Is5 {
#[doc = "0: Edge"]
Edge = 0,
#[doc = "1: Level"]
Level = 1,
}
impl From<Is5> for bool {
#[inline(always)]
fn from(variant: Is5) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `IS5` reader - Interrupt sense bit 5"]
pub type Is5R = crate::BitReader<Is5>;
impl Is5R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Is5 {
match self.bits {
false => Is5::Edge,
true => Is5::Level,
}
}
#[doc = "Edge"]
#[inline(always)]
pub fn is_edge(&self) -> bool {
*self == Is5::Edge
}
#[doc = "Level"]
#[inline(always)]
pub fn is_level(&self) -> bool {
*self == Is5::Level
}
}
#[doc = "Field `IS5` writer - Interrupt sense bit 5"]
pub type Is5W<'a, REG> = crate::BitWriter<'a, REG, Is5>;
impl<'a, REG> Is5W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Edge"]
#[inline(always)]
pub fn edge(self) -> &'a mut crate::W<REG> {
self.variant(Is5::Edge)
}
#[doc = "Level"]
#[inline(always)]
pub fn level(self) -> &'a mut crate::W<REG> {
self.variant(Is5::Level)
}
}
#[doc = "Interrupt sense bit 6\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Is6 {
#[doc = "0: Edge"]
Edge = 0,
#[doc = "1: Level"]
Level = 1,
}
impl From<Is6> for bool {
#[inline(always)]
fn from(variant: Is6) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `IS6` reader - Interrupt sense bit 6"]
pub type Is6R = crate::BitReader<Is6>;
impl Is6R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Is6 {
match self.bits {
false => Is6::Edge,
true => Is6::Level,
}
}
#[doc = "Edge"]
#[inline(always)]
pub fn is_edge(&self) -> bool {
*self == Is6::Edge
}
#[doc = "Level"]
#[inline(always)]
pub fn is_level(&self) -> bool {
*self == Is6::Level
}
}
#[doc = "Field `IS6` writer - Interrupt sense bit 6"]
pub type Is6W<'a, REG> = crate::BitWriter<'a, REG, Is6>;
impl<'a, REG> Is6W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Edge"]
#[inline(always)]
pub fn edge(self) -> &'a mut crate::W<REG> {
self.variant(Is6::Edge)
}
#[doc = "Level"]
#[inline(always)]
pub fn level(self) -> &'a mut crate::W<REG> {
self.variant(Is6::Level)
}
}
#[doc = "Interrupt sense bit 7\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Is7 {
#[doc = "0: Edge"]
Edge = 0,
#[doc = "1: Level"]
Level = 1,
}
impl From<Is7> for bool {
#[inline(always)]
fn from(variant: Is7) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `IS7` reader - Interrupt sense bit 7"]
pub type Is7R = crate::BitReader<Is7>;
impl Is7R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Is7 {
match self.bits {
false => Is7::Edge,
true => Is7::Level,
}
}
#[doc = "Edge"]
#[inline(always)]
pub fn is_edge(&self) -> bool {
*self == Is7::Edge
}
#[doc = "Level"]
#[inline(always)]
pub fn is_level(&self) -> bool {
*self == Is7::Level
}
}
#[doc = "Field `IS7` writer - Interrupt sense bit 7"]
pub type Is7W<'a, REG> = crate::BitWriter<'a, REG, Is7>;
impl<'a, REG> Is7W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Edge"]
#[inline(always)]
pub fn edge(self) -> &'a mut crate::W<REG> {
self.variant(Is7::Edge)
}
#[doc = "Level"]
#[inline(always)]
pub fn level(self) -> &'a mut crate::W<REG> {
self.variant(Is7::Level)
}
}
impl R {
#[doc = "Bit 0 - Interrupt sense bit 0"]
#[inline(always)]
pub fn is0(&self) -> Is0R {
Is0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Interrupt sense bit 1"]
#[inline(always)]
pub fn is1(&self) -> Is1R {
Is1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Interrupt sense bit 2"]
#[inline(always)]
pub fn is2(&self) -> Is2R {
Is2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Interrupt sense bit 3"]
#[inline(always)]
pub fn is3(&self) -> Is3R {
Is3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Interrupt sense bit 4"]
#[inline(always)]
pub fn is4(&self) -> Is4R {
Is4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Interrupt sense bit 5"]
#[inline(always)]
pub fn is5(&self) -> Is5R {
Is5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Interrupt sense bit 6"]
#[inline(always)]
pub fn is6(&self) -> Is6R {
Is6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Interrupt sense bit 7"]
#[inline(always)]
pub fn is7(&self) -> Is7R {
Is7R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Interrupt sense bit 0"]
#[inline(always)]
pub fn is0(&mut self) -> Is0W<IsSpec> {
Is0W::new(self, 0)
}
#[doc = "Bit 1 - Interrupt sense bit 1"]
#[inline(always)]
pub fn is1(&mut self) -> Is1W<IsSpec> {
Is1W::new(self, 1)
}
#[doc = "Bit 2 - Interrupt sense bit 2"]
#[inline(always)]
pub fn is2(&mut self) -> Is2W<IsSpec> {
Is2W::new(self, 2)
}
#[doc = "Bit 3 - Interrupt sense bit 3"]
#[inline(always)]
pub fn is3(&mut self) -> Is3W<IsSpec> {
Is3W::new(self, 3)
}
#[doc = "Bit 4 - Interrupt sense bit 4"]
#[inline(always)]
pub fn is4(&mut self) -> Is4W<IsSpec> {
Is4W::new(self, 4)
}
#[doc = "Bit 5 - Interrupt sense bit 5"]
#[inline(always)]
pub fn is5(&mut self) -> Is5W<IsSpec> {
Is5W::new(self, 5)
}
#[doc = "Bit 6 - Interrupt sense bit 6"]
#[inline(always)]
pub fn is6(&mut self) -> Is6W<IsSpec> {
Is6W::new(self, 6)
}
#[doc = "Bit 7 - Interrupt sense bit 7"]
#[inline(always)]
pub fn is7(&mut self) -> Is7W<IsSpec> {
Is7W::new(self, 7)
}
}
#[doc = "Interrupt sense register\n\nYou can [`read`](crate::Reg::read) this register and get [`is::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`is::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IsSpec;
impl crate::RegisterSpec for IsSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`is::R`](R) reader structure"]
impl crate::Readable for IsSpec {}
#[doc = "`write(|w| ..)` method takes [`is::W`](W) writer structure"]
impl crate::Writable for IsSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets IS to value 0"]
impl crate::Resettable for IsSpec {}
}
#[doc = "IBE (rw) register accessor: Interrupt both-edges register\n\nYou can [`read`](crate::Reg::read) this register and get [`ibe::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ibe::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ibe`] module"]
#[doc(alias = "IBE")]
pub type Ibe = crate::Reg<ibe::IbeSpec>;
#[doc = "Interrupt both-edges register"]
pub mod ibe {
#[doc = "Register `IBE` reader"]
pub type R = crate::R<IbeSpec>;
#[doc = "Register `IBE` writer"]
pub type W = crate::W<IbeSpec>;
#[doc = "Interrupt both-edges bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Ibe0 {
#[doc = "0: Single Edge"]
SingleEdge = 0,
#[doc = "1: Both Edge"]
BothEdge = 1,
}
impl From<Ibe0> for bool {
#[inline(always)]
fn from(variant: Ibe0) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `IBE0` reader - Interrupt both-edges bit 0"]
pub type Ibe0R = crate::BitReader<Ibe0>;
impl Ibe0R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Ibe0 {
match self.bits {
false => Ibe0::SingleEdge,
true => Ibe0::BothEdge,
}
}
#[doc = "Single Edge"]
#[inline(always)]
pub fn is_single_edge(&self) -> bool {
*self == Ibe0::SingleEdge
}
#[doc = "Both Edge"]
#[inline(always)]
pub fn is_both_edge(&self) -> bool {
*self == Ibe0::BothEdge
}
}
#[doc = "Field `IBE0` writer - Interrupt both-edges bit 0"]
pub type Ibe0W<'a, REG> = crate::BitWriter<'a, REG, Ibe0>;
impl<'a, REG> Ibe0W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Single Edge"]
#[inline(always)]
pub fn single_edge(self) -> &'a mut crate::W<REG> {
self.variant(Ibe0::SingleEdge)
}
#[doc = "Both Edge"]
#[inline(always)]
pub fn both_edge(self) -> &'a mut crate::W<REG> {
self.variant(Ibe0::BothEdge)
}
}
#[doc = "Interrupt both-edges bit 1\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Ibe1 {
#[doc = "0: Single Edge"]
SingleEdge = 0,
#[doc = "1: Both Edge"]
BothEdge = 1,
}
impl From<Ibe1> for bool {
#[inline(always)]
fn from(variant: Ibe1) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `IBE1` reader - Interrupt both-edges bit 1"]
pub type Ibe1R = crate::BitReader<Ibe1>;
impl Ibe1R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Ibe1 {
match self.bits {
false => Ibe1::SingleEdge,
true => Ibe1::BothEdge,
}
}
#[doc = "Single Edge"]
#[inline(always)]
pub fn is_single_edge(&self) -> bool {
*self == Ibe1::SingleEdge
}
#[doc = "Both Edge"]
#[inline(always)]
pub fn is_both_edge(&self) -> bool {
*self == Ibe1::BothEdge
}
}
#[doc = "Field `IBE1` writer - Interrupt both-edges bit 1"]
pub type Ibe1W<'a, REG> = crate::BitWriter<'a, REG, Ibe1>;
impl<'a, REG> Ibe1W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Single Edge"]
#[inline(always)]
pub fn single_edge(self) -> &'a mut crate::W<REG> {
self.variant(Ibe1::SingleEdge)
}
#[doc = "Both Edge"]
#[inline(always)]
pub fn both_edge(self) -> &'a mut crate::W<REG> {
self.variant(Ibe1::BothEdge)
}
}
#[doc = "Interrupt both-edges bit 2\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Ibe2 {
#[doc = "0: Single Edge"]
SingleEdge = 0,
#[doc = "1: Both Edge"]
BothEdge = 1,
}
impl From<Ibe2> for bool {
#[inline(always)]
fn from(variant: Ibe2) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `IBE2` reader - Interrupt both-edges bit 2"]
pub type Ibe2R = crate::BitReader<Ibe2>;
impl Ibe2R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Ibe2 {
match self.bits {
false => Ibe2::SingleEdge,
true => Ibe2::BothEdge,
}
}
#[doc = "Single Edge"]
#[inline(always)]
pub fn is_single_edge(&self) -> bool {
*self == Ibe2::SingleEdge
}
#[doc = "Both Edge"]
#[inline(always)]
pub fn is_both_edge(&self) -> bool {
*self == Ibe2::BothEdge
}
}
#[doc = "Field `IBE2` writer - Interrupt both-edges bit 2"]
pub type Ibe2W<'a, REG> = crate::BitWriter<'a, REG, Ibe2>;
impl<'a, REG> Ibe2W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Single Edge"]
#[inline(always)]
pub fn single_edge(self) -> &'a mut crate::W<REG> {
self.variant(Ibe2::SingleEdge)
}
#[doc = "Both Edge"]
#[inline(always)]
pub fn both_edge(self) -> &'a mut crate::W<REG> {
self.variant(Ibe2::BothEdge)
}
}
#[doc = "Interrupt both-edges bit 3\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Ibe3 {
#[doc = "0: Single Edge"]
SingleEdge = 0,
#[doc = "1: Both Edge"]
BothEdge = 1,
}
impl From<Ibe3> for bool {
#[inline(always)]
fn from(variant: Ibe3) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `IBE3` reader - Interrupt both-edges bit 3"]
pub type Ibe3R = crate::BitReader<Ibe3>;
impl Ibe3R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Ibe3 {
match self.bits {
false => Ibe3::SingleEdge,
true => Ibe3::BothEdge,
}
}
#[doc = "Single Edge"]
#[inline(always)]
pub fn is_single_edge(&self) -> bool {
*self == Ibe3::SingleEdge
}
#[doc = "Both Edge"]
#[inline(always)]
pub fn is_both_edge(&self) -> bool {
*self == Ibe3::BothEdge
}
}
#[doc = "Field `IBE3` writer - Interrupt both-edges bit 3"]
pub type Ibe3W<'a, REG> = crate::BitWriter<'a, REG, Ibe3>;
impl<'a, REG> Ibe3W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Single Edge"]
#[inline(always)]
pub fn single_edge(self) -> &'a mut crate::W<REG> {
self.variant(Ibe3::SingleEdge)
}
#[doc = "Both Edge"]
#[inline(always)]
pub fn both_edge(self) -> &'a mut crate::W<REG> {
self.variant(Ibe3::BothEdge)
}
}
#[doc = "Interrupt both-edges bit 4\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Ibe4 {
#[doc = "0: Single Edge"]
SingleEdge = 0,
#[doc = "1: Both Edge"]
BothEdge = 1,
}
impl From<Ibe4> for bool {
#[inline(always)]
fn from(variant: Ibe4) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `IBE4` reader - Interrupt both-edges bit 4"]
pub type Ibe4R = crate::BitReader<Ibe4>;
impl Ibe4R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Ibe4 {
match self.bits {
false => Ibe4::SingleEdge,
true => Ibe4::BothEdge,
}
}
#[doc = "Single Edge"]
#[inline(always)]
pub fn is_single_edge(&self) -> bool {
*self == Ibe4::SingleEdge
}
#[doc = "Both Edge"]
#[inline(always)]
pub fn is_both_edge(&self) -> bool {
*self == Ibe4::BothEdge
}
}
#[doc = "Field `IBE4` writer - Interrupt both-edges bit 4"]
pub type Ibe4W<'a, REG> = crate::BitWriter<'a, REG, Ibe4>;
impl<'a, REG> Ibe4W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Single Edge"]
#[inline(always)]
pub fn single_edge(self) -> &'a mut crate::W<REG> {
self.variant(Ibe4::SingleEdge)
}
#[doc = "Both Edge"]
#[inline(always)]
pub fn both_edge(self) -> &'a mut crate::W<REG> {
self.variant(Ibe4::BothEdge)
}
}
#[doc = "Interrupt both-edges bit 5\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Ibe5 {
#[doc = "0: Single Edge"]
SingleEdge = 0,
#[doc = "1: Both Edge"]
BothEdge = 1,
}
impl From<Ibe5> for bool {
#[inline(always)]
fn from(variant: Ibe5) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `IBE5` reader - Interrupt both-edges bit 5"]
pub type Ibe5R = crate::BitReader<Ibe5>;
impl Ibe5R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Ibe5 {
match self.bits {
false => Ibe5::SingleEdge,
true => Ibe5::BothEdge,
}
}
#[doc = "Single Edge"]
#[inline(always)]
pub fn is_single_edge(&self) -> bool {
*self == Ibe5::SingleEdge
}
#[doc = "Both Edge"]
#[inline(always)]
pub fn is_both_edge(&self) -> bool {
*self == Ibe5::BothEdge
}
}
#[doc = "Field `IBE5` writer - Interrupt both-edges bit 5"]
pub type Ibe5W<'a, REG> = crate::BitWriter<'a, REG, Ibe5>;
impl<'a, REG> Ibe5W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Single Edge"]
#[inline(always)]
pub fn single_edge(self) -> &'a mut crate::W<REG> {
self.variant(Ibe5::SingleEdge)
}
#[doc = "Both Edge"]
#[inline(always)]
pub fn both_edge(self) -> &'a mut crate::W<REG> {
self.variant(Ibe5::BothEdge)
}
}
#[doc = "Interrupt both-edges bit 6\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Ibe6 {
#[doc = "0: Single Edge"]
SingleEdge = 0,
#[doc = "1: Both Edge"]
BothEdge = 1,
}
impl From<Ibe6> for bool {
#[inline(always)]
fn from(variant: Ibe6) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `IBE6` reader - Interrupt both-edges bit 6"]
pub type Ibe6R = crate::BitReader<Ibe6>;
impl Ibe6R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Ibe6 {
match self.bits {
false => Ibe6::SingleEdge,
true => Ibe6::BothEdge,
}
}
#[doc = "Single Edge"]
#[inline(always)]
pub fn is_single_edge(&self) -> bool {
*self == Ibe6::SingleEdge
}
#[doc = "Both Edge"]
#[inline(always)]
pub fn is_both_edge(&self) -> bool {
*self == Ibe6::BothEdge
}
}
#[doc = "Field `IBE6` writer - Interrupt both-edges bit 6"]
pub type Ibe6W<'a, REG> = crate::BitWriter<'a, REG, Ibe6>;
impl<'a, REG> Ibe6W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Single Edge"]
#[inline(always)]
pub fn single_edge(self) -> &'a mut crate::W<REG> {
self.variant(Ibe6::SingleEdge)
}
#[doc = "Both Edge"]
#[inline(always)]
pub fn both_edge(self) -> &'a mut crate::W<REG> {
self.variant(Ibe6::BothEdge)
}
}
#[doc = "Interrupt both-edges bit 7\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Ibe7 {
#[doc = "0: Single Edge"]
SingleEdge = 0,
#[doc = "1: Both Edge"]
BothEdge = 1,
}
impl From<Ibe7> for bool {
#[inline(always)]
fn from(variant: Ibe7) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `IBE7` reader - Interrupt both-edges bit 7"]
pub type Ibe7R = crate::BitReader<Ibe7>;
impl Ibe7R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Ibe7 {
match self.bits {
false => Ibe7::SingleEdge,
true => Ibe7::BothEdge,
}
}
#[doc = "Single Edge"]
#[inline(always)]
pub fn is_single_edge(&self) -> bool {
*self == Ibe7::SingleEdge
}
#[doc = "Both Edge"]
#[inline(always)]
pub fn is_both_edge(&self) -> bool {
*self == Ibe7::BothEdge
}
}
#[doc = "Field `IBE7` writer - Interrupt both-edges bit 7"]
pub type Ibe7W<'a, REG> = crate::BitWriter<'a, REG, Ibe7>;
impl<'a, REG> Ibe7W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Single Edge"]
#[inline(always)]
pub fn single_edge(self) -> &'a mut crate::W<REG> {
self.variant(Ibe7::SingleEdge)
}
#[doc = "Both Edge"]
#[inline(always)]
pub fn both_edge(self) -> &'a mut crate::W<REG> {
self.variant(Ibe7::BothEdge)
}
}
impl R {
#[doc = "Bit 0 - Interrupt both-edges bit 0"]
#[inline(always)]
pub fn ibe0(&self) -> Ibe0R {
Ibe0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Interrupt both-edges bit 1"]
#[inline(always)]
pub fn ibe1(&self) -> Ibe1R {
Ibe1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Interrupt both-edges bit 2"]
#[inline(always)]
pub fn ibe2(&self) -> Ibe2R {
Ibe2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Interrupt both-edges bit 3"]
#[inline(always)]
pub fn ibe3(&self) -> Ibe3R {
Ibe3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Interrupt both-edges bit 4"]
#[inline(always)]
pub fn ibe4(&self) -> Ibe4R {
Ibe4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Interrupt both-edges bit 5"]
#[inline(always)]
pub fn ibe5(&self) -> Ibe5R {
Ibe5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Interrupt both-edges bit 6"]
#[inline(always)]
pub fn ibe6(&self) -> Ibe6R {
Ibe6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Interrupt both-edges bit 7"]
#[inline(always)]
pub fn ibe7(&self) -> Ibe7R {
Ibe7R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Interrupt both-edges bit 0"]
#[inline(always)]
pub fn ibe0(&mut self) -> Ibe0W<IbeSpec> {
Ibe0W::new(self, 0)
}
#[doc = "Bit 1 - Interrupt both-edges bit 1"]
#[inline(always)]
pub fn ibe1(&mut self) -> Ibe1W<IbeSpec> {
Ibe1W::new(self, 1)
}
#[doc = "Bit 2 - Interrupt both-edges bit 2"]
#[inline(always)]
pub fn ibe2(&mut self) -> Ibe2W<IbeSpec> {
Ibe2W::new(self, 2)
}
#[doc = "Bit 3 - Interrupt both-edges bit 3"]
#[inline(always)]
pub fn ibe3(&mut self) -> Ibe3W<IbeSpec> {
Ibe3W::new(self, 3)
}
#[doc = "Bit 4 - Interrupt both-edges bit 4"]
#[inline(always)]
pub fn ibe4(&mut self) -> Ibe4W<IbeSpec> {
Ibe4W::new(self, 4)
}
#[doc = "Bit 5 - Interrupt both-edges bit 5"]
#[inline(always)]
pub fn ibe5(&mut self) -> Ibe5W<IbeSpec> {
Ibe5W::new(self, 5)
}
#[doc = "Bit 6 - Interrupt both-edges bit 6"]
#[inline(always)]
pub fn ibe6(&mut self) -> Ibe6W<IbeSpec> {
Ibe6W::new(self, 6)
}
#[doc = "Bit 7 - Interrupt both-edges bit 7"]
#[inline(always)]
pub fn ibe7(&mut self) -> Ibe7W<IbeSpec> {
Ibe7W::new(self, 7)
}
}
#[doc = "Interrupt both-edges register\n\nYou can [`read`](crate::Reg::read) this register and get [`ibe::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ibe::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IbeSpec;
impl crate::RegisterSpec for IbeSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ibe::R`](R) reader structure"]
impl crate::Readable for IbeSpec {}
#[doc = "`write(|w| ..)` method takes [`ibe::W`](W) writer structure"]
impl crate::Writable for IbeSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets IBE to value 0"]
impl crate::Resettable for IbeSpec {}
}
#[doc = "IEV (rw) register accessor: Interrupt event register\n\nYou can [`read`](crate::Reg::read) this register and get [`iev::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iev::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iev`] module"]
#[doc(alias = "IEV")]
pub type Iev = crate::Reg<iev::IevSpec>;
#[doc = "Interrupt event register"]
pub mod iev {
#[doc = "Register `IEV` reader"]
pub type R = crate::R<IevSpec>;
#[doc = "Register `IEV` writer"]
pub type W = crate::W<IevSpec>;
#[doc = "Interrupt event bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Iev0 {
#[doc = "0: Rising Edge/High Level"]
RisingEdgeHighLevel = 0,
#[doc = "1: Falling Edge/Low Level"]
FallingEdgeLowLevel = 1,
}
impl From<Iev0> for bool {
#[inline(always)]
fn from(variant: Iev0) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `IEV0` reader - Interrupt event bit 0"]
pub type Iev0R = crate::BitReader<Iev0>;
impl Iev0R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Iev0 {
match self.bits {
false => Iev0::RisingEdgeHighLevel,
true => Iev0::FallingEdgeLowLevel,
}
}
#[doc = "Rising Edge/High Level"]
#[inline(always)]
pub fn is_rising_edge_high_level(&self) -> bool {
*self == Iev0::RisingEdgeHighLevel
}
#[doc = "Falling Edge/Low Level"]
#[inline(always)]
pub fn is_falling_edge_low_level(&self) -> bool {
*self == Iev0::FallingEdgeLowLevel
}
}
#[doc = "Field `IEV0` writer - Interrupt event bit 0"]
pub type Iev0W<'a, REG> = crate::BitWriter<'a, REG, Iev0>;
impl<'a, REG> Iev0W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Rising Edge/High Level"]
#[inline(always)]
pub fn rising_edge_high_level(self) -> &'a mut crate::W<REG> {
self.variant(Iev0::RisingEdgeHighLevel)
}
#[doc = "Falling Edge/Low Level"]
#[inline(always)]
pub fn falling_edge_low_level(self) -> &'a mut crate::W<REG> {
self.variant(Iev0::FallingEdgeLowLevel)
}
}
#[doc = "Interrupt event bit 1\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Iev1 {
#[doc = "0: Rising Edge/High Level"]
RisingEdgeHighLevel = 0,
#[doc = "1: Falling Edge/Low Level"]
FallingEdgeLowLevel = 1,
}
impl From<Iev1> for bool {
#[inline(always)]
fn from(variant: Iev1) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `IEV1` reader - Interrupt event bit 1"]
pub type Iev1R = crate::BitReader<Iev1>;
impl Iev1R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Iev1 {
match self.bits {
false => Iev1::RisingEdgeHighLevel,
true => Iev1::FallingEdgeLowLevel,
}
}
#[doc = "Rising Edge/High Level"]
#[inline(always)]
pub fn is_rising_edge_high_level(&self) -> bool {
*self == Iev1::RisingEdgeHighLevel
}
#[doc = "Falling Edge/Low Level"]
#[inline(always)]
pub fn is_falling_edge_low_level(&self) -> bool {
*self == Iev1::FallingEdgeLowLevel
}
}
#[doc = "Field `IEV1` writer - Interrupt event bit 1"]
pub type Iev1W<'a, REG> = crate::BitWriter<'a, REG, Iev1>;
impl<'a, REG> Iev1W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Rising Edge/High Level"]
#[inline(always)]
pub fn rising_edge_high_level(self) -> &'a mut crate::W<REG> {
self.variant(Iev1::RisingEdgeHighLevel)
}
#[doc = "Falling Edge/Low Level"]
#[inline(always)]
pub fn falling_edge_low_level(self) -> &'a mut crate::W<REG> {
self.variant(Iev1::FallingEdgeLowLevel)
}
}
#[doc = "Interrupt event bit 2\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Iev2 {
#[doc = "0: Rising Edge/High Level"]
RisingEdgeHighLevel = 0,
#[doc = "1: Falling Edge/Low Level"]
FallingEdgeLowLevel = 1,
}
impl From<Iev2> for bool {
#[inline(always)]
fn from(variant: Iev2) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `IEV2` reader - Interrupt event bit 2"]
pub type Iev2R = crate::BitReader<Iev2>;
impl Iev2R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Iev2 {
match self.bits {
false => Iev2::RisingEdgeHighLevel,
true => Iev2::FallingEdgeLowLevel,
}
}
#[doc = "Rising Edge/High Level"]
#[inline(always)]
pub fn is_rising_edge_high_level(&self) -> bool {
*self == Iev2::RisingEdgeHighLevel
}
#[doc = "Falling Edge/Low Level"]
#[inline(always)]
pub fn is_falling_edge_low_level(&self) -> bool {
*self == Iev2::FallingEdgeLowLevel
}
}
#[doc = "Field `IEV2` writer - Interrupt event bit 2"]
pub type Iev2W<'a, REG> = crate::BitWriter<'a, REG, Iev2>;
impl<'a, REG> Iev2W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Rising Edge/High Level"]
#[inline(always)]
pub fn rising_edge_high_level(self) -> &'a mut crate::W<REG> {
self.variant(Iev2::RisingEdgeHighLevel)
}
#[doc = "Falling Edge/Low Level"]
#[inline(always)]
pub fn falling_edge_low_level(self) -> &'a mut crate::W<REG> {
self.variant(Iev2::FallingEdgeLowLevel)
}
}
#[doc = "Interrupt event bit 3\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Iev3 {
#[doc = "0: Rising Edge/High Level"]
RisingEdgeHighLevel = 0,
#[doc = "1: Falling Edge/Low Level"]
FallingEdgeLowLevel = 1,
}
impl From<Iev3> for bool {
#[inline(always)]
fn from(variant: Iev3) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `IEV3` reader - Interrupt event bit 3"]
pub type Iev3R = crate::BitReader<Iev3>;
impl Iev3R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Iev3 {
match self.bits {
false => Iev3::RisingEdgeHighLevel,
true => Iev3::FallingEdgeLowLevel,
}
}
#[doc = "Rising Edge/High Level"]
#[inline(always)]
pub fn is_rising_edge_high_level(&self) -> bool {
*self == Iev3::RisingEdgeHighLevel
}
#[doc = "Falling Edge/Low Level"]
#[inline(always)]
pub fn is_falling_edge_low_level(&self) -> bool {
*self == Iev3::FallingEdgeLowLevel
}
}
#[doc = "Field `IEV3` writer - Interrupt event bit 3"]
pub type Iev3W<'a, REG> = crate::BitWriter<'a, REG, Iev3>;
impl<'a, REG> Iev3W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Rising Edge/High Level"]
#[inline(always)]
pub fn rising_edge_high_level(self) -> &'a mut crate::W<REG> {
self.variant(Iev3::RisingEdgeHighLevel)
}
#[doc = "Falling Edge/Low Level"]
#[inline(always)]
pub fn falling_edge_low_level(self) -> &'a mut crate::W<REG> {
self.variant(Iev3::FallingEdgeLowLevel)
}
}
#[doc = "Interrupt event bit 4\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Iev4 {
#[doc = "0: Rising Edge/High Level"]
RisingEdgeHighLevel = 0,
#[doc = "1: Falling Edge/Low Level"]
FallingEdgeLowLevel = 1,
}
impl From<Iev4> for bool {
#[inline(always)]
fn from(variant: Iev4) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `IEV4` reader - Interrupt event bit 4"]
pub type Iev4R = crate::BitReader<Iev4>;
impl Iev4R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Iev4 {
match self.bits {
false => Iev4::RisingEdgeHighLevel,
true => Iev4::FallingEdgeLowLevel,
}
}
#[doc = "Rising Edge/High Level"]
#[inline(always)]
pub fn is_rising_edge_high_level(&self) -> bool {
*self == Iev4::RisingEdgeHighLevel
}
#[doc = "Falling Edge/Low Level"]
#[inline(always)]
pub fn is_falling_edge_low_level(&self) -> bool {
*self == Iev4::FallingEdgeLowLevel
}
}
#[doc = "Field `IEV4` writer - Interrupt event bit 4"]
pub type Iev4W<'a, REG> = crate::BitWriter<'a, REG, Iev4>;
impl<'a, REG> Iev4W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Rising Edge/High Level"]
#[inline(always)]
pub fn rising_edge_high_level(self) -> &'a mut crate::W<REG> {
self.variant(Iev4::RisingEdgeHighLevel)
}
#[doc = "Falling Edge/Low Level"]
#[inline(always)]
pub fn falling_edge_low_level(self) -> &'a mut crate::W<REG> {
self.variant(Iev4::FallingEdgeLowLevel)
}
}
#[doc = "Interrupt event bit 5\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Iev5 {
#[doc = "0: Rising Edge/High Level"]
RisingEdgeHighLevel = 0,
#[doc = "1: Falling Edge/Low Level"]
FallingEdgeLowLevel = 1,
}
impl From<Iev5> for bool {
#[inline(always)]
fn from(variant: Iev5) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `IEV5` reader - Interrupt event bit 5"]
pub type Iev5R = crate::BitReader<Iev5>;
impl Iev5R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Iev5 {
match self.bits {
false => Iev5::RisingEdgeHighLevel,
true => Iev5::FallingEdgeLowLevel,
}
}
#[doc = "Rising Edge/High Level"]
#[inline(always)]
pub fn is_rising_edge_high_level(&self) -> bool {
*self == Iev5::RisingEdgeHighLevel
}
#[doc = "Falling Edge/Low Level"]
#[inline(always)]
pub fn is_falling_edge_low_level(&self) -> bool {
*self == Iev5::FallingEdgeLowLevel
}
}
#[doc = "Field `IEV5` writer - Interrupt event bit 5"]
pub type Iev5W<'a, REG> = crate::BitWriter<'a, REG, Iev5>;
impl<'a, REG> Iev5W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Rising Edge/High Level"]
#[inline(always)]
pub fn rising_edge_high_level(self) -> &'a mut crate::W<REG> {
self.variant(Iev5::RisingEdgeHighLevel)
}
#[doc = "Falling Edge/Low Level"]
#[inline(always)]
pub fn falling_edge_low_level(self) -> &'a mut crate::W<REG> {
self.variant(Iev5::FallingEdgeLowLevel)
}
}
#[doc = "Interrupt event bit 6\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Iev6 {
#[doc = "0: Rising Edge/High Level"]
RisingEdgeHighLevel = 0,
#[doc = "1: Falling Edge/Low Level"]
FallingEdgeLowLevel = 1,
}
impl From<Iev6> for bool {
#[inline(always)]
fn from(variant: Iev6) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `IEV6` reader - Interrupt event bit 6"]
pub type Iev6R = crate::BitReader<Iev6>;
impl Iev6R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Iev6 {
match self.bits {
false => Iev6::RisingEdgeHighLevel,
true => Iev6::FallingEdgeLowLevel,
}
}
#[doc = "Rising Edge/High Level"]
#[inline(always)]
pub fn is_rising_edge_high_level(&self) -> bool {
*self == Iev6::RisingEdgeHighLevel
}
#[doc = "Falling Edge/Low Level"]
#[inline(always)]
pub fn is_falling_edge_low_level(&self) -> bool {
*self == Iev6::FallingEdgeLowLevel
}
}
#[doc = "Field `IEV6` writer - Interrupt event bit 6"]
pub type Iev6W<'a, REG> = crate::BitWriter<'a, REG, Iev6>;
impl<'a, REG> Iev6W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Rising Edge/High Level"]
#[inline(always)]
pub fn rising_edge_high_level(self) -> &'a mut crate::W<REG> {
self.variant(Iev6::RisingEdgeHighLevel)
}
#[doc = "Falling Edge/Low Level"]
#[inline(always)]
pub fn falling_edge_low_level(self) -> &'a mut crate::W<REG> {
self.variant(Iev6::FallingEdgeLowLevel)
}
}
#[doc = "Interrupt event bit 7\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Iev7 {
#[doc = "0: Rising Edge/High Level"]
RisingEdgeHighLevel = 0,
#[doc = "1: Falling Edge/Low Level"]
FallingEdgeLowLevel = 1,
}
impl From<Iev7> for bool {
#[inline(always)]
fn from(variant: Iev7) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `IEV7` reader - Interrupt event bit 7"]
pub type Iev7R = crate::BitReader<Iev7>;
impl Iev7R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Iev7 {
match self.bits {
false => Iev7::RisingEdgeHighLevel,
true => Iev7::FallingEdgeLowLevel,
}
}
#[doc = "Rising Edge/High Level"]
#[inline(always)]
pub fn is_rising_edge_high_level(&self) -> bool {
*self == Iev7::RisingEdgeHighLevel
}
#[doc = "Falling Edge/Low Level"]
#[inline(always)]
pub fn is_falling_edge_low_level(&self) -> bool {
*self == Iev7::FallingEdgeLowLevel
}
}
#[doc = "Field `IEV7` writer - Interrupt event bit 7"]
pub type Iev7W<'a, REG> = crate::BitWriter<'a, REG, Iev7>;
impl<'a, REG> Iev7W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Rising Edge/High Level"]
#[inline(always)]
pub fn rising_edge_high_level(self) -> &'a mut crate::W<REG> {
self.variant(Iev7::RisingEdgeHighLevel)
}
#[doc = "Falling Edge/Low Level"]
#[inline(always)]
pub fn falling_edge_low_level(self) -> &'a mut crate::W<REG> {
self.variant(Iev7::FallingEdgeLowLevel)
}
}
impl R {
#[doc = "Bit 0 - Interrupt event bit 0"]
#[inline(always)]
pub fn iev0(&self) -> Iev0R {
Iev0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Interrupt event bit 1"]
#[inline(always)]
pub fn iev1(&self) -> Iev1R {
Iev1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Interrupt event bit 2"]
#[inline(always)]
pub fn iev2(&self) -> Iev2R {
Iev2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Interrupt event bit 3"]
#[inline(always)]
pub fn iev3(&self) -> Iev3R {
Iev3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Interrupt event bit 4"]
#[inline(always)]
pub fn iev4(&self) -> Iev4R {
Iev4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Interrupt event bit 5"]
#[inline(always)]
pub fn iev5(&self) -> Iev5R {
Iev5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Interrupt event bit 6"]
#[inline(always)]
pub fn iev6(&self) -> Iev6R {
Iev6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Interrupt event bit 7"]
#[inline(always)]
pub fn iev7(&self) -> Iev7R {
Iev7R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Interrupt event bit 0"]
#[inline(always)]
pub fn iev0(&mut self) -> Iev0W<IevSpec> {
Iev0W::new(self, 0)
}
#[doc = "Bit 1 - Interrupt event bit 1"]
#[inline(always)]
pub fn iev1(&mut self) -> Iev1W<IevSpec> {
Iev1W::new(self, 1)
}
#[doc = "Bit 2 - Interrupt event bit 2"]
#[inline(always)]
pub fn iev2(&mut self) -> Iev2W<IevSpec> {
Iev2W::new(self, 2)
}
#[doc = "Bit 3 - Interrupt event bit 3"]
#[inline(always)]
pub fn iev3(&mut self) -> Iev3W<IevSpec> {
Iev3W::new(self, 3)
}
#[doc = "Bit 4 - Interrupt event bit 4"]
#[inline(always)]
pub fn iev4(&mut self) -> Iev4W<IevSpec> {
Iev4W::new(self, 4)
}
#[doc = "Bit 5 - Interrupt event bit 5"]
#[inline(always)]
pub fn iev5(&mut self) -> Iev5W<IevSpec> {
Iev5W::new(self, 5)
}
#[doc = "Bit 6 - Interrupt event bit 6"]
#[inline(always)]
pub fn iev6(&mut self) -> Iev6W<IevSpec> {
Iev6W::new(self, 6)
}
#[doc = "Bit 7 - Interrupt event bit 7"]
#[inline(always)]
pub fn iev7(&mut self) -> Iev7W<IevSpec> {
Iev7W::new(self, 7)
}
}
#[doc = "Interrupt event register\n\nYou can [`read`](crate::Reg::read) this register and get [`iev::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iev::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IevSpec;
impl crate::RegisterSpec for IevSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`iev::R`](R) reader structure"]
impl crate::Readable for IevSpec {}
#[doc = "`write(|w| ..)` method takes [`iev::W`](W) writer structure"]
impl crate::Writable for IevSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets IEV to value 0"]
impl crate::Resettable for IevSpec {}
}
#[doc = "IE (rw) register accessor: Interrupt mask register\n\nYou can [`read`](crate::Reg::read) this register and get [`ie::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ie::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ie`] module"]
#[doc(alias = "IE")]
pub type Ie = crate::Reg<ie::IeSpec>;
#[doc = "Interrupt mask register"]
pub mod ie {
#[doc = "Register `IE` reader"]
pub type R = crate::R<IeSpec>;
#[doc = "Register `IE` writer"]
pub type W = crate::W<IeSpec>;
#[doc = "Field `IE0` reader - Interrupt mask bit 0"]
pub type Ie0R = crate::BitReader;
#[doc = "Field `IE0` writer - Interrupt mask bit 0"]
pub type Ie0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IE1` reader - Interrupt mask bit 1"]
pub type Ie1R = crate::BitReader;
#[doc = "Field `IE1` writer - Interrupt mask bit 1"]
pub type Ie1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IE2` reader - Interrupt mask bit 2"]
pub type Ie2R = crate::BitReader;
#[doc = "Field `IE2` writer - Interrupt mask bit 2"]
pub type Ie2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IE3` reader - Interrupt mask bit 3"]
pub type Ie3R = crate::BitReader;
#[doc = "Field `IE3` writer - Interrupt mask bit 3"]
pub type Ie3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IE4` reader - Interrupt mask bit 4"]
pub type Ie4R = crate::BitReader;
#[doc = "Field `IE4` writer - Interrupt mask bit 4"]
pub type Ie4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IE5` reader - Interrupt mask bit 5"]
pub type Ie5R = crate::BitReader;
#[doc = "Field `IE5` writer - Interrupt mask bit 5"]
pub type Ie5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IE6` reader - Interrupt mask bit 6"]
pub type Ie6R = crate::BitReader;
#[doc = "Field `IE6` writer - Interrupt mask bit 6"]
pub type Ie6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IE7` reader - Interrupt mask bit 7"]
pub type Ie7R = crate::BitReader;
#[doc = "Field `IE7` writer - Interrupt mask bit 7"]
pub type Ie7W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - Interrupt mask bit 0"]
#[inline(always)]
pub fn ie0(&self) -> Ie0R {
Ie0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Interrupt mask bit 1"]
#[inline(always)]
pub fn ie1(&self) -> Ie1R {
Ie1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Interrupt mask bit 2"]
#[inline(always)]
pub fn ie2(&self) -> Ie2R {
Ie2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Interrupt mask bit 3"]
#[inline(always)]
pub fn ie3(&self) -> Ie3R {
Ie3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Interrupt mask bit 4"]
#[inline(always)]
pub fn ie4(&self) -> Ie4R {
Ie4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Interrupt mask bit 5"]
#[inline(always)]
pub fn ie5(&self) -> Ie5R {
Ie5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Interrupt mask bit 6"]
#[inline(always)]
pub fn ie6(&self) -> Ie6R {
Ie6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Interrupt mask bit 7"]
#[inline(always)]
pub fn ie7(&self) -> Ie7R {
Ie7R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Interrupt mask bit 0"]
#[inline(always)]
pub fn ie0(&mut self) -> Ie0W<IeSpec> {
Ie0W::new(self, 0)
}
#[doc = "Bit 1 - Interrupt mask bit 1"]
#[inline(always)]
pub fn ie1(&mut self) -> Ie1W<IeSpec> {
Ie1W::new(self, 1)
}
#[doc = "Bit 2 - Interrupt mask bit 2"]
#[inline(always)]
pub fn ie2(&mut self) -> Ie2W<IeSpec> {
Ie2W::new(self, 2)
}
#[doc = "Bit 3 - Interrupt mask bit 3"]
#[inline(always)]
pub fn ie3(&mut self) -> Ie3W<IeSpec> {
Ie3W::new(self, 3)
}
#[doc = "Bit 4 - Interrupt mask bit 4"]
#[inline(always)]
pub fn ie4(&mut self) -> Ie4W<IeSpec> {
Ie4W::new(self, 4)
}
#[doc = "Bit 5 - Interrupt mask bit 5"]
#[inline(always)]
pub fn ie5(&mut self) -> Ie5W<IeSpec> {
Ie5W::new(self, 5)
}
#[doc = "Bit 6 - Interrupt mask bit 6"]
#[inline(always)]
pub fn ie6(&mut self) -> Ie6W<IeSpec> {
Ie6W::new(self, 6)
}
#[doc = "Bit 7 - Interrupt mask bit 7"]
#[inline(always)]
pub fn ie7(&mut self) -> Ie7W<IeSpec> {
Ie7W::new(self, 7)
}
}
#[doc = "Interrupt mask register\n\nYou can [`read`](crate::Reg::read) this register and get [`ie::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ie::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IeSpec;
impl crate::RegisterSpec for IeSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ie::R`](R) reader structure"]
impl crate::Readable for IeSpec {}
#[doc = "`write(|w| ..)` method takes [`ie::W`](W) writer structure"]
impl crate::Writable for IeSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets IE to value 0"]
impl crate::Resettable for IeSpec {}
}
#[doc = "RIS (rw) register accessor: Raw interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`ris::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ris::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ris`] module"]
#[doc(alias = "RIS")]
pub type Ris = crate::Reg<ris::RisSpec>;
#[doc = "Raw interrupt status register"]
pub mod ris {
#[doc = "Register `RIS` reader"]
pub type R = crate::R<RisSpec>;
#[doc = "Register `RIS` writer"]
pub type W = crate::W<RisSpec>;
#[doc = "Field `RIS0` reader - Raw interrupt status bit 0"]
pub type Ris0R = crate::BitReader;
#[doc = "Field `RIS0` writer - Raw interrupt status bit 0"]
pub type Ris0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RIS1` reader - Raw interrupt status bit 1"]
pub type Ris1R = crate::BitReader;
#[doc = "Field `RIS1` writer - Raw interrupt status bit 1"]
pub type Ris1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RIS2` reader - Raw interrupt status bit 2"]
pub type Ris2R = crate::BitReader;
#[doc = "Field `RIS2` writer - Raw interrupt status bit 2"]
pub type Ris2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RIS3` reader - Raw interrupt status bit 3"]
pub type Ris3R = crate::BitReader;
#[doc = "Field `RIS3` writer - Raw interrupt status bit 3"]
pub type Ris3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RIS4` reader - Raw interrupt status bit 4"]
pub type Ris4R = crate::BitReader;
#[doc = "Field `RIS4` writer - Raw interrupt status bit 4"]
pub type Ris4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RIS5` reader - Raw interrupt status bit 5"]
pub type Ris5R = crate::BitReader;
#[doc = "Field `RIS5` writer - Raw interrupt status bit 5"]
pub type Ris5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RIS6` reader - Raw interrupt status bit 6"]
pub type Ris6R = crate::BitReader;
#[doc = "Field `RIS6` writer - Raw interrupt status bit 6"]
pub type Ris6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RIS7` reader - Raw interrupt status bit 7"]
pub type Ris7R = crate::BitReader;
#[doc = "Field `RIS7` writer - Raw interrupt status bit 7"]
pub type Ris7W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - Raw interrupt status bit 0"]
#[inline(always)]
pub fn ris0(&self) -> Ris0R {
Ris0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Raw interrupt status bit 1"]
#[inline(always)]
pub fn ris1(&self) -> Ris1R {
Ris1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Raw interrupt status bit 2"]
#[inline(always)]
pub fn ris2(&self) -> Ris2R {
Ris2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Raw interrupt status bit 3"]
#[inline(always)]
pub fn ris3(&self) -> Ris3R {
Ris3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Raw interrupt status bit 4"]
#[inline(always)]
pub fn ris4(&self) -> Ris4R {
Ris4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Raw interrupt status bit 5"]
#[inline(always)]
pub fn ris5(&self) -> Ris5R {
Ris5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Raw interrupt status bit 6"]
#[inline(always)]
pub fn ris6(&self) -> Ris6R {
Ris6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Raw interrupt status bit 7"]
#[inline(always)]
pub fn ris7(&self) -> Ris7R {
Ris7R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Raw interrupt status bit 0"]
#[inline(always)]
pub fn ris0(&mut self) -> Ris0W<RisSpec> {
Ris0W::new(self, 0)
}
#[doc = "Bit 1 - Raw interrupt status bit 1"]
#[inline(always)]
pub fn ris1(&mut self) -> Ris1W<RisSpec> {
Ris1W::new(self, 1)
}
#[doc = "Bit 2 - Raw interrupt status bit 2"]
#[inline(always)]
pub fn ris2(&mut self) -> Ris2W<RisSpec> {
Ris2W::new(self, 2)
}
#[doc = "Bit 3 - Raw interrupt status bit 3"]
#[inline(always)]
pub fn ris3(&mut self) -> Ris3W<RisSpec> {
Ris3W::new(self, 3)
}
#[doc = "Bit 4 - Raw interrupt status bit 4"]
#[inline(always)]
pub fn ris4(&mut self) -> Ris4W<RisSpec> {
Ris4W::new(self, 4)
}
#[doc = "Bit 5 - Raw interrupt status bit 5"]
#[inline(always)]
pub fn ris5(&mut self) -> Ris5W<RisSpec> {
Ris5W::new(self, 5)
}
#[doc = "Bit 6 - Raw interrupt status bit 6"]
#[inline(always)]
pub fn ris6(&mut self) -> Ris6W<RisSpec> {
Ris6W::new(self, 6)
}
#[doc = "Bit 7 - Raw interrupt status bit 7"]
#[inline(always)]
pub fn ris7(&mut self) -> Ris7W<RisSpec> {
Ris7W::new(self, 7)
}
}
#[doc = "Raw interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`ris::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ris::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RisSpec;
impl crate::RegisterSpec for RisSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ris::R`](R) reader structure"]
impl crate::Readable for RisSpec {}
#[doc = "`write(|w| ..)` method takes [`ris::W`](W) writer structure"]
impl crate::Writable for RisSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets RIS to value 0"]
impl crate::Resettable for RisSpec {}
}
#[doc = "MIS (rw) register accessor: Masked interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`mis::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mis::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mis`] module"]
#[doc(alias = "MIS")]
pub type Mis = crate::Reg<mis::MisSpec>;
#[doc = "Masked interrupt status register"]
pub mod mis {
#[doc = "Register `MIS` reader"]
pub type R = crate::R<MisSpec>;
#[doc = "Register `MIS` writer"]
pub type W = crate::W<MisSpec>;
#[doc = "Field `MIS0` reader - Masked interrupt status bit 0"]
pub type Mis0R = crate::BitReader;
#[doc = "Field `MIS0` writer - Masked interrupt status bit 0"]
pub type Mis0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MIS1` reader - Masked interrupt status bit 1"]
pub type Mis1R = crate::BitReader;
#[doc = "Field `MIS1` writer - Masked interrupt status bit 1"]
pub type Mis1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MIS2` reader - Masked interrupt status bit 2"]
pub type Mis2R = crate::BitReader;
#[doc = "Field `MIS2` writer - Masked interrupt status bit 2"]
pub type Mis2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MIS3` reader - Masked interrupt status bit 3"]
pub type Mis3R = crate::BitReader;
#[doc = "Field `MIS3` writer - Masked interrupt status bit 3"]
pub type Mis3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MIS4` reader - Masked interrupt status bit 4"]
pub type Mis4R = crate::BitReader;
#[doc = "Field `MIS4` writer - Masked interrupt status bit 4"]
pub type Mis4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MIS5` reader - Masked interrupt status bit 5"]
pub type Mis5R = crate::BitReader;
#[doc = "Field `MIS5` writer - Masked interrupt status bit 5"]
pub type Mis5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MIS6` reader - Masked interrupt status bit 6"]
pub type Mis6R = crate::BitReader;
#[doc = "Field `MIS6` writer - Masked interrupt status bit 6"]
pub type Mis6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MIS7` reader - Masked interrupt status bit 7"]
pub type Mis7R = crate::BitReader;
#[doc = "Field `MIS7` writer - Masked interrupt status bit 7"]
pub type Mis7W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - Masked interrupt status bit 0"]
#[inline(always)]
pub fn mis0(&self) -> Mis0R {
Mis0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Masked interrupt status bit 1"]
#[inline(always)]
pub fn mis1(&self) -> Mis1R {
Mis1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Masked interrupt status bit 2"]
#[inline(always)]
pub fn mis2(&self) -> Mis2R {
Mis2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Masked interrupt status bit 3"]
#[inline(always)]
pub fn mis3(&self) -> Mis3R {
Mis3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Masked interrupt status bit 4"]
#[inline(always)]
pub fn mis4(&self) -> Mis4R {
Mis4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Masked interrupt status bit 5"]
#[inline(always)]
pub fn mis5(&self) -> Mis5R {
Mis5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Masked interrupt status bit 6"]
#[inline(always)]
pub fn mis6(&self) -> Mis6R {
Mis6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Masked interrupt status bit 7"]
#[inline(always)]
pub fn mis7(&self) -> Mis7R {
Mis7R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Masked interrupt status bit 0"]
#[inline(always)]
pub fn mis0(&mut self) -> Mis0W<MisSpec> {
Mis0W::new(self, 0)
}
#[doc = "Bit 1 - Masked interrupt status bit 1"]
#[inline(always)]
pub fn mis1(&mut self) -> Mis1W<MisSpec> {
Mis1W::new(self, 1)
}
#[doc = "Bit 2 - Masked interrupt status bit 2"]
#[inline(always)]
pub fn mis2(&mut self) -> Mis2W<MisSpec> {
Mis2W::new(self, 2)
}
#[doc = "Bit 3 - Masked interrupt status bit 3"]
#[inline(always)]
pub fn mis3(&mut self) -> Mis3W<MisSpec> {
Mis3W::new(self, 3)
}
#[doc = "Bit 4 - Masked interrupt status bit 4"]
#[inline(always)]
pub fn mis4(&mut self) -> Mis4W<MisSpec> {
Mis4W::new(self, 4)
}
#[doc = "Bit 5 - Masked interrupt status bit 5"]
#[inline(always)]
pub fn mis5(&mut self) -> Mis5W<MisSpec> {
Mis5W::new(self, 5)
}
#[doc = "Bit 6 - Masked interrupt status bit 6"]
#[inline(always)]
pub fn mis6(&mut self) -> Mis6W<MisSpec> {
Mis6W::new(self, 6)
}
#[doc = "Bit 7 - Masked interrupt status bit 7"]
#[inline(always)]
pub fn mis7(&mut self) -> Mis7W<MisSpec> {
Mis7W::new(self, 7)
}
}
#[doc = "Masked interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`mis::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mis::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MisSpec;
impl crate::RegisterSpec for MisSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`mis::R`](R) reader structure"]
impl crate::Readable for MisSpec {}
#[doc = "`write(|w| ..)` method takes [`mis::W`](W) writer structure"]
impl crate::Writable for MisSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets MIS to value 0"]
impl crate::Resettable for MisSpec {}
}
#[doc = "IC (rw) register accessor: Interrupt clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`ic::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ic`] module"]
#[doc(alias = "IC")]
pub type Ic = crate::Reg<ic::IcSpec>;
#[doc = "Interrupt clear register"]
pub mod ic {
#[doc = "Register `IC` reader"]
pub type R = crate::R<IcSpec>;
#[doc = "Register `IC` writer"]
pub type W = crate::W<IcSpec>;
#[doc = "Field `IC0` reader - Interrupt clear bit 0"]
pub type Ic0R = crate::BitReader;
#[doc = "Field `IC0` writer - Interrupt clear bit 0"]
pub type Ic0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IC1` reader - Interrupt clear bit 1"]
pub type Ic1R = crate::BitReader;
#[doc = "Field `IC1` writer - Interrupt clear bit 1"]
pub type Ic1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IC2` reader - Interrupt clear bit 2"]
pub type Ic2R = crate::BitReader;
#[doc = "Field `IC2` writer - Interrupt clear bit 2"]
pub type Ic2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IC3` reader - Interrupt clear bit 3"]
pub type Ic3R = crate::BitReader;
#[doc = "Field `IC3` writer - Interrupt clear bit 3"]
pub type Ic3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IC4` reader - Interrupt clear bit 4"]
pub type Ic4R = crate::BitReader;
#[doc = "Field `IC4` writer - Interrupt clear bit 4"]
pub type Ic4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IC5` reader - Interrupt clear bit 5"]
pub type Ic5R = crate::BitReader;
#[doc = "Field `IC5` writer - Interrupt clear bit 5"]
pub type Ic5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IC6` reader - Interrupt clear bit 6"]
pub type Ic6R = crate::BitReader;
#[doc = "Field `IC6` writer - Interrupt clear bit 6"]
pub type Ic6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IC7` reader - Interrupt clear bit 7"]
pub type Ic7R = crate::BitReader;
#[doc = "Field `IC7` writer - Interrupt clear bit 7"]
pub type Ic7W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - Interrupt clear bit 0"]
#[inline(always)]
pub fn ic0(&self) -> Ic0R {
Ic0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Interrupt clear bit 1"]
#[inline(always)]
pub fn ic1(&self) -> Ic1R {
Ic1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Interrupt clear bit 2"]
#[inline(always)]
pub fn ic2(&self) -> Ic2R {
Ic2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Interrupt clear bit 3"]
#[inline(always)]
pub fn ic3(&self) -> Ic3R {
Ic3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Interrupt clear bit 4"]
#[inline(always)]
pub fn ic4(&self) -> Ic4R {
Ic4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Interrupt clear bit 5"]
#[inline(always)]
pub fn ic5(&self) -> Ic5R {
Ic5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Interrupt clear bit 6"]
#[inline(always)]
pub fn ic6(&self) -> Ic6R {
Ic6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Interrupt clear bit 7"]
#[inline(always)]
pub fn ic7(&self) -> Ic7R {
Ic7R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Interrupt clear bit 0"]
#[inline(always)]
pub fn ic0(&mut self) -> Ic0W<IcSpec> {
Ic0W::new(self, 0)
}
#[doc = "Bit 1 - Interrupt clear bit 1"]
#[inline(always)]
pub fn ic1(&mut self) -> Ic1W<IcSpec> {
Ic1W::new(self, 1)
}
#[doc = "Bit 2 - Interrupt clear bit 2"]
#[inline(always)]
pub fn ic2(&mut self) -> Ic2W<IcSpec> {
Ic2W::new(self, 2)
}
#[doc = "Bit 3 - Interrupt clear bit 3"]
#[inline(always)]
pub fn ic3(&mut self) -> Ic3W<IcSpec> {
Ic3W::new(self, 3)
}
#[doc = "Bit 4 - Interrupt clear bit 4"]
#[inline(always)]
pub fn ic4(&mut self) -> Ic4W<IcSpec> {
Ic4W::new(self, 4)
}
#[doc = "Bit 5 - Interrupt clear bit 5"]
#[inline(always)]
pub fn ic5(&mut self) -> Ic5W<IcSpec> {
Ic5W::new(self, 5)
}
#[doc = "Bit 6 - Interrupt clear bit 6"]
#[inline(always)]
pub fn ic6(&mut self) -> Ic6W<IcSpec> {
Ic6W::new(self, 6)
}
#[doc = "Bit 7 - Interrupt clear bit 7"]
#[inline(always)]
pub fn ic7(&mut self) -> Ic7W<IcSpec> {
Ic7W::new(self, 7)
}
}
#[doc = "Interrupt clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`ic::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IcSpec;
impl crate::RegisterSpec for IcSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ic::R`](R) reader structure"]
impl crate::Readable for IcSpec {}
#[doc = "`write(|w| ..)` method takes [`ic::W`](W) writer structure"]
impl crate::Writable for IcSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets IC to value 0"]
impl crate::Resettable for IcSpec {}
}
#[doc = "AFSEL (rw) register accessor: Mode control select register\n\nYou can [`read`](crate::Reg::read) this register and get [`afsel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`afsel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@afsel`] module"]
#[doc(alias = "AFSEL")]
pub type Afsel = crate::Reg<afsel::AfselSpec>;
#[doc = "Mode control select register"]
pub mod afsel {
#[doc = "Register `AFSEL` reader"]
pub type R = crate::R<AfselSpec>;
#[doc = "Register `AFSEL` writer"]
pub type W = crate::W<AfselSpec>;
#[doc = "Mode control select bit 0\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Afsel0 {
#[doc = "0: Software Mode"]
SoftwareMode = 0,
#[doc = "1: Hardware Mode"]
HardwareMode = 1,
}
impl From<Afsel0> for bool {
#[inline(always)]
fn from(variant: Afsel0) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `AFSEL0` reader - Mode control select bit 0"]
pub type Afsel0R = crate::BitReader<Afsel0>;
impl Afsel0R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Afsel0 {
match self.bits {
false => Afsel0::SoftwareMode,
true => Afsel0::HardwareMode,
}
}
#[doc = "Software Mode"]
#[inline(always)]
pub fn is_software_mode(&self) -> bool {
*self == Afsel0::SoftwareMode
}
#[doc = "Hardware Mode"]
#[inline(always)]
pub fn is_hardware_mode(&self) -> bool {
*self == Afsel0::HardwareMode
}
}
#[doc = "Field `AFSEL0` writer - Mode control select bit 0"]
pub type Afsel0W<'a, REG> = crate::BitWriter<'a, REG, Afsel0>;
impl<'a, REG> Afsel0W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Software Mode"]
#[inline(always)]
pub fn software_mode(self) -> &'a mut crate::W<REG> {
self.variant(Afsel0::SoftwareMode)
}
#[doc = "Hardware Mode"]
#[inline(always)]
pub fn hardware_mode(self) -> &'a mut crate::W<REG> {
self.variant(Afsel0::HardwareMode)
}
}
#[doc = "Mode control select bit 1\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Afsel1 {
#[doc = "0: Software Mode"]
SoftwareMode = 0,
#[doc = "1: Hardware Mode"]
HardwareMode = 1,
}
impl From<Afsel1> for bool {
#[inline(always)]
fn from(variant: Afsel1) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `AFSEL1` reader - Mode control select bit 1"]
pub type Afsel1R = crate::BitReader<Afsel1>;
impl Afsel1R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Afsel1 {
match self.bits {
false => Afsel1::SoftwareMode,
true => Afsel1::HardwareMode,
}
}
#[doc = "Software Mode"]
#[inline(always)]
pub fn is_software_mode(&self) -> bool {
*self == Afsel1::SoftwareMode
}
#[doc = "Hardware Mode"]
#[inline(always)]
pub fn is_hardware_mode(&self) -> bool {
*self == Afsel1::HardwareMode
}
}
#[doc = "Field `AFSEL1` writer - Mode control select bit 1"]
pub type Afsel1W<'a, REG> = crate::BitWriter<'a, REG, Afsel1>;
impl<'a, REG> Afsel1W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Software Mode"]
#[inline(always)]
pub fn software_mode(self) -> &'a mut crate::W<REG> {
self.variant(Afsel1::SoftwareMode)
}
#[doc = "Hardware Mode"]
#[inline(always)]
pub fn hardware_mode(self) -> &'a mut crate::W<REG> {
self.variant(Afsel1::HardwareMode)
}
}
#[doc = "Mode control select bit 2\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Afsel2 {
#[doc = "0: Software Mode"]
SoftwareMode = 0,
#[doc = "1: Hardware Mode"]
HardwareMode = 1,
}
impl From<Afsel2> for bool {
#[inline(always)]
fn from(variant: Afsel2) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `AFSEL2` reader - Mode control select bit 2"]
pub type Afsel2R = crate::BitReader<Afsel2>;
impl Afsel2R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Afsel2 {
match self.bits {
false => Afsel2::SoftwareMode,
true => Afsel2::HardwareMode,
}
}
#[doc = "Software Mode"]
#[inline(always)]
pub fn is_software_mode(&self) -> bool {
*self == Afsel2::SoftwareMode
}
#[doc = "Hardware Mode"]
#[inline(always)]
pub fn is_hardware_mode(&self) -> bool {
*self == Afsel2::HardwareMode
}
}
#[doc = "Field `AFSEL2` writer - Mode control select bit 2"]
pub type Afsel2W<'a, REG> = crate::BitWriter<'a, REG, Afsel2>;
impl<'a, REG> Afsel2W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Software Mode"]
#[inline(always)]
pub fn software_mode(self) -> &'a mut crate::W<REG> {
self.variant(Afsel2::SoftwareMode)
}
#[doc = "Hardware Mode"]
#[inline(always)]
pub fn hardware_mode(self) -> &'a mut crate::W<REG> {
self.variant(Afsel2::HardwareMode)
}
}
#[doc = "Mode control select bit 3\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Afsel3 {
#[doc = "0: Software Mode"]
SoftwareMode = 0,
#[doc = "1: Hardware Mode"]
HardwareMode = 1,
}
impl From<Afsel3> for bool {
#[inline(always)]
fn from(variant: Afsel3) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `AFSEL3` reader - Mode control select bit 3"]
pub type Afsel3R = crate::BitReader<Afsel3>;
impl Afsel3R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Afsel3 {
match self.bits {
false => Afsel3::SoftwareMode,
true => Afsel3::HardwareMode,
}
}
#[doc = "Software Mode"]
#[inline(always)]
pub fn is_software_mode(&self) -> bool {
*self == Afsel3::SoftwareMode
}
#[doc = "Hardware Mode"]
#[inline(always)]
pub fn is_hardware_mode(&self) -> bool {
*self == Afsel3::HardwareMode
}
}
#[doc = "Field `AFSEL3` writer - Mode control select bit 3"]
pub type Afsel3W<'a, REG> = crate::BitWriter<'a, REG, Afsel3>;
impl<'a, REG> Afsel3W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Software Mode"]
#[inline(always)]
pub fn software_mode(self) -> &'a mut crate::W<REG> {
self.variant(Afsel3::SoftwareMode)
}
#[doc = "Hardware Mode"]
#[inline(always)]
pub fn hardware_mode(self) -> &'a mut crate::W<REG> {
self.variant(Afsel3::HardwareMode)
}
}
#[doc = "Mode control select bit 4\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Afsel4 {
#[doc = "0: Software Mode"]
SoftwareMode = 0,
#[doc = "1: Hardware Mode"]
HardwareMode = 1,
}
impl From<Afsel4> for bool {
#[inline(always)]
fn from(variant: Afsel4) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `AFSEL4` reader - Mode control select bit 4"]
pub type Afsel4R = crate::BitReader<Afsel4>;
impl Afsel4R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Afsel4 {
match self.bits {
false => Afsel4::SoftwareMode,
true => Afsel4::HardwareMode,
}
}
#[doc = "Software Mode"]
#[inline(always)]
pub fn is_software_mode(&self) -> bool {
*self == Afsel4::SoftwareMode
}
#[doc = "Hardware Mode"]
#[inline(always)]
pub fn is_hardware_mode(&self) -> bool {
*self == Afsel4::HardwareMode
}
}
#[doc = "Field `AFSEL4` writer - Mode control select bit 4"]
pub type Afsel4W<'a, REG> = crate::BitWriter<'a, REG, Afsel4>;
impl<'a, REG> Afsel4W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Software Mode"]
#[inline(always)]
pub fn software_mode(self) -> &'a mut crate::W<REG> {
self.variant(Afsel4::SoftwareMode)
}
#[doc = "Hardware Mode"]
#[inline(always)]
pub fn hardware_mode(self) -> &'a mut crate::W<REG> {
self.variant(Afsel4::HardwareMode)
}
}
#[doc = "Mode control select bit 5\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Afsel5 {
#[doc = "0: Software Mode"]
SoftwareMode = 0,
#[doc = "1: Hardware Mode"]
HardwareMode = 1,
}
impl From<Afsel5> for bool {
#[inline(always)]
fn from(variant: Afsel5) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `AFSEL5` reader - Mode control select bit 5"]
pub type Afsel5R = crate::BitReader<Afsel5>;
impl Afsel5R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Afsel5 {
match self.bits {
false => Afsel5::SoftwareMode,
true => Afsel5::HardwareMode,
}
}
#[doc = "Software Mode"]
#[inline(always)]
pub fn is_software_mode(&self) -> bool {
*self == Afsel5::SoftwareMode
}
#[doc = "Hardware Mode"]
#[inline(always)]
pub fn is_hardware_mode(&self) -> bool {
*self == Afsel5::HardwareMode
}
}
#[doc = "Field `AFSEL5` writer - Mode control select bit 5"]
pub type Afsel5W<'a, REG> = crate::BitWriter<'a, REG, Afsel5>;
impl<'a, REG> Afsel5W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Software Mode"]
#[inline(always)]
pub fn software_mode(self) -> &'a mut crate::W<REG> {
self.variant(Afsel5::SoftwareMode)
}
#[doc = "Hardware Mode"]
#[inline(always)]
pub fn hardware_mode(self) -> &'a mut crate::W<REG> {
self.variant(Afsel5::HardwareMode)
}
}
#[doc = "Mode control select bit 6\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Afsel6 {
#[doc = "0: Software Mode"]
SoftwareMode = 0,
#[doc = "1: Hardware Mode"]
HardwareMode = 1,
}
impl From<Afsel6> for bool {
#[inline(always)]
fn from(variant: Afsel6) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `AFSEL6` reader - Mode control select bit 6"]
pub type Afsel6R = crate::BitReader<Afsel6>;
impl Afsel6R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Afsel6 {
match self.bits {
false => Afsel6::SoftwareMode,
true => Afsel6::HardwareMode,
}
}
#[doc = "Software Mode"]
#[inline(always)]
pub fn is_software_mode(&self) -> bool {
*self == Afsel6::SoftwareMode
}
#[doc = "Hardware Mode"]
#[inline(always)]
pub fn is_hardware_mode(&self) -> bool {
*self == Afsel6::HardwareMode
}
}
#[doc = "Field `AFSEL6` writer - Mode control select bit 6"]
pub type Afsel6W<'a, REG> = crate::BitWriter<'a, REG, Afsel6>;
impl<'a, REG> Afsel6W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Software Mode"]
#[inline(always)]
pub fn software_mode(self) -> &'a mut crate::W<REG> {
self.variant(Afsel6::SoftwareMode)
}
#[doc = "Hardware Mode"]
#[inline(always)]
pub fn hardware_mode(self) -> &'a mut crate::W<REG> {
self.variant(Afsel6::HardwareMode)
}
}
#[doc = "Mode control select bit 7\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Afsel7 {
#[doc = "0: Software Mode"]
SoftwareMode = 0,
#[doc = "1: Hardware Mode"]
HardwareMode = 1,
}
impl From<Afsel7> for bool {
#[inline(always)]
fn from(variant: Afsel7) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `AFSEL7` reader - Mode control select bit 7"]
pub type Afsel7R = crate::BitReader<Afsel7>;
impl Afsel7R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Afsel7 {
match self.bits {
false => Afsel7::SoftwareMode,
true => Afsel7::HardwareMode,
}
}
#[doc = "Software Mode"]
#[inline(always)]
pub fn is_software_mode(&self) -> bool {
*self == Afsel7::SoftwareMode
}
#[doc = "Hardware Mode"]
#[inline(always)]
pub fn is_hardware_mode(&self) -> bool {
*self == Afsel7::HardwareMode
}
}
#[doc = "Field `AFSEL7` writer - Mode control select bit 7"]
pub type Afsel7W<'a, REG> = crate::BitWriter<'a, REG, Afsel7>;
impl<'a, REG> Afsel7W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Software Mode"]
#[inline(always)]
pub fn software_mode(self) -> &'a mut crate::W<REG> {
self.variant(Afsel7::SoftwareMode)
}
#[doc = "Hardware Mode"]
#[inline(always)]
pub fn hardware_mode(self) -> &'a mut crate::W<REG> {
self.variant(Afsel7::HardwareMode)
}
}
impl R {
#[doc = "Bit 0 - Mode control select bit 0"]
#[inline(always)]
pub fn afsel0(&self) -> Afsel0R {
Afsel0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Mode control select bit 1"]
#[inline(always)]
pub fn afsel1(&self) -> Afsel1R {
Afsel1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Mode control select bit 2"]
#[inline(always)]
pub fn afsel2(&self) -> Afsel2R {
Afsel2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Mode control select bit 3"]
#[inline(always)]
pub fn afsel3(&self) -> Afsel3R {
Afsel3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Mode control select bit 4"]
#[inline(always)]
pub fn afsel4(&self) -> Afsel4R {
Afsel4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Mode control select bit 5"]
#[inline(always)]
pub fn afsel5(&self) -> Afsel5R {
Afsel5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Mode control select bit 6"]
#[inline(always)]
pub fn afsel6(&self) -> Afsel6R {
Afsel6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Mode control select bit 7"]
#[inline(always)]
pub fn afsel7(&self) -> Afsel7R {
Afsel7R::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Mode control select bit 0"]
#[inline(always)]
pub fn afsel0(&mut self) -> Afsel0W<AfselSpec> {
Afsel0W::new(self, 0)
}
#[doc = "Bit 1 - Mode control select bit 1"]
#[inline(always)]
pub fn afsel1(&mut self) -> Afsel1W<AfselSpec> {
Afsel1W::new(self, 1)
}
#[doc = "Bit 2 - Mode control select bit 2"]
#[inline(always)]
pub fn afsel2(&mut self) -> Afsel2W<AfselSpec> {
Afsel2W::new(self, 2)
}
#[doc = "Bit 3 - Mode control select bit 3"]
#[inline(always)]
pub fn afsel3(&mut self) -> Afsel3W<AfselSpec> {
Afsel3W::new(self, 3)
}
#[doc = "Bit 4 - Mode control select bit 4"]
#[inline(always)]
pub fn afsel4(&mut self) -> Afsel4W<AfselSpec> {
Afsel4W::new(self, 4)
}
#[doc = "Bit 5 - Mode control select bit 5"]
#[inline(always)]
pub fn afsel5(&mut self) -> Afsel5W<AfselSpec> {
Afsel5W::new(self, 5)
}
#[doc = "Bit 6 - Mode control select bit 6"]
#[inline(always)]
pub fn afsel6(&mut self) -> Afsel6W<AfselSpec> {
Afsel6W::new(self, 6)
}
#[doc = "Bit 7 - Mode control select bit 7"]
#[inline(always)]
pub fn afsel7(&mut self) -> Afsel7W<AfselSpec> {
Afsel7W::new(self, 7)
}
}
#[doc = "Mode control select register\n\nYou can [`read`](crate::Reg::read) this register and get [`afsel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`afsel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AfselSpec;
impl crate::RegisterSpec for AfselSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`afsel::R`](R) reader structure"]
impl crate::Readable for AfselSpec {}
#[doc = "`write(|w| ..)` method takes [`afsel::W`](W) writer structure"]
impl crate::Writable for AfselSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets AFSEL to value 0"]
impl crate::Resettable for AfselSpec {}
}
}
#[doc = "GPIO registers"]
pub type Gpio1 = crate::Periph<gpio0::RegisterBlock, 0x4001_5000>;
impl core::fmt::Debug for Gpio1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Gpio1").finish()
}
}
#[doc = "GPIO registers"]
pub use self::gpio0 as gpio1;
#[doc = "GPIO registers"]
pub type Gpio2 = crate::Periph<gpio0::RegisterBlock, 0x4001_6000>;
impl core::fmt::Debug for Gpio2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Gpio2").finish()
}
}
#[doc = "GPIO registers"]
pub use self::gpio0 as gpio2;
#[doc = "GPIO registers"]
pub type Gpio3 = crate::Periph<gpio0::RegisterBlock, 0x4001_7000>;
impl core::fmt::Debug for Gpio3 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Gpio3").finish()
}
}
#[doc = "GPIO registers"]
pub use self::gpio0 as gpio3;
#[doc = "GPIO registers"]
pub type Gpio4 = crate::Periph<gpio0::RegisterBlock, 0x4001_8000>;
impl core::fmt::Debug for Gpio4 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Gpio4").finish()
}
}
#[doc = "GPIO registers"]
pub use self::gpio0 as gpio4;
#[doc = "GPIO registers"]
pub type Gpio5 = crate::Periph<gpio0::RegisterBlock, 0x4001_9000>;
impl core::fmt::Debug for Gpio5 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Gpio5").finish()
}
}
#[doc = "GPIO registers"]
pub use self::gpio0 as gpio5;
#[doc = "GPIO registers"]
pub type Gpio6 = crate::Periph<gpio0::RegisterBlock, 0x4001_a000>;
impl core::fmt::Debug for Gpio6 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Gpio6").finish()
}
}
#[doc = "GPIO registers"]
pub use self::gpio0 as gpio6;
#[doc = "GPIO registers"]
pub type Gpio7 = crate::Periph<gpio0::RegisterBlock, 0x4001_b000>;
impl core::fmt::Debug for Gpio7 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Gpio7").finish()
}
}
#[doc = "GPIO registers"]
pub use self::gpio0 as gpio7;
#[doc = "GPIO registers"]
pub type Gpio8 = crate::Periph<gpio0::RegisterBlock, 0x4001_c000>;
impl core::fmt::Debug for Gpio8 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Gpio8").finish()
}
}
#[doc = "GPIO registers"]
pub use self::gpio0 as gpio8;
#[doc = "GPIO registers"]
pub type Gpio9 = crate::Periph<gpio0::RegisterBlock, 0x4001_d000>;
impl core::fmt::Debug for Gpio9 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Gpio9").finish()
}
}
#[doc = "GPIO registers"]
pub use self::gpio0 as gpio9;
#[doc = "TIMER registers"]
pub type Timer0 = crate::Periph<timer0::RegisterBlock, 0x4001_e000>;
impl core::fmt::Debug for Timer0 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Timer0").finish()
}
}
#[doc = "TIMER registers"]
pub mod timer0 {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
timer1load: Timer1load,
timer1value: Timer1value,
timer1ctrl: Timer1ctrl,
timer1int_clr: Timer1intClr,
timer1ris: Timer1ris,
timer1mis: Timer1mis,
timer1bgl: Timer1bgl,
_reserved7: [u8; 0x04],
timer2load: Timer2load,
timer2value: Timer2value,
timer2ctrl: Timer2ctrl,
timer2int_clr: Timer2intClr,
timer2ris: Timer2ris,
timer2mis: Timer2mis,
timer2bgl: Timer2bgl,
}
impl RegisterBlock {
#[doc = "0x00 - Load Register"]
#[inline(always)]
pub const fn timer1load(&self) -> &Timer1load {
&self.timer1load
}
#[doc = "0x04 - Current Value Register"]
#[inline(always)]
pub const fn timer1value(&self) -> &Timer1value {
&self.timer1value
}
#[doc = "0x08 - Control Register"]
#[inline(always)]
pub const fn timer1ctrl(&self) -> &Timer1ctrl {
&self.timer1ctrl
}
#[doc = "0x0c - Interrupt Clear Register"]
#[inline(always)]
pub const fn timer1int_clr(&self) -> &Timer1intClr {
&self.timer1int_clr
}
#[doc = "0x10 - Raw Interrupt Status Register"]
#[inline(always)]
pub const fn timer1ris(&self) -> &Timer1ris {
&self.timer1ris
}
#[doc = "0x14 - Masked Interrupt Status Register"]
#[inline(always)]
pub const fn timer1mis(&self) -> &Timer1mis {
&self.timer1mis
}
#[doc = "0x18 - Background Load Register"]
#[inline(always)]
pub const fn timer1bgl(&self) -> &Timer1bgl {
&self.timer1bgl
}
#[doc = "0x20 - Load Register"]
#[inline(always)]
pub const fn timer2load(&self) -> &Timer2load {
&self.timer2load
}
#[doc = "0x24 - Current Value Register"]
#[inline(always)]
pub const fn timer2value(&self) -> &Timer2value {
&self.timer2value
}
#[doc = "0x28 - Control Register"]
#[inline(always)]
pub const fn timer2ctrl(&self) -> &Timer2ctrl {
&self.timer2ctrl
}
#[doc = "0x2c - Interrupt Clear Register"]
#[inline(always)]
pub const fn timer2int_clr(&self) -> &Timer2intClr {
&self.timer2int_clr
}
#[doc = "0x30 - Raw Interrupt Status Register"]
#[inline(always)]
pub const fn timer2ris(&self) -> &Timer2ris {
&self.timer2ris
}
#[doc = "0x34 - Masked Interrupt Status Register"]
#[inline(always)]
pub const fn timer2mis(&self) -> &Timer2mis {
&self.timer2mis
}
#[doc = "0x38 - Background Load Register"]
#[inline(always)]
pub const fn timer2bgl(&self) -> &Timer2bgl {
&self.timer2bgl
}
}
#[doc = "Timer1Load (rw) register accessor: Load Register\n\nYou can [`read`](crate::Reg::read) this register and get [`timer1load::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer1load::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timer1load`] module"]
#[doc(alias = "Timer1Load")]
pub type Timer1load = crate::Reg<timer1load::Timer1loadSpec>;
#[doc = "Load Register"]
pub mod timer1load {
#[doc = "Register `Timer1Load` reader"]
pub type R = crate::R<Timer1loadSpec>;
#[doc = "Register `Timer1Load` writer"]
pub type W = crate::W<Timer1loadSpec>;
#[doc = "Field `Timer1Load` reader - Load Register"]
pub type Timer1loadR = crate::FieldReader<u32>;
#[doc = "Field `Timer1Load` writer - Load Register"]
pub type Timer1loadW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - Load Register"]
#[inline(always)]
pub fn timer1load(&self) -> Timer1loadR {
Timer1loadR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - Load Register"]
#[inline(always)]
pub fn timer1load(&mut self) -> Timer1loadW<Timer1loadSpec> {
Timer1loadW::new(self, 0)
}
}
#[doc = "Load Register\n\nYou can [`read`](crate::Reg::read) this register and get [`timer1load::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer1load::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Timer1loadSpec;
impl crate::RegisterSpec for Timer1loadSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`timer1load::R`](R) reader structure"]
impl crate::Readable for Timer1loadSpec {}
#[doc = "`write(|w| ..)` method takes [`timer1load::W`](W) writer structure"]
impl crate::Writable for Timer1loadSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets Timer1Load to value 0"]
impl crate::Resettable for Timer1loadSpec {}
}
#[doc = "Timer1Value (r) register accessor: Current Value Register\n\nYou can [`read`](crate::Reg::read) this register and get [`timer1value::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timer1value`] module"]
#[doc(alias = "Timer1Value")]
pub type Timer1value = crate::Reg<timer1value::Timer1valueSpec>;
#[doc = "Current Value Register"]
pub mod timer1value {
#[doc = "Register `Timer1Value` reader"]
pub type R = crate::R<Timer1valueSpec>;
#[doc = "Field `Timer1Value` reader - Current Value Register"]
pub type Timer1valueR = crate::FieldReader<u32>;
impl R {
#[doc = "Bits 0:31 - Current Value Register"]
#[inline(always)]
pub fn timer1value(&self) -> Timer1valueR {
Timer1valueR::new(self.bits)
}
}
#[doc = "Current Value Register\n\nYou can [`read`](crate::Reg::read) this register and get [`timer1value::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Timer1valueSpec;
impl crate::RegisterSpec for Timer1valueSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`timer1value::R`](R) reader structure"]
impl crate::Readable for Timer1valueSpec {}
#[doc = "`reset()` method sets Timer1Value to value 0"]
impl crate::Resettable for Timer1valueSpec {}
}
#[doc = "Timer1Ctrl (rw) register accessor: Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`timer1ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer1ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timer1ctrl`] module"]
#[doc(alias = "Timer1Ctrl")]
pub type Timer1ctrl = crate::Reg<timer1ctrl::Timer1ctrlSpec>;
#[doc = "Control Register"]
pub mod timer1ctrl {
#[doc = "Register `Timer1Ctrl` reader"]
pub type R = crate::R<Timer1ctrlSpec>;
#[doc = "Register `Timer1Ctrl` writer"]
pub type W = crate::W<Timer1ctrlSpec>;
#[doc = "Field `OneShot` reader - One shot mode"]
pub type OneShotR = crate::BitReader;
#[doc = "Field `OneShot` writer - One shot mode"]
pub type OneShotW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Timer Size\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum TimerSize {
#[doc = "0: 16-bit"]
_16bit = 0,
#[doc = "1: 32-bit"]
_32bit = 1,
}
impl From<TimerSize> for bool {
#[inline(always)]
fn from(variant: TimerSize) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `TimerSize` reader - Timer Size"]
pub type TimerSizeR = crate::BitReader<TimerSize>;
impl TimerSizeR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> TimerSize {
match self.bits {
false => TimerSize::_16bit,
true => TimerSize::_32bit,
}
}
#[doc = "16-bit"]
#[inline(always)]
pub fn is_16bit(&self) -> bool {
*self == TimerSize::_16bit
}
#[doc = "32-bit"]
#[inline(always)]
pub fn is_32bit(&self) -> bool {
*self == TimerSize::_32bit
}
}
#[doc = "Field `TimerSize` writer - Timer Size"]
pub type TimerSizeW<'a, REG> = crate::BitWriter<'a, REG, TimerSize>;
impl<'a, REG> TimerSizeW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "16-bit"]
#[inline(always)]
pub fn _16bit(self) -> &'a mut crate::W<REG> {
self.variant(TimerSize::_16bit)
}
#[doc = "32-bit"]
#[inline(always)]
pub fn _32bit(self) -> &'a mut crate::W<REG> {
self.variant(TimerSize::_32bit)
}
}
#[doc = "Prescaler bits\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum TimerPre {
#[doc = "0: Div 1"]
Div1 = 0,
#[doc = "1: Div 16"]
Div16 = 1,
#[doc = "2: Div 256"]
Div256 = 2,
}
impl From<TimerPre> for u8 {
#[inline(always)]
fn from(variant: TimerPre) -> Self {
variant as _
}
}
impl crate::FieldSpec for TimerPre {
type Ux = u8;
}
impl crate::IsEnum for TimerPre {}
#[doc = "Field `TimerPre` reader - Prescaler bits"]
pub type TimerPreR = crate::FieldReader<TimerPre>;
impl TimerPreR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<TimerPre> {
match self.bits {
0 => Some(TimerPre::Div1),
1 => Some(TimerPre::Div16),
2 => Some(TimerPre::Div256),
_ => None,
}
}
#[doc = "Div 1"]
#[inline(always)]
pub fn is_div1(&self) -> bool {
*self == TimerPre::Div1
}
#[doc = "Div 16"]
#[inline(always)]
pub fn is_div16(&self) -> bool {
*self == TimerPre::Div16
}
#[doc = "Div 256"]
#[inline(always)]
pub fn is_div256(&self) -> bool {
*self == TimerPre::Div256
}
}
#[doc = "Field `TimerPre` writer - Prescaler bits"]
pub type TimerPreW<'a, REG> = crate::FieldWriter<'a, REG, 2, TimerPre>;
impl<'a, REG> TimerPreW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Div 1"]
#[inline(always)]
pub fn div1(self) -> &'a mut crate::W<REG> {
self.variant(TimerPre::Div1)
}
#[doc = "Div 16"]
#[inline(always)]
pub fn div16(self) -> &'a mut crate::W<REG> {
self.variant(TimerPre::Div16)
}
#[doc = "Div 256"]
#[inline(always)]
pub fn div256(self) -> &'a mut crate::W<REG> {
self.variant(TimerPre::Div256)
}
}
#[doc = "Field `IntEnable` reader - Interrupt enable"]
pub type IntEnableR = crate::BitReader;
#[doc = "Field `IntEnable` writer - Interrupt enable"]
pub type IntEnableW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Timer Mode\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum TimerMode {
#[doc = "0: Free-running"]
Freerunning = 0,
#[doc = "1: Periodic"]
Periodic = 1,
}
impl From<TimerMode> for bool {
#[inline(always)]
fn from(variant: TimerMode) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `TimerMode` reader - Timer Mode"]
pub type TimerModeR = crate::BitReader<TimerMode>;
impl TimerModeR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> TimerMode {
match self.bits {
false => TimerMode::Freerunning,
true => TimerMode::Periodic,
}
}
#[doc = "Free-running"]
#[inline(always)]
pub fn is_freerunning(&self) -> bool {
*self == TimerMode::Freerunning
}
#[doc = "Periodic"]
#[inline(always)]
pub fn is_periodic(&self) -> bool {
*self == TimerMode::Periodic
}
}
#[doc = "Field `TimerMode` writer - Timer Mode"]
pub type TimerModeW<'a, REG> = crate::BitWriter<'a, REG, TimerMode>;
impl<'a, REG> TimerModeW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Free-running"]
#[inline(always)]
pub fn freerunning(self) -> &'a mut crate::W<REG> {
self.variant(TimerMode::Freerunning)
}
#[doc = "Periodic"]
#[inline(always)]
pub fn periodic(self) -> &'a mut crate::W<REG> {
self.variant(TimerMode::Periodic)
}
}
#[doc = "Field `TimerEn` reader - Timer Enable"]
pub type TimerEnR = crate::BitReader;
#[doc = "Field `TimerEn` writer - Timer Enable"]
pub type TimerEnW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - One shot mode"]
#[inline(always)]
pub fn one_shot(&self) -> OneShotR {
OneShotR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Timer Size"]
#[inline(always)]
pub fn timer_size(&self) -> TimerSizeR {
TimerSizeR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bits 2:3 - Prescaler bits"]
#[inline(always)]
pub fn timer_pre(&self) -> TimerPreR {
TimerPreR::new(((self.bits >> 2) & 3) as u8)
}
#[doc = "Bit 5 - Interrupt enable"]
#[inline(always)]
pub fn int_enable(&self) -> IntEnableR {
IntEnableR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Timer Mode"]
#[inline(always)]
pub fn timer_mode(&self) -> TimerModeR {
TimerModeR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Timer Enable"]
#[inline(always)]
pub fn timer_en(&self) -> TimerEnR {
TimerEnR::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - One shot mode"]
#[inline(always)]
pub fn one_shot(&mut self) -> OneShotW<Timer1ctrlSpec> {
OneShotW::new(self, 0)
}
#[doc = "Bit 1 - Timer Size"]
#[inline(always)]
pub fn timer_size(&mut self) -> TimerSizeW<Timer1ctrlSpec> {
TimerSizeW::new(self, 1)
}
#[doc = "Bits 2:3 - Prescaler bits"]
#[inline(always)]
pub fn timer_pre(&mut self) -> TimerPreW<Timer1ctrlSpec> {
TimerPreW::new(self, 2)
}
#[doc = "Bit 5 - Interrupt enable"]
#[inline(always)]
pub fn int_enable(&mut self) -> IntEnableW<Timer1ctrlSpec> {
IntEnableW::new(self, 5)
}
#[doc = "Bit 6 - Timer Mode"]
#[inline(always)]
pub fn timer_mode(&mut self) -> TimerModeW<Timer1ctrlSpec> {
TimerModeW::new(self, 6)
}
#[doc = "Bit 7 - Timer Enable"]
#[inline(always)]
pub fn timer_en(&mut self) -> TimerEnW<Timer1ctrlSpec> {
TimerEnW::new(self, 7)
}
}
#[doc = "Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`timer1ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer1ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Timer1ctrlSpec;
impl crate::RegisterSpec for Timer1ctrlSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`timer1ctrl::R`](R) reader structure"]
impl crate::Readable for Timer1ctrlSpec {}
#[doc = "`write(|w| ..)` method takes [`timer1ctrl::W`](W) writer structure"]
impl crate::Writable for Timer1ctrlSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets Timer1Ctrl to value 0"]
impl crate::Resettable for Timer1ctrlSpec {}
}
#[doc = "Timer1IntClr (w) register accessor: Interrupt Clear Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer1int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timer1int_clr`] module"]
#[doc(alias = "Timer1IntClr")]
pub type Timer1intClr = crate::Reg<timer1int_clr::Timer1intClrSpec>;
#[doc = "Interrupt Clear Register"]
pub mod timer1int_clr {
#[doc = "Register `Timer1IntClr` writer"]
pub type W = crate::W<Timer1intClrSpec>;
#[doc = "Field `Timer1IntClr` writer - Interrupt Clear Register"]
pub type Timer1intClrW<'a, REG> = crate::BitWriter<'a, REG>;
impl W {
#[doc = "Bit 0 - Interrupt Clear Register"]
#[inline(always)]
pub fn timer1int_clr(&mut self) -> Timer1intClrW<Timer1intClrSpec> {
Timer1intClrW::new(self, 0)
}
}
#[doc = "Interrupt Clear Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer1int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Timer1intClrSpec;
impl crate::RegisterSpec for Timer1intClrSpec {
type Ux = u32;
}
#[doc = "`write(|w| ..)` method takes [`timer1int_clr::W`](W) writer structure"]
impl crate::Writable for Timer1intClrSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets Timer1IntClr to value 0"]
impl crate::Resettable for Timer1intClrSpec {}
}
#[doc = "Timer1RIS (r) register accessor: Raw Interrupt Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`timer1ris::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timer1ris`] module"]
#[doc(alias = "Timer1RIS")]
pub type Timer1ris = crate::Reg<timer1ris::Timer1risSpec>;
#[doc = "Raw Interrupt Status Register"]
pub mod timer1ris {
#[doc = "Register `Timer1RIS` reader"]
pub type R = crate::R<Timer1risSpec>;
#[doc = "Field `Timer1RIS` reader - Raw Interrupt Status Register"]
pub type Timer1risR = crate::BitReader;
impl R {
#[doc = "Bit 0 - Raw Interrupt Status Register"]
#[inline(always)]
pub fn timer1ris(&self) -> Timer1risR {
Timer1risR::new((self.bits & 1) != 0)
}
}
#[doc = "Raw Interrupt Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`timer1ris::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Timer1risSpec;
impl crate::RegisterSpec for Timer1risSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`timer1ris::R`](R) reader structure"]
impl crate::Readable for Timer1risSpec {}
#[doc = "`reset()` method sets Timer1RIS to value 0"]
impl crate::Resettable for Timer1risSpec {}
}
#[doc = "Timer1MIS (r) register accessor: Masked Interrupt Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`timer1mis::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timer1mis`] module"]
#[doc(alias = "Timer1MIS")]
pub type Timer1mis = crate::Reg<timer1mis::Timer1misSpec>;
#[doc = "Masked Interrupt Status Register"]
pub mod timer1mis {
#[doc = "Register `Timer1MIS` reader"]
pub type R = crate::R<Timer1misSpec>;
#[doc = "Field `Timer1MIS` reader - Masked Interrupt Status Register"]
pub type Timer1misR = crate::BitReader;
impl R {
#[doc = "Bit 0 - Masked Interrupt Status Register"]
#[inline(always)]
pub fn timer1mis(&self) -> Timer1misR {
Timer1misR::new((self.bits & 1) != 0)
}
}
#[doc = "Masked Interrupt Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`timer1mis::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Timer1misSpec;
impl crate::RegisterSpec for Timer1misSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`timer1mis::R`](R) reader structure"]
impl crate::Readable for Timer1misSpec {}
#[doc = "`reset()` method sets Timer1MIS to value 0"]
impl crate::Resettable for Timer1misSpec {}
}
#[doc = "Timer1BGL (rw) register accessor: Background Load Register\n\nYou can [`read`](crate::Reg::read) this register and get [`timer1bgl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer1bgl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timer1bgl`] module"]
#[doc(alias = "Timer1BGL")]
pub type Timer1bgl = crate::Reg<timer1bgl::Timer1bglSpec>;
#[doc = "Background Load Register"]
pub mod timer1bgl {
#[doc = "Register `Timer1BGL` reader"]
pub type R = crate::R<Timer1bglSpec>;
#[doc = "Register `Timer1BGL` writer"]
pub type W = crate::W<Timer1bglSpec>;
#[doc = "Field `Timer1BGL` reader - Background Load Register"]
pub type Timer1bglR = crate::FieldReader<u32>;
#[doc = "Field `Timer1BGL` writer - Background Load Register"]
pub type Timer1bglW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - Background Load Register"]
#[inline(always)]
pub fn timer1bgl(&self) -> Timer1bglR {
Timer1bglR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - Background Load Register"]
#[inline(always)]
pub fn timer1bgl(&mut self) -> Timer1bglW<Timer1bglSpec> {
Timer1bglW::new(self, 0)
}
}
#[doc = "Background Load Register\n\nYou can [`read`](crate::Reg::read) this register and get [`timer1bgl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer1bgl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Timer1bglSpec;
impl crate::RegisterSpec for Timer1bglSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`timer1bgl::R`](R) reader structure"]
impl crate::Readable for Timer1bglSpec {}
#[doc = "`write(|w| ..)` method takes [`timer1bgl::W`](W) writer structure"]
impl crate::Writable for Timer1bglSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets Timer1BGL to value 0"]
impl crate::Resettable for Timer1bglSpec {}
}
#[doc = "Timer2Load (rw) register accessor: Load Register\n\nYou can [`read`](crate::Reg::read) this register and get [`timer2load::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer2load::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timer2load`] module"]
#[doc(alias = "Timer2Load")]
pub type Timer2load = crate::Reg<timer2load::Timer2loadSpec>;
#[doc = "Load Register"]
pub mod timer2load {
#[doc = "Register `Timer2Load` reader"]
pub type R = crate::R<Timer2loadSpec>;
#[doc = "Register `Timer2Load` writer"]
pub type W = crate::W<Timer2loadSpec>;
#[doc = "Field `Timer2Load` reader - Load Register"]
pub type Timer2loadR = crate::FieldReader<u32>;
#[doc = "Field `Timer2Load` writer - Load Register"]
pub type Timer2loadW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - Load Register"]
#[inline(always)]
pub fn timer2load(&self) -> Timer2loadR {
Timer2loadR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - Load Register"]
#[inline(always)]
pub fn timer2load(&mut self) -> Timer2loadW<Timer2loadSpec> {
Timer2loadW::new(self, 0)
}
}
#[doc = "Load Register\n\nYou can [`read`](crate::Reg::read) this register and get [`timer2load::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer2load::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Timer2loadSpec;
impl crate::RegisterSpec for Timer2loadSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`timer2load::R`](R) reader structure"]
impl crate::Readable for Timer2loadSpec {}
#[doc = "`write(|w| ..)` method takes [`timer2load::W`](W) writer structure"]
impl crate::Writable for Timer2loadSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets Timer2Load to value 0"]
impl crate::Resettable for Timer2loadSpec {}
}
#[doc = "Timer2Value (r) register accessor: Current Value Register\n\nYou can [`read`](crate::Reg::read) this register and get [`timer2value::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timer2value`] module"]
#[doc(alias = "Timer2Value")]
pub type Timer2value = crate::Reg<timer2value::Timer2valueSpec>;
#[doc = "Current Value Register"]
pub mod timer2value {
#[doc = "Register `Timer2Value` reader"]
pub type R = crate::R<Timer2valueSpec>;
#[doc = "Field `Timer2Value` reader - Current Value Register"]
pub type Timer2valueR = crate::FieldReader<u32>;
impl R {
#[doc = "Bits 0:31 - Current Value Register"]
#[inline(always)]
pub fn timer2value(&self) -> Timer2valueR {
Timer2valueR::new(self.bits)
}
}
#[doc = "Current Value Register\n\nYou can [`read`](crate::Reg::read) this register and get [`timer2value::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Timer2valueSpec;
impl crate::RegisterSpec for Timer2valueSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`timer2value::R`](R) reader structure"]
impl crate::Readable for Timer2valueSpec {}
#[doc = "`reset()` method sets Timer2Value to value 0"]
impl crate::Resettable for Timer2valueSpec {}
}
#[doc = "Timer2Ctrl (rw) register accessor: Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`timer2ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer2ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timer2ctrl`] module"]
#[doc(alias = "Timer2Ctrl")]
pub type Timer2ctrl = crate::Reg<timer2ctrl::Timer2ctrlSpec>;
#[doc = "Control Register"]
pub mod timer2ctrl {
#[doc = "Register `Timer2Ctrl` reader"]
pub type R = crate::R<Timer2ctrlSpec>;
#[doc = "Register `Timer2Ctrl` writer"]
pub type W = crate::W<Timer2ctrlSpec>;
#[doc = "Field `OneShot` reader - One shot mode"]
pub type OneShotR = crate::BitReader;
#[doc = "Field `OneShot` writer - One shot mode"]
pub type OneShotW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Timer Size\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum TimerSize {
#[doc = "0: 16-bit"]
_16bit = 0,
#[doc = "1: 32-bit"]
_32bit = 1,
}
impl From<TimerSize> for bool {
#[inline(always)]
fn from(variant: TimerSize) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `TimerSize` reader - Timer Size"]
pub type TimerSizeR = crate::BitReader<TimerSize>;
impl TimerSizeR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> TimerSize {
match self.bits {
false => TimerSize::_16bit,
true => TimerSize::_32bit,
}
}
#[doc = "16-bit"]
#[inline(always)]
pub fn is_16bit(&self) -> bool {
*self == TimerSize::_16bit
}
#[doc = "32-bit"]
#[inline(always)]
pub fn is_32bit(&self) -> bool {
*self == TimerSize::_32bit
}
}
#[doc = "Field `TimerSize` writer - Timer Size"]
pub type TimerSizeW<'a, REG> = crate::BitWriter<'a, REG, TimerSize>;
impl<'a, REG> TimerSizeW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "16-bit"]
#[inline(always)]
pub fn _16bit(self) -> &'a mut crate::W<REG> {
self.variant(TimerSize::_16bit)
}
#[doc = "32-bit"]
#[inline(always)]
pub fn _32bit(self) -> &'a mut crate::W<REG> {
self.variant(TimerSize::_32bit)
}
}
#[doc = "Prescaler bits\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum TimerPre {
#[doc = "0: Div 1"]
Div1 = 0,
#[doc = "1: Div 16"]
Div16 = 1,
#[doc = "2: Div 256"]
Div256 = 2,
}
impl From<TimerPre> for u8 {
#[inline(always)]
fn from(variant: TimerPre) -> Self {
variant as _
}
}
impl crate::FieldSpec for TimerPre {
type Ux = u8;
}
impl crate::IsEnum for TimerPre {}
#[doc = "Field `TimerPre` reader - Prescaler bits"]
pub type TimerPreR = crate::FieldReader<TimerPre>;
impl TimerPreR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<TimerPre> {
match self.bits {
0 => Some(TimerPre::Div1),
1 => Some(TimerPre::Div16),
2 => Some(TimerPre::Div256),
_ => None,
}
}
#[doc = "Div 1"]
#[inline(always)]
pub fn is_div1(&self) -> bool {
*self == TimerPre::Div1
}
#[doc = "Div 16"]
#[inline(always)]
pub fn is_div16(&self) -> bool {
*self == TimerPre::Div16
}
#[doc = "Div 256"]
#[inline(always)]
pub fn is_div256(&self) -> bool {
*self == TimerPre::Div256
}
}
#[doc = "Field `TimerPre` writer - Prescaler bits"]
pub type TimerPreW<'a, REG> = crate::FieldWriter<'a, REG, 2, TimerPre>;
impl<'a, REG> TimerPreW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Div 1"]
#[inline(always)]
pub fn div1(self) -> &'a mut crate::W<REG> {
self.variant(TimerPre::Div1)
}
#[doc = "Div 16"]
#[inline(always)]
pub fn div16(self) -> &'a mut crate::W<REG> {
self.variant(TimerPre::Div16)
}
#[doc = "Div 256"]
#[inline(always)]
pub fn div256(self) -> &'a mut crate::W<REG> {
self.variant(TimerPre::Div256)
}
}
#[doc = "Field `IntEnable` reader - Interrupt enable"]
pub type IntEnableR = crate::BitReader;
#[doc = "Field `IntEnable` writer - Interrupt enable"]
pub type IntEnableW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Timer Mode\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum TimerMode {
#[doc = "0: Free-running"]
Freerunning = 0,
#[doc = "1: Periodic"]
Periodic = 1,
}
impl From<TimerMode> for bool {
#[inline(always)]
fn from(variant: TimerMode) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `TimerMode` reader - Timer Mode"]
pub type TimerModeR = crate::BitReader<TimerMode>;
impl TimerModeR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> TimerMode {
match self.bits {
false => TimerMode::Freerunning,
true => TimerMode::Periodic,
}
}
#[doc = "Free-running"]
#[inline(always)]
pub fn is_freerunning(&self) -> bool {
*self == TimerMode::Freerunning
}
#[doc = "Periodic"]
#[inline(always)]
pub fn is_periodic(&self) -> bool {
*self == TimerMode::Periodic
}
}
#[doc = "Field `TimerMode` writer - Timer Mode"]
pub type TimerModeW<'a, REG> = crate::BitWriter<'a, REG, TimerMode>;
impl<'a, REG> TimerModeW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Free-running"]
#[inline(always)]
pub fn freerunning(self) -> &'a mut crate::W<REG> {
self.variant(TimerMode::Freerunning)
}
#[doc = "Periodic"]
#[inline(always)]
pub fn periodic(self) -> &'a mut crate::W<REG> {
self.variant(TimerMode::Periodic)
}
}
#[doc = "Field `TimerEn` reader - Timer Enable"]
pub type TimerEnR = crate::BitReader;
#[doc = "Field `TimerEn` writer - Timer Enable"]
pub type TimerEnW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - One shot mode"]
#[inline(always)]
pub fn one_shot(&self) -> OneShotR {
OneShotR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Timer Size"]
#[inline(always)]
pub fn timer_size(&self) -> TimerSizeR {
TimerSizeR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bits 2:3 - Prescaler bits"]
#[inline(always)]
pub fn timer_pre(&self) -> TimerPreR {
TimerPreR::new(((self.bits >> 2) & 3) as u8)
}
#[doc = "Bit 5 - Interrupt enable"]
#[inline(always)]
pub fn int_enable(&self) -> IntEnableR {
IntEnableR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Timer Mode"]
#[inline(always)]
pub fn timer_mode(&self) -> TimerModeR {
TimerModeR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Timer Enable"]
#[inline(always)]
pub fn timer_en(&self) -> TimerEnR {
TimerEnR::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - One shot mode"]
#[inline(always)]
pub fn one_shot(&mut self) -> OneShotW<Timer2ctrlSpec> {
OneShotW::new(self, 0)
}
#[doc = "Bit 1 - Timer Size"]
#[inline(always)]
pub fn timer_size(&mut self) -> TimerSizeW<Timer2ctrlSpec> {
TimerSizeW::new(self, 1)
}
#[doc = "Bits 2:3 - Prescaler bits"]
#[inline(always)]
pub fn timer_pre(&mut self) -> TimerPreW<Timer2ctrlSpec> {
TimerPreW::new(self, 2)
}
#[doc = "Bit 5 - Interrupt enable"]
#[inline(always)]
pub fn int_enable(&mut self) -> IntEnableW<Timer2ctrlSpec> {
IntEnableW::new(self, 5)
}
#[doc = "Bit 6 - Timer Mode"]
#[inline(always)]
pub fn timer_mode(&mut self) -> TimerModeW<Timer2ctrlSpec> {
TimerModeW::new(self, 6)
}
#[doc = "Bit 7 - Timer Enable"]
#[inline(always)]
pub fn timer_en(&mut self) -> TimerEnW<Timer2ctrlSpec> {
TimerEnW::new(self, 7)
}
}
#[doc = "Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`timer2ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer2ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Timer2ctrlSpec;
impl crate::RegisterSpec for Timer2ctrlSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`timer2ctrl::R`](R) reader structure"]
impl crate::Readable for Timer2ctrlSpec {}
#[doc = "`write(|w| ..)` method takes [`timer2ctrl::W`](W) writer structure"]
impl crate::Writable for Timer2ctrlSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets Timer2Ctrl to value 0"]
impl crate::Resettable for Timer2ctrlSpec {}
}
#[doc = "Timer2IntClr (w) register accessor: Interrupt Clear Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer2int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timer2int_clr`] module"]
#[doc(alias = "Timer2IntClr")]
pub type Timer2intClr = crate::Reg<timer2int_clr::Timer2intClrSpec>;
#[doc = "Interrupt Clear Register"]
pub mod timer2int_clr {
#[doc = "Register `Timer2IntClr` writer"]
pub type W = crate::W<Timer2intClrSpec>;
#[doc = "Field `Timer2IntClr` writer - Interrupt Clear Register"]
pub type Timer2intClrW<'a, REG> = crate::BitWriter<'a, REG>;
impl W {
#[doc = "Bit 0 - Interrupt Clear Register"]
#[inline(always)]
pub fn timer2int_clr(&mut self) -> Timer2intClrW<Timer2intClrSpec> {
Timer2intClrW::new(self, 0)
}
}
#[doc = "Interrupt Clear Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer2int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Timer2intClrSpec;
impl crate::RegisterSpec for Timer2intClrSpec {
type Ux = u32;
}
#[doc = "`write(|w| ..)` method takes [`timer2int_clr::W`](W) writer structure"]
impl crate::Writable for Timer2intClrSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets Timer2IntClr to value 0"]
impl crate::Resettable for Timer2intClrSpec {}
}
#[doc = "Timer2RIS (r) register accessor: Raw Interrupt Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`timer2ris::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timer2ris`] module"]
#[doc(alias = "Timer2RIS")]
pub type Timer2ris = crate::Reg<timer2ris::Timer2risSpec>;
#[doc = "Raw Interrupt Status Register"]
pub mod timer2ris {
#[doc = "Register `Timer2RIS` reader"]
pub type R = crate::R<Timer2risSpec>;
#[doc = "Field `Timer2RIS` reader - Raw Interrupt Status Register"]
pub type Timer2risR = crate::BitReader;
impl R {
#[doc = "Bit 0 - Raw Interrupt Status Register"]
#[inline(always)]
pub fn timer2ris(&self) -> Timer2risR {
Timer2risR::new((self.bits & 1) != 0)
}
}
#[doc = "Raw Interrupt Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`timer2ris::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Timer2risSpec;
impl crate::RegisterSpec for Timer2risSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`timer2ris::R`](R) reader structure"]
impl crate::Readable for Timer2risSpec {}
#[doc = "`reset()` method sets Timer2RIS to value 0"]
impl crate::Resettable for Timer2risSpec {}
}
#[doc = "Timer2MIS (r) register accessor: Masked Interrupt Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`timer2mis::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timer2mis`] module"]
#[doc(alias = "Timer2MIS")]
pub type Timer2mis = crate::Reg<timer2mis::Timer2misSpec>;
#[doc = "Masked Interrupt Status Register"]
pub mod timer2mis {
#[doc = "Register `Timer2MIS` reader"]
pub type R = crate::R<Timer2misSpec>;
#[doc = "Field `Timer2MIS` reader - Masked Interrupt Status Register"]
pub type Timer2misR = crate::BitReader;
impl R {
#[doc = "Bit 0 - Masked Interrupt Status Register"]
#[inline(always)]
pub fn timer2mis(&self) -> Timer2misR {
Timer2misR::new((self.bits & 1) != 0)
}
}
#[doc = "Masked Interrupt Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`timer2mis::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Timer2misSpec;
impl crate::RegisterSpec for Timer2misSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`timer2mis::R`](R) reader structure"]
impl crate::Readable for Timer2misSpec {}
#[doc = "`reset()` method sets Timer2MIS to value 0"]
impl crate::Resettable for Timer2misSpec {}
}
#[doc = "Timer2BGL (rw) register accessor: Background Load Register\n\nYou can [`read`](crate::Reg::read) this register and get [`timer2bgl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer2bgl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timer2bgl`] module"]
#[doc(alias = "Timer2BGL")]
pub type Timer2bgl = crate::Reg<timer2bgl::Timer2bglSpec>;
#[doc = "Background Load Register"]
pub mod timer2bgl {
#[doc = "Register `Timer2BGL` reader"]
pub type R = crate::R<Timer2bglSpec>;
#[doc = "Register `Timer2BGL` writer"]
pub type W = crate::W<Timer2bglSpec>;
#[doc = "Field `Timer2BGL` reader - Background Load Register"]
pub type Timer2bglR = crate::FieldReader<u32>;
#[doc = "Field `Timer2BGL` writer - Background Load Register"]
pub type Timer2bglW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - Background Load Register"]
#[inline(always)]
pub fn timer2bgl(&self) -> Timer2bglR {
Timer2bglR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - Background Load Register"]
#[inline(always)]
pub fn timer2bgl(&mut self) -> Timer2bglW<Timer2bglSpec> {
Timer2bglW::new(self, 0)
}
}
#[doc = "Background Load Register\n\nYou can [`read`](crate::Reg::read) this register and get [`timer2bgl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer2bgl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Timer2bglSpec;
impl crate::RegisterSpec for Timer2bglSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`timer2bgl::R`](R) reader structure"]
impl crate::Readable for Timer2bglSpec {}
#[doc = "`write(|w| ..)` method takes [`timer2bgl::W`](W) writer structure"]
impl crate::Writable for Timer2bglSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets Timer2BGL to value 0"]
impl crate::Resettable for Timer2bglSpec {}
}
}
#[doc = "TIMER registers"]
pub type Timer1 = crate::Periph<timer0::RegisterBlock, 0x4001_f000>;
impl core::fmt::Debug for Timer1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Timer1").finish()
}
}
#[doc = "TIMER registers"]
pub use self::timer0 as timer1;
#[doc = "GPTIMER registers"]
pub type Gptimer0 = crate::Periph<gptimer0::RegisterBlock, 0x4002_0000>;
impl core::fmt::Debug for Gptimer0 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Gptimer0").finish()
}
}
#[doc = "GPTIMER registers"]
pub mod gptimer0 {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
cr1: Cr1,
cr2: Cr2,
smcr: Smcr,
dier: Dier,
sr: Sr,
egr: Egr,
_reserved_6_ccmr0: [u8; 0x04],
_reserved_7_ccmr1: [u8; 0x04],
ccer: Ccer,
cnt: Cnt,
psc: Psc,
arr: Arr,
rcr: Rcr,
ccr0: Ccr0,
ccr1: Ccr1,
ccr2: Ccr2,
ccr3: Ccr3,
bdtr: Bdtr,
}
impl RegisterBlock {
#[doc = "0x00 - Control register 1"]
#[inline(always)]
pub const fn cr1(&self) -> &Cr1 {
&self.cr1
}
#[doc = "0x04 - Control register 2"]
#[inline(always)]
pub const fn cr2(&self) -> &Cr2 {
&self.cr2
}
#[doc = "0x08 - Slave mode control register"]
#[inline(always)]
pub const fn smcr(&self) -> &Smcr {
&self.smcr
}
#[doc = "0x0c - DMA/interrupt enable register"]
#[inline(always)]
pub const fn dier(&self) -> &Dier {
&self.dier
}
#[doc = "0x10 - Status register"]
#[inline(always)]
pub const fn sr(&self) -> &Sr {
&self.sr
}
#[doc = "0x14 - Event generation register"]
#[inline(always)]
pub const fn egr(&self) -> &Egr {
&self.egr
}
#[doc = "0x18 - Capture/compare mode register 0"]
#[inline(always)]
pub const fn ccmr0_output(&self) -> &Ccmr0Output {
unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(24).cast() }
}
#[doc = "0x18 - Capture/compare mode register 0"]
#[inline(always)]
pub const fn ccmr0_input(&self) -> &Ccmr0Input {
unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(24).cast() }
}
#[doc = "0x1c - Capture/compare mode register 1"]
#[inline(always)]
pub const fn ccmr1_output(&self) -> &Ccmr1Output {
unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(28).cast() }
}
#[doc = "0x1c - Capture/compare mode register 1"]
#[inline(always)]
pub const fn ccmr1_input(&self) -> &Ccmr1Input {
unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(28).cast() }
}
#[doc = "0x20 - Capture/compare enable register"]
#[inline(always)]
pub const fn ccer(&self) -> &Ccer {
&self.ccer
}
#[doc = "0x24 - Counter"]
#[inline(always)]
pub const fn cnt(&self) -> &Cnt {
&self.cnt
}
#[doc = "0x28 - Prescaler"]
#[inline(always)]
pub const fn psc(&self) -> &Psc {
&self.psc
}
#[doc = "0x2c - Auto reload register"]
#[inline(always)]
pub const fn arr(&self) -> &Arr {
&self.arr
}
#[doc = "0x30 - Repetition counter register"]
#[inline(always)]
pub const fn rcr(&self) -> &Rcr {
&self.rcr
}
#[doc = "0x34 - Capture compare register 0"]
#[inline(always)]
pub const fn ccr0(&self) -> &Ccr0 {
&self.ccr0
}
#[doc = "0x38 - Capture compare register 1"]
#[inline(always)]
pub const fn ccr1(&self) -> &Ccr1 {
&self.ccr1
}
#[doc = "0x3c - Capture compare register 2"]
#[inline(always)]
pub const fn ccr2(&self) -> &Ccr2 {
&self.ccr2
}
#[doc = "0x40 - Capture compare register 3"]
#[inline(always)]
pub const fn ccr3(&self) -> &Ccr3 {
&self.ccr3
}
#[doc = "0x44 - Break and dead time register"]
#[inline(always)]
pub const fn bdtr(&self) -> &Bdtr {
&self.bdtr
}
}
#[doc = "CR1 (rw) register accessor: Control register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`cr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr1`] module"]
#[doc(alias = "CR1")]
pub type Cr1 = crate::Reg<cr1::Cr1Spec>;
#[doc = "Control register 1"]
pub mod cr1 {
#[doc = "Register `CR1` reader"]
pub type R = crate::R<Cr1Spec>;
#[doc = "Register `CR1` writer"]
pub type W = crate::W<Cr1Spec>;
#[doc = "Field `CEN` reader - Counter enable"]
pub type CenR = crate::BitReader;
#[doc = "Field `CEN` writer - Counter enable"]
pub type CenW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Update disable\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Udis {
#[doc = "0: UEV enabled"]
Uevenabled = 0,
#[doc = "1: UEV disabled"]
Uevdisabled = 1,
}
impl From<Udis> for bool {
#[inline(always)]
fn from(variant: Udis) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `UDIS` reader - Update disable"]
pub type UdisR = crate::BitReader<Udis>;
impl UdisR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Udis {
match self.bits {
false => Udis::Uevenabled,
true => Udis::Uevdisabled,
}
}
#[doc = "UEV enabled"]
#[inline(always)]
pub fn is_uevenabled(&self) -> bool {
*self == Udis::Uevenabled
}
#[doc = "UEV disabled"]
#[inline(always)]
pub fn is_uevdisabled(&self) -> bool {
*self == Udis::Uevdisabled
}
}
#[doc = "Field `UDIS` writer - Update disable"]
pub type UdisW<'a, REG> = crate::BitWriter<'a, REG, Udis>;
impl<'a, REG> UdisW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "UEV enabled"]
#[inline(always)]
pub fn uevenabled(self) -> &'a mut crate::W<REG> {
self.variant(Udis::Uevenabled)
}
#[doc = "UEV disabled"]
#[inline(always)]
pub fn uevdisabled(self) -> &'a mut crate::W<REG> {
self.variant(Udis::Uevdisabled)
}
}
#[doc = "Update request source\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Urs {
#[doc = "0: All sources"]
Allsources = 0,
#[doc = "1: Counter overflow/underflow"]
Counteroverflowunderflow = 1,
}
impl From<Urs> for bool {
#[inline(always)]
fn from(variant: Urs) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `URS` reader - Update request source"]
pub type UrsR = crate::BitReader<Urs>;
impl UrsR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Urs {
match self.bits {
false => Urs::Allsources,
true => Urs::Counteroverflowunderflow,
}
}
#[doc = "All sources"]
#[inline(always)]
pub fn is_allsources(&self) -> bool {
*self == Urs::Allsources
}
#[doc = "Counter overflow/underflow"]
#[inline(always)]
pub fn is_counteroverflowunderflow(&self) -> bool {
*self == Urs::Counteroverflowunderflow
}
}
#[doc = "Field `URS` writer - Update request source"]
pub type UrsW<'a, REG> = crate::BitWriter<'a, REG, Urs>;
impl<'a, REG> UrsW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "All sources"]
#[inline(always)]
pub fn allsources(self) -> &'a mut crate::W<REG> {
self.variant(Urs::Allsources)
}
#[doc = "Counter overflow/underflow"]
#[inline(always)]
pub fn counteroverflowunderflow(self) -> &'a mut crate::W<REG> {
self.variant(Urs::Counteroverflowunderflow)
}
}
#[doc = "Field `OPM` reader - One pulse mode"]
pub type OpmR = crate::BitReader;
#[doc = "Field `OPM` writer - One pulse mode"]
pub type OpmW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Direction\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Dir {
#[doc = "0: Up counter"]
Upcounter = 0,
#[doc = "1: Down counter"]
Downcounter = 1,
}
impl From<Dir> for bool {
#[inline(always)]
fn from(variant: Dir) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `DIR` reader - Direction"]
pub type DirR = crate::BitReader<Dir>;
impl DirR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Dir {
match self.bits {
false => Dir::Upcounter,
true => Dir::Downcounter,
}
}
#[doc = "Up counter"]
#[inline(always)]
pub fn is_upcounter(&self) -> bool {
*self == Dir::Upcounter
}
#[doc = "Down counter"]
#[inline(always)]
pub fn is_downcounter(&self) -> bool {
*self == Dir::Downcounter
}
}
#[doc = "Field `DIR` writer - Direction"]
pub type DirW<'a, REG> = crate::BitWriter<'a, REG, Dir>;
impl<'a, REG> DirW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Up counter"]
#[inline(always)]
pub fn upcounter(self) -> &'a mut crate::W<REG> {
self.variant(Dir::Upcounter)
}
#[doc = "Down counter"]
#[inline(always)]
pub fn downcounter(self) -> &'a mut crate::W<REG> {
self.variant(Dir::Downcounter)
}
}
#[doc = "Center-aligned mode selection\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Cms {
#[doc = "0: Edge-aligned"]
Edgealigned = 0,
#[doc = "1: Center-aligned 1"]
Centeraligned1 = 1,
#[doc = "2: Center-aligned 2"]
Centeraligned2 = 2,
#[doc = "3: Center-aligned 3"]
Centeraligned3 = 3,
}
impl From<Cms> for u8 {
#[inline(always)]
fn from(variant: Cms) -> Self {
variant as _
}
}
impl crate::FieldSpec for Cms {
type Ux = u8;
}
impl crate::IsEnum for Cms {}
#[doc = "Field `CMS` reader - Center-aligned mode selection"]
pub type CmsR = crate::FieldReader<Cms>;
impl CmsR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Cms {
match self.bits {
0 => Cms::Edgealigned,
1 => Cms::Centeraligned1,
2 => Cms::Centeraligned2,
3 => Cms::Centeraligned3,
_ => unreachable!(),
}
}
#[doc = "Edge-aligned"]
#[inline(always)]
pub fn is_edgealigned(&self) -> bool {
*self == Cms::Edgealigned
}
#[doc = "Center-aligned 1"]
#[inline(always)]
pub fn is_centeraligned1(&self) -> bool {
*self == Cms::Centeraligned1
}
#[doc = "Center-aligned 2"]
#[inline(always)]
pub fn is_centeraligned2(&self) -> bool {
*self == Cms::Centeraligned2
}
#[doc = "Center-aligned 3"]
#[inline(always)]
pub fn is_centeraligned3(&self) -> bool {
*self == Cms::Centeraligned3
}
}
#[doc = "Field `CMS` writer - Center-aligned mode selection"]
pub type CmsW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cms, crate::Safe>;
impl<'a, REG> CmsW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Edge-aligned"]
#[inline(always)]
pub fn edgealigned(self) -> &'a mut crate::W<REG> {
self.variant(Cms::Edgealigned)
}
#[doc = "Center-aligned 1"]
#[inline(always)]
pub fn centeraligned1(self) -> &'a mut crate::W<REG> {
self.variant(Cms::Centeraligned1)
}
#[doc = "Center-aligned 2"]
#[inline(always)]
pub fn centeraligned2(self) -> &'a mut crate::W<REG> {
self.variant(Cms::Centeraligned2)
}
#[doc = "Center-aligned 3"]
#[inline(always)]
pub fn centeraligned3(self) -> &'a mut crate::W<REG> {
self.variant(Cms::Centeraligned3)
}
}
#[doc = "Field `ARPE` reader - Auto-reload preload enable"]
pub type ArpeR = crate::BitReader;
#[doc = "Field `ARPE` writer - Auto-reload preload enable"]
pub type ArpeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Clock division\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Ckd {
#[doc = "0: Div 1"]
Div1 = 0,
#[doc = "1: Div 2"]
Div2 = 1,
#[doc = "2: Div 4"]
Div4 = 2,
#[doc = "3: Div 8"]
Div8 = 3,
}
impl From<Ckd> for u8 {
#[inline(always)]
fn from(variant: Ckd) -> Self {
variant as _
}
}
impl crate::FieldSpec for Ckd {
type Ux = u8;
}
impl crate::IsEnum for Ckd {}
#[doc = "Field `CKD` reader - Clock division"]
pub type CkdR = crate::FieldReader<Ckd>;
impl CkdR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Ckd {
match self.bits {
0 => Ckd::Div1,
1 => Ckd::Div2,
2 => Ckd::Div4,
3 => Ckd::Div8,
_ => unreachable!(),
}
}
#[doc = "Div 1"]
#[inline(always)]
pub fn is_div1(&self) -> bool {
*self == Ckd::Div1
}
#[doc = "Div 2"]
#[inline(always)]
pub fn is_div2(&self) -> bool {
*self == Ckd::Div2
}
#[doc = "Div 4"]
#[inline(always)]
pub fn is_div4(&self) -> bool {
*self == Ckd::Div4
}
#[doc = "Div 8"]
#[inline(always)]
pub fn is_div8(&self) -> bool {
*self == Ckd::Div8
}
}
#[doc = "Field `CKD` writer - Clock division"]
pub type CkdW<'a, REG> = crate::FieldWriter<'a, REG, 2, Ckd, crate::Safe>;
impl<'a, REG> CkdW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Div 1"]
#[inline(always)]
pub fn div1(self) -> &'a mut crate::W<REG> {
self.variant(Ckd::Div1)
}
#[doc = "Div 2"]
#[inline(always)]
pub fn div2(self) -> &'a mut crate::W<REG> {
self.variant(Ckd::Div2)
}
#[doc = "Div 4"]
#[inline(always)]
pub fn div4(self) -> &'a mut crate::W<REG> {
self.variant(Ckd::Div4)
}
#[doc = "Div 8"]
#[inline(always)]
pub fn div8(self) -> &'a mut crate::W<REG> {
self.variant(Ckd::Div8)
}
}
impl R {
#[doc = "Bit 0 - Counter enable"]
#[inline(always)]
pub fn cen(&self) -> CenR {
CenR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Update disable"]
#[inline(always)]
pub fn udis(&self) -> UdisR {
UdisR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Update request source"]
#[inline(always)]
pub fn urs(&self) -> UrsR {
UrsR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - One pulse mode"]
#[inline(always)]
pub fn opm(&self) -> OpmR {
OpmR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Direction"]
#[inline(always)]
pub fn dir(&self) -> DirR {
DirR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bits 5:6 - Center-aligned mode selection"]
#[inline(always)]
pub fn cms(&self) -> CmsR {
CmsR::new(((self.bits >> 5) & 3) as u8)
}
#[doc = "Bit 7 - Auto-reload preload enable"]
#[inline(always)]
pub fn arpe(&self) -> ArpeR {
ArpeR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:9 - Clock division"]
#[inline(always)]
pub fn ckd(&self) -> CkdR {
CkdR::new(((self.bits >> 8) & 3) as u8)
}
}
impl W {
#[doc = "Bit 0 - Counter enable"]
#[inline(always)]
pub fn cen(&mut self) -> CenW<Cr1Spec> {
CenW::new(self, 0)
}
#[doc = "Bit 1 - Update disable"]
#[inline(always)]
pub fn udis(&mut self) -> UdisW<Cr1Spec> {
UdisW::new(self, 1)
}
#[doc = "Bit 2 - Update request source"]
#[inline(always)]
pub fn urs(&mut self) -> UrsW<Cr1Spec> {
UrsW::new(self, 2)
}
#[doc = "Bit 3 - One pulse mode"]
#[inline(always)]
pub fn opm(&mut self) -> OpmW<Cr1Spec> {
OpmW::new(self, 3)
}
#[doc = "Bit 4 - Direction"]
#[inline(always)]
pub fn dir(&mut self) -> DirW<Cr1Spec> {
DirW::new(self, 4)
}
#[doc = "Bits 5:6 - Center-aligned mode selection"]
#[inline(always)]
pub fn cms(&mut self) -> CmsW<Cr1Spec> {
CmsW::new(self, 5)
}
#[doc = "Bit 7 - Auto-reload preload enable"]
#[inline(always)]
pub fn arpe(&mut self) -> ArpeW<Cr1Spec> {
ArpeW::new(self, 7)
}
#[doc = "Bits 8:9 - Clock division"]
#[inline(always)]
pub fn ckd(&mut self) -> CkdW<Cr1Spec> {
CkdW::new(self, 8)
}
}
#[doc = "Control register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`cr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cr1Spec;
impl crate::RegisterSpec for Cr1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cr1::R`](R) reader structure"]
impl crate::Readable for Cr1Spec {}
#[doc = "`write(|w| ..)` method takes [`cr1::W`](W) writer structure"]
impl crate::Writable for Cr1Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets CR1 to value 0"]
impl crate::Resettable for Cr1Spec {}
}
#[doc = "CR2 (rw) register accessor: Control register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`cr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr2`] module"]
#[doc(alias = "CR2")]
pub type Cr2 = crate::Reg<cr2::Cr2Spec>;
#[doc = "Control register 2"]
pub mod cr2 {
#[doc = "Register `CR2` reader"]
pub type R = crate::R<Cr2Spec>;
#[doc = "Register `CR2` writer"]
pub type W = crate::W<Cr2Spec>;
#[doc = "Field `CCPC` reader - Capture/Compare preloaded control"]
pub type CcpcR = crate::BitReader;
#[doc = "Field `CCPC` writer - Capture/Compare preloaded control"]
pub type CcpcW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Capture/Compare control update selection\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Ccus {
#[doc = "0: COMG"]
Comg = 0,
#[doc = "1: COMG and TRGI"]
ComgandTrgi = 1,
}
impl From<Ccus> for bool {
#[inline(always)]
fn from(variant: Ccus) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `CCUS` reader - Capture/Compare control update selection"]
pub type CcusR = crate::BitReader<Ccus>;
impl CcusR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Ccus {
match self.bits {
false => Ccus::Comg,
true => Ccus::ComgandTrgi,
}
}
#[doc = "COMG"]
#[inline(always)]
pub fn is_comg(&self) -> bool {
*self == Ccus::Comg
}
#[doc = "COMG and TRGI"]
#[inline(always)]
pub fn is_comgand_trgi(&self) -> bool {
*self == Ccus::ComgandTrgi
}
}
#[doc = "Field `CCUS` writer - Capture/Compare control update selection"]
pub type CcusW<'a, REG> = crate::BitWriter<'a, REG, Ccus>;
impl<'a, REG> CcusW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "COMG"]
#[inline(always)]
pub fn comg(self) -> &'a mut crate::W<REG> {
self.variant(Ccus::Comg)
}
#[doc = "COMG and TRGI"]
#[inline(always)]
pub fn comgand_trgi(self) -> &'a mut crate::W<REG> {
self.variant(Ccus::ComgandTrgi)
}
}
#[doc = "Capture/Compare DMA selection\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Ccds {
#[doc = "0: CCx"]
Ccx = 0,
#[doc = "1: Update"]
Update = 1,
}
impl From<Ccds> for bool {
#[inline(always)]
fn from(variant: Ccds) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `CCDS` reader - Capture/Compare DMA selection"]
pub type CcdsR = crate::BitReader<Ccds>;
impl CcdsR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Ccds {
match self.bits {
false => Ccds::Ccx,
true => Ccds::Update,
}
}
#[doc = "CCx"]
#[inline(always)]
pub fn is_ccx(&self) -> bool {
*self == Ccds::Ccx
}
#[doc = "Update"]
#[inline(always)]
pub fn is_update(&self) -> bool {
*self == Ccds::Update
}
}
#[doc = "Field `CCDS` writer - Capture/Compare DMA selection"]
pub type CcdsW<'a, REG> = crate::BitWriter<'a, REG, Ccds>;
impl<'a, REG> CcdsW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "CCx"]
#[inline(always)]
pub fn ccx(self) -> &'a mut crate::W<REG> {
self.variant(Ccds::Ccx)
}
#[doc = "Update"]
#[inline(always)]
pub fn update(self) -> &'a mut crate::W<REG> {
self.variant(Ccds::Update)
}
}
#[doc = "Master mode selection\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Mms {
#[doc = "0: Reset"]
Reset = 0,
#[doc = "1: Enable"]
Enable = 1,
#[doc = "2: Update"]
Update = 2,
#[doc = "3: Compare Pulse"]
ComparePulse = 3,
#[doc = "4: OC0REF"]
Oc0ref = 4,
#[doc = "5: OC1REF"]
Oc1ref = 5,
#[doc = "6: OC2REF"]
Oc2ref = 6,
#[doc = "7: OC3REF"]
Oc3ref = 7,
}
impl From<Mms> for u8 {
#[inline(always)]
fn from(variant: Mms) -> Self {
variant as _
}
}
impl crate::FieldSpec for Mms {
type Ux = u8;
}
impl crate::IsEnum for Mms {}
#[doc = "Field `MMS` reader - Master mode selection"]
pub type MmsR = crate::FieldReader<Mms>;
impl MmsR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Mms {
match self.bits {
0 => Mms::Reset,
1 => Mms::Enable,
2 => Mms::Update,
3 => Mms::ComparePulse,
4 => Mms::Oc0ref,
5 => Mms::Oc1ref,
6 => Mms::Oc2ref,
7 => Mms::Oc3ref,
_ => unreachable!(),
}
}
#[doc = "Reset"]
#[inline(always)]
pub fn is_reset(&self) -> bool {
*self == Mms::Reset
}
#[doc = "Enable"]
#[inline(always)]
pub fn is_enable(&self) -> bool {
*self == Mms::Enable
}
#[doc = "Update"]
#[inline(always)]
pub fn is_update(&self) -> bool {
*self == Mms::Update
}
#[doc = "Compare Pulse"]
#[inline(always)]
pub fn is_compare_pulse(&self) -> bool {
*self == Mms::ComparePulse
}
#[doc = "OC0REF"]
#[inline(always)]
pub fn is_oc0ref(&self) -> bool {
*self == Mms::Oc0ref
}
#[doc = "OC1REF"]
#[inline(always)]
pub fn is_oc1ref(&self) -> bool {
*self == Mms::Oc1ref
}
#[doc = "OC2REF"]
#[inline(always)]
pub fn is_oc2ref(&self) -> bool {
*self == Mms::Oc2ref
}
#[doc = "OC3REF"]
#[inline(always)]
pub fn is_oc3ref(&self) -> bool {
*self == Mms::Oc3ref
}
}
#[doc = "Field `MMS` writer - Master mode selection"]
pub type MmsW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mms, crate::Safe>;
impl<'a, REG> MmsW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Reset"]
#[inline(always)]
pub fn reset(self) -> &'a mut crate::W<REG> {
self.variant(Mms::Reset)
}
#[doc = "Enable"]
#[inline(always)]
pub fn enable(self) -> &'a mut crate::W<REG> {
self.variant(Mms::Enable)
}
#[doc = "Update"]
#[inline(always)]
pub fn update(self) -> &'a mut crate::W<REG> {
self.variant(Mms::Update)
}
#[doc = "Compare Pulse"]
#[inline(always)]
pub fn compare_pulse(self) -> &'a mut crate::W<REG> {
self.variant(Mms::ComparePulse)
}
#[doc = "OC0REF"]
#[inline(always)]
pub fn oc0ref(self) -> &'a mut crate::W<REG> {
self.variant(Mms::Oc0ref)
}
#[doc = "OC1REF"]
#[inline(always)]
pub fn oc1ref(self) -> &'a mut crate::W<REG> {
self.variant(Mms::Oc1ref)
}
#[doc = "OC2REF"]
#[inline(always)]
pub fn oc2ref(self) -> &'a mut crate::W<REG> {
self.variant(Mms::Oc2ref)
}
#[doc = "OC3REF"]
#[inline(always)]
pub fn oc3ref(self) -> &'a mut crate::W<REG> {
self.variant(Mms::Oc3ref)
}
}
#[doc = "TI0 selection\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Ti0s {
#[doc = "0: TI0"]
Ti0 = 0,
#[doc = "1: XOR of TI0/TI1/TI2"]
XorofTi0ti1ti2 = 1,
}
impl From<Ti0s> for bool {
#[inline(always)]
fn from(variant: Ti0s) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `TI0S` reader - TI0 selection"]
pub type Ti0sR = crate::BitReader<Ti0s>;
impl Ti0sR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Ti0s {
match self.bits {
false => Ti0s::Ti0,
true => Ti0s::XorofTi0ti1ti2,
}
}
#[doc = "TI0"]
#[inline(always)]
pub fn is_ti0(&self) -> bool {
*self == Ti0s::Ti0
}
#[doc = "XOR of TI0/TI1/TI2"]
#[inline(always)]
pub fn is_xorof_ti0ti1ti2(&self) -> bool {
*self == Ti0s::XorofTi0ti1ti2
}
}
#[doc = "Field `TI0S` writer - TI0 selection"]
pub type Ti0sW<'a, REG> = crate::BitWriter<'a, REG, Ti0s>;
impl<'a, REG> Ti0sW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "TI0"]
#[inline(always)]
pub fn ti0(self) -> &'a mut crate::W<REG> {
self.variant(Ti0s::Ti0)
}
#[doc = "XOR of TI0/TI1/TI2"]
#[inline(always)]
pub fn xorof_ti0ti1ti2(self) -> &'a mut crate::W<REG> {
self.variant(Ti0s::XorofTi0ti1ti2)
}
}
#[doc = "Field `OIS0` reader - OC0 idle state"]
pub type Ois0R = crate::BitReader;
#[doc = "Field `OIS0` writer - OC0 idle state"]
pub type Ois0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OIS0N` reader - OC0N idle state"]
pub type Ois0nR = crate::BitReader;
#[doc = "Field `OIS0N` writer - OC0N idle state"]
pub type Ois0nW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OIS1` reader - OC1 idle state"]
pub type Ois1R = crate::BitReader;
#[doc = "Field `OIS1` writer - OC1 idle state"]
pub type Ois1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OIS1N` reader - OC1N idle state"]
pub type Ois1nR = crate::BitReader;
#[doc = "Field `OIS1N` writer - OC1N idle state"]
pub type Ois1nW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OIS2` reader - OC2 idle state"]
pub type Ois2R = crate::BitReader;
#[doc = "Field `OIS2` writer - OC2 idle state"]
pub type Ois2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OIS2N` reader - OC2N idle state"]
pub type Ois2nR = crate::BitReader;
#[doc = "Field `OIS2N` writer - OC2N idle state"]
pub type Ois2nW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OIS4` reader - OC3 idle state"]
pub type Ois4R = crate::BitReader;
#[doc = "Field `OIS4` writer - OC3 idle state"]
pub type Ois4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OIS4N` reader - OC3N idle state"]
pub type Ois4nR = crate::BitReader;
#[doc = "Field `OIS4N` writer - OC3N idle state"]
pub type Ois4nW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - Capture/Compare preloaded control"]
#[inline(always)]
pub fn ccpc(&self) -> CcpcR {
CcpcR::new((self.bits & 1) != 0)
}
#[doc = "Bit 2 - Capture/Compare control update selection"]
#[inline(always)]
pub fn ccus(&self) -> CcusR {
CcusR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Capture/Compare DMA selection"]
#[inline(always)]
pub fn ccds(&self) -> CcdsR {
CcdsR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bits 4:6 - Master mode selection"]
#[inline(always)]
pub fn mms(&self) -> MmsR {
MmsR::new(((self.bits >> 4) & 7) as u8)
}
#[doc = "Bit 7 - TI0 selection"]
#[inline(always)]
pub fn ti0s(&self) -> Ti0sR {
Ti0sR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - OC0 idle state"]
#[inline(always)]
pub fn ois0(&self) -> Ois0R {
Ois0R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - OC0N idle state"]
#[inline(always)]
pub fn ois0n(&self) -> Ois0nR {
Ois0nR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - OC1 idle state"]
#[inline(always)]
pub fn ois1(&self) -> Ois1R {
Ois1R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - OC1N idle state"]
#[inline(always)]
pub fn ois1n(&self) -> Ois1nR {
Ois1nR::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12 - OC2 idle state"]
#[inline(always)]
pub fn ois2(&self) -> Ois2R {
Ois2R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13 - OC2N idle state"]
#[inline(always)]
pub fn ois2n(&self) -> Ois2nR {
Ois2nR::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - OC3 idle state"]
#[inline(always)]
pub fn ois4(&self) -> Ois4R {
Ois4R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15 - OC3N idle state"]
#[inline(always)]
pub fn ois4n(&self) -> Ois4nR {
Ois4nR::new(((self.bits >> 15) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Capture/Compare preloaded control"]
#[inline(always)]
pub fn ccpc(&mut self) -> CcpcW<Cr2Spec> {
CcpcW::new(self, 0)
}
#[doc = "Bit 2 - Capture/Compare control update selection"]
#[inline(always)]
pub fn ccus(&mut self) -> CcusW<Cr2Spec> {
CcusW::new(self, 2)
}
#[doc = "Bit 3 - Capture/Compare DMA selection"]
#[inline(always)]
pub fn ccds(&mut self) -> CcdsW<Cr2Spec> {
CcdsW::new(self, 3)
}
#[doc = "Bits 4:6 - Master mode selection"]
#[inline(always)]
pub fn mms(&mut self) -> MmsW<Cr2Spec> {
MmsW::new(self, 4)
}
#[doc = "Bit 7 - TI0 selection"]
#[inline(always)]
pub fn ti0s(&mut self) -> Ti0sW<Cr2Spec> {
Ti0sW::new(self, 7)
}
#[doc = "Bit 8 - OC0 idle state"]
#[inline(always)]
pub fn ois0(&mut self) -> Ois0W<Cr2Spec> {
Ois0W::new(self, 8)
}
#[doc = "Bit 9 - OC0N idle state"]
#[inline(always)]
pub fn ois0n(&mut self) -> Ois0nW<Cr2Spec> {
Ois0nW::new(self, 9)
}
#[doc = "Bit 10 - OC1 idle state"]
#[inline(always)]
pub fn ois1(&mut self) -> Ois1W<Cr2Spec> {
Ois1W::new(self, 10)
}
#[doc = "Bit 11 - OC1N idle state"]
#[inline(always)]
pub fn ois1n(&mut self) -> Ois1nW<Cr2Spec> {
Ois1nW::new(self, 11)
}
#[doc = "Bit 12 - OC2 idle state"]
#[inline(always)]
pub fn ois2(&mut self) -> Ois2W<Cr2Spec> {
Ois2W::new(self, 12)
}
#[doc = "Bit 13 - OC2N idle state"]
#[inline(always)]
pub fn ois2n(&mut self) -> Ois2nW<Cr2Spec> {
Ois2nW::new(self, 13)
}
#[doc = "Bit 14 - OC3 idle state"]
#[inline(always)]
pub fn ois4(&mut self) -> Ois4W<Cr2Spec> {
Ois4W::new(self, 14)
}
#[doc = "Bit 15 - OC3N idle state"]
#[inline(always)]
pub fn ois4n(&mut self) -> Ois4nW<Cr2Spec> {
Ois4nW::new(self, 15)
}
}
#[doc = "Control register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`cr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cr2Spec;
impl crate::RegisterSpec for Cr2Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cr2::R`](R) reader structure"]
impl crate::Readable for Cr2Spec {}
#[doc = "`write(|w| ..)` method takes [`cr2::W`](W) writer structure"]
impl crate::Writable for Cr2Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets CR2 to value 0"]
impl crate::Resettable for Cr2Spec {}
}
#[doc = "SMCR (rw) register accessor: Slave mode control register\n\nYou can [`read`](crate::Reg::read) this register and get [`smcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`smcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smcr`] module"]
#[doc(alias = "SMCR")]
pub type Smcr = crate::Reg<smcr::SmcrSpec>;
#[doc = "Slave mode control register"]
pub mod smcr {
#[doc = "Register `SMCR` reader"]
pub type R = crate::R<SmcrSpec>;
#[doc = "Register `SMCR` writer"]
pub type W = crate::W<SmcrSpec>;
#[doc = "Slave mode selection\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Sms {
#[doc = "0: Disabled"]
Disabled = 0,
#[doc = "1: Encoder 1"]
Encoder1 = 1,
#[doc = "2: Encoder 2"]
Encoder2 = 2,
#[doc = "3: Encoder 3"]
Encoder3 = 3,
#[doc = "4: Reset"]
Reset = 4,
#[doc = "5: Gated"]
Gated = 5,
#[doc = "6: Trigger"]
Trigger = 6,
#[doc = "7: External Clock 1"]
ExternalClock1 = 7,
}
impl From<Sms> for u8 {
#[inline(always)]
fn from(variant: Sms) -> Self {
variant as _
}
}
impl crate::FieldSpec for Sms {
type Ux = u8;
}
impl crate::IsEnum for Sms {}
#[doc = "Field `SMS` reader - Slave mode selection"]
pub type SmsR = crate::FieldReader<Sms>;
impl SmsR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Sms {
match self.bits {
0 => Sms::Disabled,
1 => Sms::Encoder1,
2 => Sms::Encoder2,
3 => Sms::Encoder3,
4 => Sms::Reset,
5 => Sms::Gated,
6 => Sms::Trigger,
7 => Sms::ExternalClock1,
_ => unreachable!(),
}
}
#[doc = "Disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == Sms::Disabled
}
#[doc = "Encoder 1"]
#[inline(always)]
pub fn is_encoder1(&self) -> bool {
*self == Sms::Encoder1
}
#[doc = "Encoder 2"]
#[inline(always)]
pub fn is_encoder2(&self) -> bool {
*self == Sms::Encoder2
}
#[doc = "Encoder 3"]
#[inline(always)]
pub fn is_encoder3(&self) -> bool {
*self == Sms::Encoder3
}
#[doc = "Reset"]
#[inline(always)]
pub fn is_reset(&self) -> bool {
*self == Sms::Reset
}
#[doc = "Gated"]
#[inline(always)]
pub fn is_gated(&self) -> bool {
*self == Sms::Gated
}
#[doc = "Trigger"]
#[inline(always)]
pub fn is_trigger(&self) -> bool {
*self == Sms::Trigger
}
#[doc = "External Clock 1"]
#[inline(always)]
pub fn is_external_clock1(&self) -> bool {
*self == Sms::ExternalClock1
}
}
#[doc = "Field `SMS` writer - Slave mode selection"]
pub type SmsW<'a, REG> = crate::FieldWriter<'a, REG, 3, Sms, crate::Safe>;
impl<'a, REG> SmsW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(Sms::Disabled)
}
#[doc = "Encoder 1"]
#[inline(always)]
pub fn encoder1(self) -> &'a mut crate::W<REG> {
self.variant(Sms::Encoder1)
}
#[doc = "Encoder 2"]
#[inline(always)]
pub fn encoder2(self) -> &'a mut crate::W<REG> {
self.variant(Sms::Encoder2)
}
#[doc = "Encoder 3"]
#[inline(always)]
pub fn encoder3(self) -> &'a mut crate::W<REG> {
self.variant(Sms::Encoder3)
}
#[doc = "Reset"]
#[inline(always)]
pub fn reset(self) -> &'a mut crate::W<REG> {
self.variant(Sms::Reset)
}
#[doc = "Gated"]
#[inline(always)]
pub fn gated(self) -> &'a mut crate::W<REG> {
self.variant(Sms::Gated)
}
#[doc = "Trigger"]
#[inline(always)]
pub fn trigger(self) -> &'a mut crate::W<REG> {
self.variant(Sms::Trigger)
}
#[doc = "External Clock 1"]
#[inline(always)]
pub fn external_clock1(self) -> &'a mut crate::W<REG> {
self.variant(Sms::ExternalClock1)
}
}
#[doc = "OCREF clear selection\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Occs {
#[doc = "0: OCREF_CLR"]
OcrefClr = 0,
#[doc = "1: ETRF"]
Etrf = 1,
}
impl From<Occs> for bool {
#[inline(always)]
fn from(variant: Occs) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `OCCS` reader - OCREF clear selection"]
pub type OccsR = crate::BitReader<Occs>;
impl OccsR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Occs {
match self.bits {
false => Occs::OcrefClr,
true => Occs::Etrf,
}
}
#[doc = "OCREF_CLR"]
#[inline(always)]
pub fn is_ocref_clr(&self) -> bool {
*self == Occs::OcrefClr
}
#[doc = "ETRF"]
#[inline(always)]
pub fn is_etrf(&self) -> bool {
*self == Occs::Etrf
}
}
#[doc = "Field `OCCS` writer - OCREF clear selection"]
pub type OccsW<'a, REG> = crate::BitWriter<'a, REG, Occs>;
impl<'a, REG> OccsW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "OCREF_CLR"]
#[inline(always)]
pub fn ocref_clr(self) -> &'a mut crate::W<REG> {
self.variant(Occs::OcrefClr)
}
#[doc = "ETRF"]
#[inline(always)]
pub fn etrf(self) -> &'a mut crate::W<REG> {
self.variant(Occs::Etrf)
}
}
#[doc = "Trigger selection\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Ts {
#[doc = "0: ITR0"]
Itr0 = 0,
#[doc = "1: ITR1"]
Itr1 = 1,
#[doc = "2: ITR2"]
Itr2 = 2,
#[doc = "3: ITR3"]
Itr3 = 3,
#[doc = "4: TI1F_ED"]
Ti1fEd = 4,
#[doc = "5: TI0FP0"]
Ti0fp0 = 5,
#[doc = "6: TI1FP1"]
Ti1fp1 = 6,
#[doc = "7: ETRF"]
Etrf = 7,
}
impl From<Ts> for u8 {
#[inline(always)]
fn from(variant: Ts) -> Self {
variant as _
}
}
impl crate::FieldSpec for Ts {
type Ux = u8;
}
impl crate::IsEnum for Ts {}
#[doc = "Field `TS` reader - Trigger selection"]
pub type TsR = crate::FieldReader<Ts>;
impl TsR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Ts {
match self.bits {
0 => Ts::Itr0,
1 => Ts::Itr1,
2 => Ts::Itr2,
3 => Ts::Itr3,
4 => Ts::Ti1fEd,
5 => Ts::Ti0fp0,
6 => Ts::Ti1fp1,
7 => Ts::Etrf,
_ => unreachable!(),
}
}
#[doc = "ITR0"]
#[inline(always)]
pub fn is_itr0(&self) -> bool {
*self == Ts::Itr0
}
#[doc = "ITR1"]
#[inline(always)]
pub fn is_itr1(&self) -> bool {
*self == Ts::Itr1
}
#[doc = "ITR2"]
#[inline(always)]
pub fn is_itr2(&self) -> bool {
*self == Ts::Itr2
}
#[doc = "ITR3"]
#[inline(always)]
pub fn is_itr3(&self) -> bool {
*self == Ts::Itr3
}
#[doc = "TI1F_ED"]
#[inline(always)]
pub fn is_ti1f_ed(&self) -> bool {
*self == Ts::Ti1fEd
}
#[doc = "TI0FP0"]
#[inline(always)]
pub fn is_ti0fp0(&self) -> bool {
*self == Ts::Ti0fp0
}
#[doc = "TI1FP1"]
#[inline(always)]
pub fn is_ti1fp1(&self) -> bool {
*self == Ts::Ti1fp1
}
#[doc = "ETRF"]
#[inline(always)]
pub fn is_etrf(&self) -> bool {
*self == Ts::Etrf
}
}
#[doc = "Field `TS` writer - Trigger selection"]
pub type TsW<'a, REG> = crate::FieldWriter<'a, REG, 3, Ts, crate::Safe>;
impl<'a, REG> TsW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "ITR0"]
#[inline(always)]
pub fn itr0(self) -> &'a mut crate::W<REG> {
self.variant(Ts::Itr0)
}
#[doc = "ITR1"]
#[inline(always)]
pub fn itr1(self) -> &'a mut crate::W<REG> {
self.variant(Ts::Itr1)
}
#[doc = "ITR2"]
#[inline(always)]
pub fn itr2(self) -> &'a mut crate::W<REG> {
self.variant(Ts::Itr2)
}
#[doc = "ITR3"]
#[inline(always)]
pub fn itr3(self) -> &'a mut crate::W<REG> {
self.variant(Ts::Itr3)
}
#[doc = "TI1F_ED"]
#[inline(always)]
pub fn ti1f_ed(self) -> &'a mut crate::W<REG> {
self.variant(Ts::Ti1fEd)
}
#[doc = "TI0FP0"]
#[inline(always)]
pub fn ti0fp0(self) -> &'a mut crate::W<REG> {
self.variant(Ts::Ti0fp0)
}
#[doc = "TI1FP1"]
#[inline(always)]
pub fn ti1fp1(self) -> &'a mut crate::W<REG> {
self.variant(Ts::Ti1fp1)
}
#[doc = "ETRF"]
#[inline(always)]
pub fn etrf(self) -> &'a mut crate::W<REG> {
self.variant(Ts::Etrf)
}
}
#[doc = "Field `MSM` reader - Master/slave mode"]
pub type MsmR = crate::BitReader;
#[doc = "Field `MSM` writer - Master/slave mode"]
pub type MsmW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "External trigger filter\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Etf {
#[doc = "0: FDIV1"]
Fdiv1 = 0,
#[doc = "1: FDIV1_N2"]
Fdiv1N2 = 1,
#[doc = "2: FDIV1_N4"]
Fdiv1N4 = 2,
#[doc = "3: FDIV1_N8"]
Fdiv1N8 = 3,
#[doc = "4: FDIV2_N6"]
Fdiv2N6 = 4,
#[doc = "5: FDIV2_N8"]
Fdiv2N8 = 5,
#[doc = "6: FDIV4_N6"]
Fdiv4N6 = 6,
#[doc = "7: FDIV4_N8"]
Fdiv4N8 = 7,
#[doc = "8: FDIV8_N6"]
Fdiv8N6 = 8,
#[doc = "9: FDIV8_N8"]
Fdiv8N8 = 9,
#[doc = "10: FDIV16_N5"]
Fdiv16N5 = 10,
#[doc = "11: FDIV16_N6"]
Fdiv16N6 = 11,
#[doc = "12: FDIV16_N8"]
Fdiv16N8 = 12,
#[doc = "13: FDIV32_N5"]
Fdiv32N5 = 13,
#[doc = "14: FDIV32_N6"]
Fdiv32N6 = 14,
#[doc = "15: FDIV32_N8"]
Fdiv32N8 = 15,
}
impl From<Etf> for u8 {
#[inline(always)]
fn from(variant: Etf) -> Self {
variant as _
}
}
impl crate::FieldSpec for Etf {
type Ux = u8;
}
impl crate::IsEnum for Etf {}
#[doc = "Field `ETF` reader - External trigger filter"]
pub type EtfR = crate::FieldReader<Etf>;
impl EtfR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Etf {
match self.bits {
0 => Etf::Fdiv1,
1 => Etf::Fdiv1N2,
2 => Etf::Fdiv1N4,
3 => Etf::Fdiv1N8,
4 => Etf::Fdiv2N6,
5 => Etf::Fdiv2N8,
6 => Etf::Fdiv4N6,
7 => Etf::Fdiv4N8,
8 => Etf::Fdiv8N6,
9 => Etf::Fdiv8N8,
10 => Etf::Fdiv16N5,
11 => Etf::Fdiv16N6,
12 => Etf::Fdiv16N8,
13 => Etf::Fdiv32N5,
14 => Etf::Fdiv32N6,
15 => Etf::Fdiv32N8,
_ => unreachable!(),
}
}
#[doc = "FDIV1"]
#[inline(always)]
pub fn is_fdiv1(&self) -> bool {
*self == Etf::Fdiv1
}
#[doc = "FDIV1_N2"]
#[inline(always)]
pub fn is_fdiv1_n2(&self) -> bool {
*self == Etf::Fdiv1N2
}
#[doc = "FDIV1_N4"]
#[inline(always)]
pub fn is_fdiv1_n4(&self) -> bool {
*self == Etf::Fdiv1N4
}
#[doc = "FDIV1_N8"]
#[inline(always)]
pub fn is_fdiv1_n8(&self) -> bool {
*self == Etf::Fdiv1N8
}
#[doc = "FDIV2_N6"]
#[inline(always)]
pub fn is_fdiv2_n6(&self) -> bool {
*self == Etf::Fdiv2N6
}
#[doc = "FDIV2_N8"]
#[inline(always)]
pub fn is_fdiv2_n8(&self) -> bool {
*self == Etf::Fdiv2N8
}
#[doc = "FDIV4_N6"]
#[inline(always)]
pub fn is_fdiv4_n6(&self) -> bool {
*self == Etf::Fdiv4N6
}
#[doc = "FDIV4_N8"]
#[inline(always)]
pub fn is_fdiv4_n8(&self) -> bool {
*self == Etf::Fdiv4N8
}
#[doc = "FDIV8_N6"]
#[inline(always)]
pub fn is_fdiv8_n6(&self) -> bool {
*self == Etf::Fdiv8N6
}
#[doc = "FDIV8_N8"]
#[inline(always)]
pub fn is_fdiv8_n8(&self) -> bool {
*self == Etf::Fdiv8N8
}
#[doc = "FDIV16_N5"]
#[inline(always)]
pub fn is_fdiv16_n5(&self) -> bool {
*self == Etf::Fdiv16N5
}
#[doc = "FDIV16_N6"]
#[inline(always)]
pub fn is_fdiv16_n6(&self) -> bool {
*self == Etf::Fdiv16N6
}
#[doc = "FDIV16_N8"]
#[inline(always)]
pub fn is_fdiv16_n8(&self) -> bool {
*self == Etf::Fdiv16N8
}
#[doc = "FDIV32_N5"]
#[inline(always)]
pub fn is_fdiv32_n5(&self) -> bool {
*self == Etf::Fdiv32N5
}
#[doc = "FDIV32_N6"]
#[inline(always)]
pub fn is_fdiv32_n6(&self) -> bool {
*self == Etf::Fdiv32N6
}
#[doc = "FDIV32_N8"]
#[inline(always)]
pub fn is_fdiv32_n8(&self) -> bool {
*self == Etf::Fdiv32N8
}
}
#[doc = "Field `ETF` writer - External trigger filter"]
pub type EtfW<'a, REG> = crate::FieldWriter<'a, REG, 4, Etf, crate::Safe>;
impl<'a, REG> EtfW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "FDIV1"]
#[inline(always)]
pub fn fdiv1(self) -> &'a mut crate::W<REG> {
self.variant(Etf::Fdiv1)
}
#[doc = "FDIV1_N2"]
#[inline(always)]
pub fn fdiv1_n2(self) -> &'a mut crate::W<REG> {
self.variant(Etf::Fdiv1N2)
}
#[doc = "FDIV1_N4"]
#[inline(always)]
pub fn fdiv1_n4(self) -> &'a mut crate::W<REG> {
self.variant(Etf::Fdiv1N4)
}
#[doc = "FDIV1_N8"]
#[inline(always)]
pub fn fdiv1_n8(self) -> &'a mut crate::W<REG> {
self.variant(Etf::Fdiv1N8)
}
#[doc = "FDIV2_N6"]
#[inline(always)]
pub fn fdiv2_n6(self) -> &'a mut crate::W<REG> {
self.variant(Etf::Fdiv2N6)
}
#[doc = "FDIV2_N8"]
#[inline(always)]
pub fn fdiv2_n8(self) -> &'a mut crate::W<REG> {
self.variant(Etf::Fdiv2N8)
}
#[doc = "FDIV4_N6"]
#[inline(always)]
pub fn fdiv4_n6(self) -> &'a mut crate::W<REG> {
self.variant(Etf::Fdiv4N6)
}
#[doc = "FDIV4_N8"]
#[inline(always)]
pub fn fdiv4_n8(self) -> &'a mut crate::W<REG> {
self.variant(Etf::Fdiv4N8)
}
#[doc = "FDIV8_N6"]
#[inline(always)]
pub fn fdiv8_n6(self) -> &'a mut crate::W<REG> {
self.variant(Etf::Fdiv8N6)
}
#[doc = "FDIV8_N8"]
#[inline(always)]
pub fn fdiv8_n8(self) -> &'a mut crate::W<REG> {
self.variant(Etf::Fdiv8N8)
}
#[doc = "FDIV16_N5"]
#[inline(always)]
pub fn fdiv16_n5(self) -> &'a mut crate::W<REG> {
self.variant(Etf::Fdiv16N5)
}
#[doc = "FDIV16_N6"]
#[inline(always)]
pub fn fdiv16_n6(self) -> &'a mut crate::W<REG> {
self.variant(Etf::Fdiv16N6)
}
#[doc = "FDIV16_N8"]
#[inline(always)]
pub fn fdiv16_n8(self) -> &'a mut crate::W<REG> {
self.variant(Etf::Fdiv16N8)
}
#[doc = "FDIV32_N5"]
#[inline(always)]
pub fn fdiv32_n5(self) -> &'a mut crate::W<REG> {
self.variant(Etf::Fdiv32N5)
}
#[doc = "FDIV32_N6"]
#[inline(always)]
pub fn fdiv32_n6(self) -> &'a mut crate::W<REG> {
self.variant(Etf::Fdiv32N6)
}
#[doc = "FDIV32_N8"]
#[inline(always)]
pub fn fdiv32_n8(self) -> &'a mut crate::W<REG> {
self.variant(Etf::Fdiv32N8)
}
}
#[doc = "External trigger prescaler\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Etps {
#[doc = "0: Div 1"]
Div1 = 0,
#[doc = "1: Div 2"]
Div2 = 1,
#[doc = "2: Div 4"]
Div4 = 2,
#[doc = "3: Div 8"]
Div8 = 3,
}
impl From<Etps> for u8 {
#[inline(always)]
fn from(variant: Etps) -> Self {
variant as _
}
}
impl crate::FieldSpec for Etps {
type Ux = u8;
}
impl crate::IsEnum for Etps {}
#[doc = "Field `ETPS` reader - External trigger prescaler"]
pub type EtpsR = crate::FieldReader<Etps>;
impl EtpsR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Etps {
match self.bits {
0 => Etps::Div1,
1 => Etps::Div2,
2 => Etps::Div4,
3 => Etps::Div8,
_ => unreachable!(),
}
}
#[doc = "Div 1"]
#[inline(always)]
pub fn is_div1(&self) -> bool {
*self == Etps::Div1
}
#[doc = "Div 2"]
#[inline(always)]
pub fn is_div2(&self) -> bool {
*self == Etps::Div2
}
#[doc = "Div 4"]
#[inline(always)]
pub fn is_div4(&self) -> bool {
*self == Etps::Div4
}
#[doc = "Div 8"]
#[inline(always)]
pub fn is_div8(&self) -> bool {
*self == Etps::Div8
}
}
#[doc = "Field `ETPS` writer - External trigger prescaler"]
pub type EtpsW<'a, REG> = crate::FieldWriter<'a, REG, 2, Etps, crate::Safe>;
impl<'a, REG> EtpsW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Div 1"]
#[inline(always)]
pub fn div1(self) -> &'a mut crate::W<REG> {
self.variant(Etps::Div1)
}
#[doc = "Div 2"]
#[inline(always)]
pub fn div2(self) -> &'a mut crate::W<REG> {
self.variant(Etps::Div2)
}
#[doc = "Div 4"]
#[inline(always)]
pub fn div4(self) -> &'a mut crate::W<REG> {
self.variant(Etps::Div4)
}
#[doc = "Div 8"]
#[inline(always)]
pub fn div8(self) -> &'a mut crate::W<REG> {
self.variant(Etps::Div8)
}
}
#[doc = "Field `ECE` reader - External clock enable"]
pub type EceR = crate::BitReader;
#[doc = "Field `ECE` writer - External clock enable"]
pub type EceW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "External trigger polarity\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Etp {
#[doc = "0: Non-inverted"]
Noninverted = 0,
#[doc = "1: Inverted"]
Inverted = 1,
}
impl From<Etp> for bool {
#[inline(always)]
fn from(variant: Etp) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `ETP` reader - External trigger polarity"]
pub type EtpR = crate::BitReader<Etp>;
impl EtpR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Etp {
match self.bits {
false => Etp::Noninverted,
true => Etp::Inverted,
}
}
#[doc = "Non-inverted"]
#[inline(always)]
pub fn is_noninverted(&self) -> bool {
*self == Etp::Noninverted
}
#[doc = "Inverted"]
#[inline(always)]
pub fn is_inverted(&self) -> bool {
*self == Etp::Inverted
}
}
#[doc = "Field `ETP` writer - External trigger polarity"]
pub type EtpW<'a, REG> = crate::BitWriter<'a, REG, Etp>;
impl<'a, REG> EtpW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Non-inverted"]
#[inline(always)]
pub fn noninverted(self) -> &'a mut crate::W<REG> {
self.variant(Etp::Noninverted)
}
#[doc = "Inverted"]
#[inline(always)]
pub fn inverted(self) -> &'a mut crate::W<REG> {
self.variant(Etp::Inverted)
}
}
impl R {
#[doc = "Bits 0:2 - Slave mode selection"]
#[inline(always)]
pub fn sms(&self) -> SmsR {
SmsR::new((self.bits & 7) as u8)
}
#[doc = "Bit 3 - OCREF clear selection"]
#[inline(always)]
pub fn occs(&self) -> OccsR {
OccsR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bits 4:6 - Trigger selection"]
#[inline(always)]
pub fn ts(&self) -> TsR {
TsR::new(((self.bits >> 4) & 7) as u8)
}
#[doc = "Bit 7 - Master/slave mode"]
#[inline(always)]
pub fn msm(&self) -> MsmR {
MsmR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:11 - External trigger filter"]
#[inline(always)]
pub fn etf(&self) -> EtfR {
EtfR::new(((self.bits >> 8) & 0x0f) as u8)
}
#[doc = "Bits 12:13 - External trigger prescaler"]
#[inline(always)]
pub fn etps(&self) -> EtpsR {
EtpsR::new(((self.bits >> 12) & 3) as u8)
}
#[doc = "Bit 14 - External clock enable"]
#[inline(always)]
pub fn ece(&self) -> EceR {
EceR::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15 - External trigger polarity"]
#[inline(always)]
pub fn etp(&self) -> EtpR {
EtpR::new(((self.bits >> 15) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:2 - Slave mode selection"]
#[inline(always)]
pub fn sms(&mut self) -> SmsW<SmcrSpec> {
SmsW::new(self, 0)
}
#[doc = "Bit 3 - OCREF clear selection"]
#[inline(always)]
pub fn occs(&mut self) -> OccsW<SmcrSpec> {
OccsW::new(self, 3)
}
#[doc = "Bits 4:6 - Trigger selection"]
#[inline(always)]
pub fn ts(&mut self) -> TsW<SmcrSpec> {
TsW::new(self, 4)
}
#[doc = "Bit 7 - Master/slave mode"]
#[inline(always)]
pub fn msm(&mut self) -> MsmW<SmcrSpec> {
MsmW::new(self, 7)
}
#[doc = "Bits 8:11 - External trigger filter"]
#[inline(always)]
pub fn etf(&mut self) -> EtfW<SmcrSpec> {
EtfW::new(self, 8)
}
#[doc = "Bits 12:13 - External trigger prescaler"]
#[inline(always)]
pub fn etps(&mut self) -> EtpsW<SmcrSpec> {
EtpsW::new(self, 12)
}
#[doc = "Bit 14 - External clock enable"]
#[inline(always)]
pub fn ece(&mut self) -> EceW<SmcrSpec> {
EceW::new(self, 14)
}
#[doc = "Bit 15 - External trigger polarity"]
#[inline(always)]
pub fn etp(&mut self) -> EtpW<SmcrSpec> {
EtpW::new(self, 15)
}
}
#[doc = "Slave mode control register\n\nYou can [`read`](crate::Reg::read) this register and get [`smcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`smcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SmcrSpec;
impl crate::RegisterSpec for SmcrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`smcr::R`](R) reader structure"]
impl crate::Readable for SmcrSpec {}
#[doc = "`write(|w| ..)` method takes [`smcr::W`](W) writer structure"]
impl crate::Writable for SmcrSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets SMCR to value 0"]
impl crate::Resettable for SmcrSpec {}
}
#[doc = "DIER (rw) register accessor: DMA/interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`dier::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dier::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dier`] module"]
#[doc(alias = "DIER")]
pub type Dier = crate::Reg<dier::DierSpec>;
#[doc = "DMA/interrupt enable register"]
pub mod dier {
#[doc = "Register `DIER` reader"]
pub type R = crate::R<DierSpec>;
#[doc = "Register `DIER` writer"]
pub type W = crate::W<DierSpec>;
#[doc = "Field `UIE` reader - Update interrupt enable"]
pub type UieR = crate::BitReader;
#[doc = "Field `UIE` writer - Update interrupt enable"]
pub type UieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CC0IE` reader - Capture/Compare 0 interrupt enable"]
pub type Cc0ieR = crate::BitReader;
#[doc = "Field `CC0IE` writer - Capture/Compare 0 interrupt enable"]
pub type Cc0ieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CC1IE` reader - Capture/Compare 1 interrupt enable"]
pub type Cc1ieR = crate::BitReader;
#[doc = "Field `CC1IE` writer - Capture/Compare 1 interrupt enable"]
pub type Cc1ieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CC2IE` reader - Capture/Compare 2 interrupt enable"]
pub type Cc2ieR = crate::BitReader;
#[doc = "Field `CC2IE` writer - Capture/Compare 2 interrupt enable"]
pub type Cc2ieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CC3IE` reader - Capture/Compare 3 interrupt enable"]
pub type Cc3ieR = crate::BitReader;
#[doc = "Field `CC3IE` writer - Capture/Compare 3 interrupt enable"]
pub type Cc3ieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `COMIE` reader - COM interrupt enable"]
pub type ComieR = crate::BitReader;
#[doc = "Field `COMIE` writer - COM interrupt enable"]
pub type ComieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TIE` reader - Trigger interrupt enable"]
pub type TieR = crate::BitReader;
#[doc = "Field `TIE` writer - Trigger interrupt enable"]
pub type TieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `BIE` reader - Break interrupt enable"]
pub type BieR = crate::BitReader;
#[doc = "Field `BIE` writer - Break interrupt enable"]
pub type BieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UDE` reader - Update DMA request enable"]
pub type UdeR = crate::BitReader;
#[doc = "Field `UDE` writer - Update DMA request enable"]
pub type UdeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CC0DE` reader - Capture/Compare 0 DMA request enable"]
pub type Cc0deR = crate::BitReader;
#[doc = "Field `CC0DE` writer - Capture/Compare 0 DMA request enable"]
pub type Cc0deW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CC1DE` reader - Capture/Compare 1 DMA request enable"]
pub type Cc1deR = crate::BitReader;
#[doc = "Field `CC1DE` writer - Capture/Compare 1 DMA request enable"]
pub type Cc1deW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CC2DE` reader - Capture/Compare 2 DMA request enable"]
pub type Cc2deR = crate::BitReader;
#[doc = "Field `CC2DE` writer - Capture/Compare 2 DMA request enable"]
pub type Cc2deW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CC3DE` reader - Capture/Compare 3 DMA request enable"]
pub type Cc3deR = crate::BitReader;
#[doc = "Field `CC3DE` writer - Capture/Compare 3 DMA request enable"]
pub type Cc3deW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `COMDE` reader - COM DMA request enable"]
pub type ComdeR = crate::BitReader;
#[doc = "Field `COMDE` writer - COM DMA request enable"]
pub type ComdeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TDE` reader - Trigger DMA request enable"]
pub type TdeR = crate::BitReader;
#[doc = "Field `TDE` writer - Trigger DMA request enable"]
pub type TdeW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - Update interrupt enable"]
#[inline(always)]
pub fn uie(&self) -> UieR {
UieR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Capture/Compare 0 interrupt enable"]
#[inline(always)]
pub fn cc0ie(&self) -> Cc0ieR {
Cc0ieR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Capture/Compare 1 interrupt enable"]
#[inline(always)]
pub fn cc1ie(&self) -> Cc1ieR {
Cc1ieR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Capture/Compare 2 interrupt enable"]
#[inline(always)]
pub fn cc2ie(&self) -> Cc2ieR {
Cc2ieR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Capture/Compare 3 interrupt enable"]
#[inline(always)]
pub fn cc3ie(&self) -> Cc3ieR {
Cc3ieR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - COM interrupt enable"]
#[inline(always)]
pub fn comie(&self) -> ComieR {
ComieR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Trigger interrupt enable"]
#[inline(always)]
pub fn tie(&self) -> TieR {
TieR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Break interrupt enable"]
#[inline(always)]
pub fn bie(&self) -> BieR {
BieR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - Update DMA request enable"]
#[inline(always)]
pub fn ude(&self) -> UdeR {
UdeR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - Capture/Compare 0 DMA request enable"]
#[inline(always)]
pub fn cc0de(&self) -> Cc0deR {
Cc0deR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - Capture/Compare 1 DMA request enable"]
#[inline(always)]
pub fn cc1de(&self) -> Cc1deR {
Cc1deR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - Capture/Compare 2 DMA request enable"]
#[inline(always)]
pub fn cc2de(&self) -> Cc2deR {
Cc2deR::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12 - Capture/Compare 3 DMA request enable"]
#[inline(always)]
pub fn cc3de(&self) -> Cc3deR {
Cc3deR::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13 - COM DMA request enable"]
#[inline(always)]
pub fn comde(&self) -> ComdeR {
ComdeR::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - Trigger DMA request enable"]
#[inline(always)]
pub fn tde(&self) -> TdeR {
TdeR::new(((self.bits >> 14) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Update interrupt enable"]
#[inline(always)]
pub fn uie(&mut self) -> UieW<DierSpec> {
UieW::new(self, 0)
}
#[doc = "Bit 1 - Capture/Compare 0 interrupt enable"]
#[inline(always)]
pub fn cc0ie(&mut self) -> Cc0ieW<DierSpec> {
Cc0ieW::new(self, 1)
}
#[doc = "Bit 2 - Capture/Compare 1 interrupt enable"]
#[inline(always)]
pub fn cc1ie(&mut self) -> Cc1ieW<DierSpec> {
Cc1ieW::new(self, 2)
}
#[doc = "Bit 3 - Capture/Compare 2 interrupt enable"]
#[inline(always)]
pub fn cc2ie(&mut self) -> Cc2ieW<DierSpec> {
Cc2ieW::new(self, 3)
}
#[doc = "Bit 4 - Capture/Compare 3 interrupt enable"]
#[inline(always)]
pub fn cc3ie(&mut self) -> Cc3ieW<DierSpec> {
Cc3ieW::new(self, 4)
}
#[doc = "Bit 5 - COM interrupt enable"]
#[inline(always)]
pub fn comie(&mut self) -> ComieW<DierSpec> {
ComieW::new(self, 5)
}
#[doc = "Bit 6 - Trigger interrupt enable"]
#[inline(always)]
pub fn tie(&mut self) -> TieW<DierSpec> {
TieW::new(self, 6)
}
#[doc = "Bit 7 - Break interrupt enable"]
#[inline(always)]
pub fn bie(&mut self) -> BieW<DierSpec> {
BieW::new(self, 7)
}
#[doc = "Bit 8 - Update DMA request enable"]
#[inline(always)]
pub fn ude(&mut self) -> UdeW<DierSpec> {
UdeW::new(self, 8)
}
#[doc = "Bit 9 - Capture/Compare 0 DMA request enable"]
#[inline(always)]
pub fn cc0de(&mut self) -> Cc0deW<DierSpec> {
Cc0deW::new(self, 9)
}
#[doc = "Bit 10 - Capture/Compare 1 DMA request enable"]
#[inline(always)]
pub fn cc1de(&mut self) -> Cc1deW<DierSpec> {
Cc1deW::new(self, 10)
}
#[doc = "Bit 11 - Capture/Compare 2 DMA request enable"]
#[inline(always)]
pub fn cc2de(&mut self) -> Cc2deW<DierSpec> {
Cc2deW::new(self, 11)
}
#[doc = "Bit 12 - Capture/Compare 3 DMA request enable"]
#[inline(always)]
pub fn cc3de(&mut self) -> Cc3deW<DierSpec> {
Cc3deW::new(self, 12)
}
#[doc = "Bit 13 - COM DMA request enable"]
#[inline(always)]
pub fn comde(&mut self) -> ComdeW<DierSpec> {
ComdeW::new(self, 13)
}
#[doc = "Bit 14 - Trigger DMA request enable"]
#[inline(always)]
pub fn tde(&mut self) -> TdeW<DierSpec> {
TdeW::new(self, 14)
}
}
#[doc = "DMA/interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`dier::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dier::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DierSpec;
impl crate::RegisterSpec for DierSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`dier::R`](R) reader structure"]
impl crate::Readable for DierSpec {}
#[doc = "`write(|w| ..)` method takes [`dier::W`](W) writer structure"]
impl crate::Writable for DierSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets DIER to value 0"]
impl crate::Resettable for DierSpec {}
}
#[doc = "SR (rw) register accessor: Status register\n\nYou can [`read`](crate::Reg::read) this register and get [`sr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sr`] module"]
#[doc(alias = "SR")]
pub type Sr = crate::Reg<sr::SrSpec>;
#[doc = "Status register"]
pub mod sr {
#[doc = "Register `SR` reader"]
pub type R = crate::R<SrSpec>;
#[doc = "Register `SR` writer"]
pub type W = crate::W<SrSpec>;
#[doc = "Field `UIF` reader - Update interrupt flag"]
pub type UifR = crate::BitReader;
#[doc = "Field `UIF` writer - Update interrupt flag"]
pub type UifW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CC0IF` reader - Capture/Compare 0 interrupt flag"]
pub type Cc0ifR = crate::BitReader;
#[doc = "Field `CC0IF` writer - Capture/Compare 0 interrupt flag"]
pub type Cc0ifW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CC1IF` reader - Capture/Compare 1 interrupt flag"]
pub type Cc1ifR = crate::BitReader;
#[doc = "Field `CC1IF` writer - Capture/Compare 1 interrupt flag"]
pub type Cc1ifW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CC2IF` reader - Capture/Compare 2 interrupt flag"]
pub type Cc2ifR = crate::BitReader;
#[doc = "Field `CC2IF` writer - Capture/Compare 2 interrupt flag"]
pub type Cc2ifW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CC3IF` reader - Capture/Compare 3 interrupt flag"]
pub type Cc3ifR = crate::BitReader;
#[doc = "Field `CC3IF` writer - Capture/Compare 3 interrupt flag"]
pub type Cc3ifW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `COMIF` reader - COM interrupt flag"]
pub type ComifR = crate::BitReader;
#[doc = "Field `COMIF` writer - COM interrupt flag"]
pub type ComifW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TIF` reader - Trigger interrupt flag"]
pub type TifR = crate::BitReader;
#[doc = "Field `TIF` writer - Trigger interrupt flag"]
pub type TifW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `BIF` reader - Break interrupt flag"]
pub type BifR = crate::BitReader;
#[doc = "Field `BIF` writer - Break interrupt flag"]
pub type BifW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CC0OF` reader - Capture/Compare 0 overcapture flag"]
pub type Cc0ofR = crate::BitReader;
#[doc = "Field `CC0OF` writer - Capture/Compare 0 overcapture flag"]
pub type Cc0ofW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CC1OF` reader - Capture/Compare 1 overcapture flag"]
pub type Cc1ofR = crate::BitReader;
#[doc = "Field `CC1OF` writer - Capture/Compare 1 overcapture flag"]
pub type Cc1ofW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CC2OF` reader - Capture/Compare 2 overcapture flag"]
pub type Cc2ofR = crate::BitReader;
#[doc = "Field `CC2OF` writer - Capture/Compare 2 overcapture flag"]
pub type Cc2ofW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CC3OF` reader - Capture/Compare 3 overcapture flag"]
pub type Cc3ofR = crate::BitReader;
#[doc = "Field `CC3OF` writer - Capture/Compare 3 overcapture flag"]
pub type Cc3ofW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - Update interrupt flag"]
#[inline(always)]
pub fn uif(&self) -> UifR {
UifR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Capture/Compare 0 interrupt flag"]
#[inline(always)]
pub fn cc0if(&self) -> Cc0ifR {
Cc0ifR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Capture/Compare 1 interrupt flag"]
#[inline(always)]
pub fn cc1if(&self) -> Cc1ifR {
Cc1ifR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Capture/Compare 2 interrupt flag"]
#[inline(always)]
pub fn cc2if(&self) -> Cc2ifR {
Cc2ifR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Capture/Compare 3 interrupt flag"]
#[inline(always)]
pub fn cc3if(&self) -> Cc3ifR {
Cc3ifR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - COM interrupt flag"]
#[inline(always)]
pub fn comif(&self) -> ComifR {
ComifR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Trigger interrupt flag"]
#[inline(always)]
pub fn tif(&self) -> TifR {
TifR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Break interrupt flag"]
#[inline(always)]
pub fn bif(&self) -> BifR {
BifR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 9 - Capture/Compare 0 overcapture flag"]
#[inline(always)]
pub fn cc0of(&self) -> Cc0ofR {
Cc0ofR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - Capture/Compare 1 overcapture flag"]
#[inline(always)]
pub fn cc1of(&self) -> Cc1ofR {
Cc1ofR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - Capture/Compare 2 overcapture flag"]
#[inline(always)]
pub fn cc2of(&self) -> Cc2ofR {
Cc2ofR::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12 - Capture/Compare 3 overcapture flag"]
#[inline(always)]
pub fn cc3of(&self) -> Cc3ofR {
Cc3ofR::new(((self.bits >> 12) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Update interrupt flag"]
#[inline(always)]
pub fn uif(&mut self) -> UifW<SrSpec> {
UifW::new(self, 0)
}
#[doc = "Bit 1 - Capture/Compare 0 interrupt flag"]
#[inline(always)]
pub fn cc0if(&mut self) -> Cc0ifW<SrSpec> {
Cc0ifW::new(self, 1)
}
#[doc = "Bit 2 - Capture/Compare 1 interrupt flag"]
#[inline(always)]
pub fn cc1if(&mut self) -> Cc1ifW<SrSpec> {
Cc1ifW::new(self, 2)
}
#[doc = "Bit 3 - Capture/Compare 2 interrupt flag"]
#[inline(always)]
pub fn cc2if(&mut self) -> Cc2ifW<SrSpec> {
Cc2ifW::new(self, 3)
}
#[doc = "Bit 4 - Capture/Compare 3 interrupt flag"]
#[inline(always)]
pub fn cc3if(&mut self) -> Cc3ifW<SrSpec> {
Cc3ifW::new(self, 4)
}
#[doc = "Bit 5 - COM interrupt flag"]
#[inline(always)]
pub fn comif(&mut self) -> ComifW<SrSpec> {
ComifW::new(self, 5)
}
#[doc = "Bit 6 - Trigger interrupt flag"]
#[inline(always)]
pub fn tif(&mut self) -> TifW<SrSpec> {
TifW::new(self, 6)
}
#[doc = "Bit 7 - Break interrupt flag"]
#[inline(always)]
pub fn bif(&mut self) -> BifW<SrSpec> {
BifW::new(self, 7)
}
#[doc = "Bit 9 - Capture/Compare 0 overcapture flag"]
#[inline(always)]
pub fn cc0of(&mut self) -> Cc0ofW<SrSpec> {
Cc0ofW::new(self, 9)
}
#[doc = "Bit 10 - Capture/Compare 1 overcapture flag"]
#[inline(always)]
pub fn cc1of(&mut self) -> Cc1ofW<SrSpec> {
Cc1ofW::new(self, 10)
}
#[doc = "Bit 11 - Capture/Compare 2 overcapture flag"]
#[inline(always)]
pub fn cc2of(&mut self) -> Cc2ofW<SrSpec> {
Cc2ofW::new(self, 11)
}
#[doc = "Bit 12 - Capture/Compare 3 overcapture flag"]
#[inline(always)]
pub fn cc3of(&mut self) -> Cc3ofW<SrSpec> {
Cc3ofW::new(self, 12)
}
}
#[doc = "Status register\n\nYou can [`read`](crate::Reg::read) this register and get [`sr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SrSpec;
impl crate::RegisterSpec for SrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`sr::R`](R) reader structure"]
impl crate::Readable for SrSpec {}
#[doc = "`write(|w| ..)` method takes [`sr::W`](W) writer structure"]
impl crate::Writable for SrSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets SR to value 0"]
impl crate::Resettable for SrSpec {}
}
#[doc = "EGR (w) register accessor: Event generation register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`egr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@egr`] module"]
#[doc(alias = "EGR")]
pub type Egr = crate::Reg<egr::EgrSpec>;
#[doc = "Event generation register"]
pub mod egr {
#[doc = "Register `EGR` writer"]
pub type W = crate::W<EgrSpec>;
#[doc = "Field `UG` writer - Update generation"]
pub type UgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CC0G` writer - Capture/Compare 0 generation"]
pub type Cc0gW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CC1G` writer - Capture/Compare 1 generation"]
pub type Cc1gW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CC2G` writer - Capture/Compare 2 generation"]
pub type Cc2gW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CC3G` writer - Capture/Compare 3 generation"]
pub type Cc3gW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `COMG` writer - Capture/Compare control update generation"]
pub type ComgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TG` writer - Trigger generation"]
pub type TgW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `BG` writer - Break generation"]
pub type BgW<'a, REG> = crate::BitWriter<'a, REG>;
impl W {
#[doc = "Bit 0 - Update generation"]
#[inline(always)]
pub fn ug(&mut self) -> UgW<EgrSpec> {
UgW::new(self, 0)
}
#[doc = "Bit 1 - Capture/Compare 0 generation"]
#[inline(always)]
pub fn cc0g(&mut self) -> Cc0gW<EgrSpec> {
Cc0gW::new(self, 1)
}
#[doc = "Bit 2 - Capture/Compare 1 generation"]
#[inline(always)]
pub fn cc1g(&mut self) -> Cc1gW<EgrSpec> {
Cc1gW::new(self, 2)
}
#[doc = "Bit 3 - Capture/Compare 2 generation"]
#[inline(always)]
pub fn cc2g(&mut self) -> Cc2gW<EgrSpec> {
Cc2gW::new(self, 3)
}
#[doc = "Bit 4 - Capture/Compare 3 generation"]
#[inline(always)]
pub fn cc3g(&mut self) -> Cc3gW<EgrSpec> {
Cc3gW::new(self, 4)
}
#[doc = "Bit 5 - Capture/Compare control update generation"]
#[inline(always)]
pub fn comg(&mut self) -> ComgW<EgrSpec> {
ComgW::new(self, 5)
}
#[doc = "Bit 6 - Trigger generation"]
#[inline(always)]
pub fn tg(&mut self) -> TgW<EgrSpec> {
TgW::new(self, 6)
}
#[doc = "Bit 7 - Break generation"]
#[inline(always)]
pub fn bg(&mut self) -> BgW<EgrSpec> {
BgW::new(self, 7)
}
}
#[doc = "Event generation register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`egr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EgrSpec;
impl crate::RegisterSpec for EgrSpec {
type Ux = u32;
}
#[doc = "`write(|w| ..)` method takes [`egr::W`](W) writer structure"]
impl crate::Writable for EgrSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets EGR to value 0"]
impl crate::Resettable for EgrSpec {}
}
#[doc = "CCMR0_input (rw) register accessor: Capture/compare mode register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ccmr0_input::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr0_input::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccmr0_input`] module"]
#[doc(alias = "CCMR0_input")]
pub type Ccmr0Input = crate::Reg<ccmr0_input::Ccmr0InputSpec>;
#[doc = "Capture/compare mode register 0"]
pub mod ccmr0_input {
#[doc = "Register `CCMR0_input` reader"]
pub type R = crate::R<Ccmr0InputSpec>;
#[doc = "Register `CCMR0_input` writer"]
pub type W = crate::W<Ccmr0InputSpec>;
#[doc = "Capture/Compare 0 selection\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Cc0s {
#[doc = "0: Output"]
Output = 0,
#[doc = "1: Input direct"]
Inputdirect = 1,
#[doc = "2: Input indirect"]
Inputindirect = 2,
#[doc = "3: Input TRC"]
InputTrc = 3,
}
impl From<Cc0s> for u8 {
#[inline(always)]
fn from(variant: Cc0s) -> Self {
variant as _
}
}
impl crate::FieldSpec for Cc0s {
type Ux = u8;
}
impl crate::IsEnum for Cc0s {}
#[doc = "Field `CC0S` reader - Capture/Compare 0 selection"]
pub type Cc0sR = crate::FieldReader<Cc0s>;
impl Cc0sR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Cc0s {
match self.bits {
0 => Cc0s::Output,
1 => Cc0s::Inputdirect,
2 => Cc0s::Inputindirect,
3 => Cc0s::InputTrc,
_ => unreachable!(),
}
}
#[doc = "Output"]
#[inline(always)]
pub fn is_output(&self) -> bool {
*self == Cc0s::Output
}
#[doc = "Input direct"]
#[inline(always)]
pub fn is_inputdirect(&self) -> bool {
*self == Cc0s::Inputdirect
}
#[doc = "Input indirect"]
#[inline(always)]
pub fn is_inputindirect(&self) -> bool {
*self == Cc0s::Inputindirect
}
#[doc = "Input TRC"]
#[inline(always)]
pub fn is_input_trc(&self) -> bool {
*self == Cc0s::InputTrc
}
}
#[doc = "Field `CC0S` writer - Capture/Compare 0 selection"]
pub type Cc0sW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cc0s, crate::Safe>;
impl<'a, REG> Cc0sW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Output"]
#[inline(always)]
pub fn output(self) -> &'a mut crate::W<REG> {
self.variant(Cc0s::Output)
}
#[doc = "Input direct"]
#[inline(always)]
pub fn inputdirect(self) -> &'a mut crate::W<REG> {
self.variant(Cc0s::Inputdirect)
}
#[doc = "Input indirect"]
#[inline(always)]
pub fn inputindirect(self) -> &'a mut crate::W<REG> {
self.variant(Cc0s::Inputindirect)
}
#[doc = "Input TRC"]
#[inline(always)]
pub fn input_trc(self) -> &'a mut crate::W<REG> {
self.variant(Cc0s::InputTrc)
}
}
#[doc = "Input capture 0 prescaler\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Ic0psc {
#[doc = "0: Div 1"]
Div1 = 0,
#[doc = "1: Div 2"]
Div2 = 1,
#[doc = "2: Div 4"]
Div4 = 2,
#[doc = "3: Div 8"]
Div8 = 3,
}
impl From<Ic0psc> for u8 {
#[inline(always)]
fn from(variant: Ic0psc) -> Self {
variant as _
}
}
impl crate::FieldSpec for Ic0psc {
type Ux = u8;
}
impl crate::IsEnum for Ic0psc {}
#[doc = "Field `IC0PSC` reader - Input capture 0 prescaler"]
pub type Ic0pscR = crate::FieldReader<Ic0psc>;
impl Ic0pscR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Ic0psc {
match self.bits {
0 => Ic0psc::Div1,
1 => Ic0psc::Div2,
2 => Ic0psc::Div4,
3 => Ic0psc::Div8,
_ => unreachable!(),
}
}
#[doc = "Div 1"]
#[inline(always)]
pub fn is_div1(&self) -> bool {
*self == Ic0psc::Div1
}
#[doc = "Div 2"]
#[inline(always)]
pub fn is_div2(&self) -> bool {
*self == Ic0psc::Div2
}
#[doc = "Div 4"]
#[inline(always)]
pub fn is_div4(&self) -> bool {
*self == Ic0psc::Div4
}
#[doc = "Div 8"]
#[inline(always)]
pub fn is_div8(&self) -> bool {
*self == Ic0psc::Div8
}
}
#[doc = "Field `IC0PSC` writer - Input capture 0 prescaler"]
pub type Ic0pscW<'a, REG> = crate::FieldWriter<'a, REG, 2, Ic0psc, crate::Safe>;
impl<'a, REG> Ic0pscW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Div 1"]
#[inline(always)]
pub fn div1(self) -> &'a mut crate::W<REG> {
self.variant(Ic0psc::Div1)
}
#[doc = "Div 2"]
#[inline(always)]
pub fn div2(self) -> &'a mut crate::W<REG> {
self.variant(Ic0psc::Div2)
}
#[doc = "Div 4"]
#[inline(always)]
pub fn div4(self) -> &'a mut crate::W<REG> {
self.variant(Ic0psc::Div4)
}
#[doc = "Div 8"]
#[inline(always)]
pub fn div8(self) -> &'a mut crate::W<REG> {
self.variant(Ic0psc::Div8)
}
}
#[doc = "Input capture 0 filter\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Ic0f {
#[doc = "0: FDIV1"]
Fdiv1 = 0,
#[doc = "1: FDIV1_N2"]
Fdiv1N2 = 1,
#[doc = "2: FDIV1_N4"]
Fdiv1N4 = 2,
#[doc = "3: FDIV1_N8"]
Fdiv1N8 = 3,
#[doc = "4: FDIV2_N6"]
Fdiv2N6 = 4,
#[doc = "5: FDIV2_N8"]
Fdiv2N8 = 5,
#[doc = "6: FDIV4_N6"]
Fdiv4N6 = 6,
#[doc = "7: FDIV4_N8"]
Fdiv4N8 = 7,
#[doc = "8: FDIV8_N6"]
Fdiv8N6 = 8,
#[doc = "9: FDIV8_N8"]
Fdiv8N8 = 9,
#[doc = "10: FDIV16_N5"]
Fdiv16N5 = 10,
#[doc = "11: FDIV16_N6"]
Fdiv16N6 = 11,
#[doc = "12: FDIV16_N8"]
Fdiv16N8 = 12,
#[doc = "13: FDIV32_N5"]
Fdiv32N5 = 13,
#[doc = "14: FDIV32_N6"]
Fdiv32N6 = 14,
#[doc = "15: FDIV32_N8"]
Fdiv32N8 = 15,
}
impl From<Ic0f> for u8 {
#[inline(always)]
fn from(variant: Ic0f) -> Self {
variant as _
}
}
impl crate::FieldSpec for Ic0f {
type Ux = u8;
}
impl crate::IsEnum for Ic0f {}
#[doc = "Field `IC0F` reader - Input capture 0 filter"]
pub type Ic0fR = crate::FieldReader<Ic0f>;
impl Ic0fR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Ic0f {
match self.bits {
0 => Ic0f::Fdiv1,
1 => Ic0f::Fdiv1N2,
2 => Ic0f::Fdiv1N4,
3 => Ic0f::Fdiv1N8,
4 => Ic0f::Fdiv2N6,
5 => Ic0f::Fdiv2N8,
6 => Ic0f::Fdiv4N6,
7 => Ic0f::Fdiv4N8,
8 => Ic0f::Fdiv8N6,
9 => Ic0f::Fdiv8N8,
10 => Ic0f::Fdiv16N5,
11 => Ic0f::Fdiv16N6,
12 => Ic0f::Fdiv16N8,
13 => Ic0f::Fdiv32N5,
14 => Ic0f::Fdiv32N6,
15 => Ic0f::Fdiv32N8,
_ => unreachable!(),
}
}
#[doc = "FDIV1"]
#[inline(always)]
pub fn is_fdiv1(&self) -> bool {
*self == Ic0f::Fdiv1
}
#[doc = "FDIV1_N2"]
#[inline(always)]
pub fn is_fdiv1_n2(&self) -> bool {
*self == Ic0f::Fdiv1N2
}
#[doc = "FDIV1_N4"]
#[inline(always)]
pub fn is_fdiv1_n4(&self) -> bool {
*self == Ic0f::Fdiv1N4
}
#[doc = "FDIV1_N8"]
#[inline(always)]
pub fn is_fdiv1_n8(&self) -> bool {
*self == Ic0f::Fdiv1N8
}
#[doc = "FDIV2_N6"]
#[inline(always)]
pub fn is_fdiv2_n6(&self) -> bool {
*self == Ic0f::Fdiv2N6
}
#[doc = "FDIV2_N8"]
#[inline(always)]
pub fn is_fdiv2_n8(&self) -> bool {
*self == Ic0f::Fdiv2N8
}
#[doc = "FDIV4_N6"]
#[inline(always)]
pub fn is_fdiv4_n6(&self) -> bool {
*self == Ic0f::Fdiv4N6
}
#[doc = "FDIV4_N8"]
#[inline(always)]
pub fn is_fdiv4_n8(&self) -> bool {
*self == Ic0f::Fdiv4N8
}
#[doc = "FDIV8_N6"]
#[inline(always)]
pub fn is_fdiv8_n6(&self) -> bool {
*self == Ic0f::Fdiv8N6
}
#[doc = "FDIV8_N8"]
#[inline(always)]
pub fn is_fdiv8_n8(&self) -> bool {
*self == Ic0f::Fdiv8N8
}
#[doc = "FDIV16_N5"]
#[inline(always)]
pub fn is_fdiv16_n5(&self) -> bool {
*self == Ic0f::Fdiv16N5
}
#[doc = "FDIV16_N6"]
#[inline(always)]
pub fn is_fdiv16_n6(&self) -> bool {
*self == Ic0f::Fdiv16N6
}
#[doc = "FDIV16_N8"]
#[inline(always)]
pub fn is_fdiv16_n8(&self) -> bool {
*self == Ic0f::Fdiv16N8
}
#[doc = "FDIV32_N5"]
#[inline(always)]
pub fn is_fdiv32_n5(&self) -> bool {
*self == Ic0f::Fdiv32N5
}
#[doc = "FDIV32_N6"]
#[inline(always)]
pub fn is_fdiv32_n6(&self) -> bool {
*self == Ic0f::Fdiv32N6
}
#[doc = "FDIV32_N8"]
#[inline(always)]
pub fn is_fdiv32_n8(&self) -> bool {
*self == Ic0f::Fdiv32N8
}
}
#[doc = "Field `IC0F` writer - Input capture 0 filter"]
pub type Ic0fW<'a, REG> = crate::FieldWriter<'a, REG, 4, Ic0f, crate::Safe>;
impl<'a, REG> Ic0fW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "FDIV1"]
#[inline(always)]
pub fn fdiv1(self) -> &'a mut crate::W<REG> {
self.variant(Ic0f::Fdiv1)
}
#[doc = "FDIV1_N2"]
#[inline(always)]
pub fn fdiv1_n2(self) -> &'a mut crate::W<REG> {
self.variant(Ic0f::Fdiv1N2)
}
#[doc = "FDIV1_N4"]
#[inline(always)]
pub fn fdiv1_n4(self) -> &'a mut crate::W<REG> {
self.variant(Ic0f::Fdiv1N4)
}
#[doc = "FDIV1_N8"]
#[inline(always)]
pub fn fdiv1_n8(self) -> &'a mut crate::W<REG> {
self.variant(Ic0f::Fdiv1N8)
}
#[doc = "FDIV2_N6"]
#[inline(always)]
pub fn fdiv2_n6(self) -> &'a mut crate::W<REG> {
self.variant(Ic0f::Fdiv2N6)
}
#[doc = "FDIV2_N8"]
#[inline(always)]
pub fn fdiv2_n8(self) -> &'a mut crate::W<REG> {
self.variant(Ic0f::Fdiv2N8)
}
#[doc = "FDIV4_N6"]
#[inline(always)]
pub fn fdiv4_n6(self) -> &'a mut crate::W<REG> {
self.variant(Ic0f::Fdiv4N6)
}
#[doc = "FDIV4_N8"]
#[inline(always)]
pub fn fdiv4_n8(self) -> &'a mut crate::W<REG> {
self.variant(Ic0f::Fdiv4N8)
}
#[doc = "FDIV8_N6"]
#[inline(always)]
pub fn fdiv8_n6(self) -> &'a mut crate::W<REG> {
self.variant(Ic0f::Fdiv8N6)
}
#[doc = "FDIV8_N8"]
#[inline(always)]
pub fn fdiv8_n8(self) -> &'a mut crate::W<REG> {
self.variant(Ic0f::Fdiv8N8)
}
#[doc = "FDIV16_N5"]
#[inline(always)]
pub fn fdiv16_n5(self) -> &'a mut crate::W<REG> {
self.variant(Ic0f::Fdiv16N5)
}
#[doc = "FDIV16_N6"]
#[inline(always)]
pub fn fdiv16_n6(self) -> &'a mut crate::W<REG> {
self.variant(Ic0f::Fdiv16N6)
}
#[doc = "FDIV16_N8"]
#[inline(always)]
pub fn fdiv16_n8(self) -> &'a mut crate::W<REG> {
self.variant(Ic0f::Fdiv16N8)
}
#[doc = "FDIV32_N5"]
#[inline(always)]
pub fn fdiv32_n5(self) -> &'a mut crate::W<REG> {
self.variant(Ic0f::Fdiv32N5)
}
#[doc = "FDIV32_N6"]
#[inline(always)]
pub fn fdiv32_n6(self) -> &'a mut crate::W<REG> {
self.variant(Ic0f::Fdiv32N6)
}
#[doc = "FDIV32_N8"]
#[inline(always)]
pub fn fdiv32_n8(self) -> &'a mut crate::W<REG> {
self.variant(Ic0f::Fdiv32N8)
}
}
#[doc = "Capture/Compare 1 selection\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Cc1s {
#[doc = "0: Output"]
Output = 0,
#[doc = "1: Input direct"]
Inputdirect = 1,
#[doc = "2: Input indirect"]
Inputindirect = 2,
#[doc = "3: Input TRC"]
InputTrc = 3,
}
impl From<Cc1s> for u8 {
#[inline(always)]
fn from(variant: Cc1s) -> Self {
variant as _
}
}
impl crate::FieldSpec for Cc1s {
type Ux = u8;
}
impl crate::IsEnum for Cc1s {}
#[doc = "Field `CC1S` reader - Capture/Compare 1 selection"]
pub type Cc1sR = crate::FieldReader<Cc1s>;
impl Cc1sR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Cc1s {
match self.bits {
0 => Cc1s::Output,
1 => Cc1s::Inputdirect,
2 => Cc1s::Inputindirect,
3 => Cc1s::InputTrc,
_ => unreachable!(),
}
}
#[doc = "Output"]
#[inline(always)]
pub fn is_output(&self) -> bool {
*self == Cc1s::Output
}
#[doc = "Input direct"]
#[inline(always)]
pub fn is_inputdirect(&self) -> bool {
*self == Cc1s::Inputdirect
}
#[doc = "Input indirect"]
#[inline(always)]
pub fn is_inputindirect(&self) -> bool {
*self == Cc1s::Inputindirect
}
#[doc = "Input TRC"]
#[inline(always)]
pub fn is_input_trc(&self) -> bool {
*self == Cc1s::InputTrc
}
}
#[doc = "Field `CC1S` writer - Capture/Compare 1 selection"]
pub type Cc1sW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cc1s, crate::Safe>;
impl<'a, REG> Cc1sW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Output"]
#[inline(always)]
pub fn output(self) -> &'a mut crate::W<REG> {
self.variant(Cc1s::Output)
}
#[doc = "Input direct"]
#[inline(always)]
pub fn inputdirect(self) -> &'a mut crate::W<REG> {
self.variant(Cc1s::Inputdirect)
}
#[doc = "Input indirect"]
#[inline(always)]
pub fn inputindirect(self) -> &'a mut crate::W<REG> {
self.variant(Cc1s::Inputindirect)
}
#[doc = "Input TRC"]
#[inline(always)]
pub fn input_trc(self) -> &'a mut crate::W<REG> {
self.variant(Cc1s::InputTrc)
}
}
#[doc = "Input capture 1 prescaler\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Ic1psc {
#[doc = "0: Div 1"]
Div1 = 0,
#[doc = "1: Div 2"]
Div2 = 1,
#[doc = "2: Div 4"]
Div4 = 2,
#[doc = "3: Div 8"]
Div8 = 3,
}
impl From<Ic1psc> for u8 {
#[inline(always)]
fn from(variant: Ic1psc) -> Self {
variant as _
}
}
impl crate::FieldSpec for Ic1psc {
type Ux = u8;
}
impl crate::IsEnum for Ic1psc {}
#[doc = "Field `IC1PSC` reader - Input capture 1 prescaler"]
pub type Ic1pscR = crate::FieldReader<Ic1psc>;
impl Ic1pscR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Ic1psc {
match self.bits {
0 => Ic1psc::Div1,
1 => Ic1psc::Div2,
2 => Ic1psc::Div4,
3 => Ic1psc::Div8,
_ => unreachable!(),
}
}
#[doc = "Div 1"]
#[inline(always)]
pub fn is_div1(&self) -> bool {
*self == Ic1psc::Div1
}
#[doc = "Div 2"]
#[inline(always)]
pub fn is_div2(&self) -> bool {
*self == Ic1psc::Div2
}
#[doc = "Div 4"]
#[inline(always)]
pub fn is_div4(&self) -> bool {
*self == Ic1psc::Div4
}
#[doc = "Div 8"]
#[inline(always)]
pub fn is_div8(&self) -> bool {
*self == Ic1psc::Div8
}
}
#[doc = "Field `IC1PSC` writer - Input capture 1 prescaler"]
pub type Ic1pscW<'a, REG> = crate::FieldWriter<'a, REG, 2, Ic1psc, crate::Safe>;
impl<'a, REG> Ic1pscW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Div 1"]
#[inline(always)]
pub fn div1(self) -> &'a mut crate::W<REG> {
self.variant(Ic1psc::Div1)
}
#[doc = "Div 2"]
#[inline(always)]
pub fn div2(self) -> &'a mut crate::W<REG> {
self.variant(Ic1psc::Div2)
}
#[doc = "Div 4"]
#[inline(always)]
pub fn div4(self) -> &'a mut crate::W<REG> {
self.variant(Ic1psc::Div4)
}
#[doc = "Div 8"]
#[inline(always)]
pub fn div8(self) -> &'a mut crate::W<REG> {
self.variant(Ic1psc::Div8)
}
}
#[doc = "Input capture 1 filter\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Ic1f {
#[doc = "0: FDIV1"]
Fdiv1 = 0,
#[doc = "1: FDIV1_N2"]
Fdiv1N2 = 1,
#[doc = "2: FDIV1_N4"]
Fdiv1N4 = 2,
#[doc = "3: FDIV1_N8"]
Fdiv1N8 = 3,
#[doc = "4: FDIV2_N6"]
Fdiv2N6 = 4,
#[doc = "5: FDIV2_N8"]
Fdiv2N8 = 5,
#[doc = "6: FDIV4_N6"]
Fdiv4N6 = 6,
#[doc = "7: FDIV4_N8"]
Fdiv4N8 = 7,
#[doc = "8: FDIV8_N6"]
Fdiv8N6 = 8,
#[doc = "9: FDIV8_N8"]
Fdiv8N8 = 9,
#[doc = "10: FDIV16_N5"]
Fdiv16N5 = 10,
#[doc = "11: FDIV16_N6"]
Fdiv16N6 = 11,
#[doc = "12: FDIV16_N8"]
Fdiv16N8 = 12,
#[doc = "13: FDIV32_N5"]
Fdiv32N5 = 13,
#[doc = "14: FDIV32_N6"]
Fdiv32N6 = 14,
#[doc = "15: FDIV32_N8"]
Fdiv32N8 = 15,
}
impl From<Ic1f> for u8 {
#[inline(always)]
fn from(variant: Ic1f) -> Self {
variant as _
}
}
impl crate::FieldSpec for Ic1f {
type Ux = u8;
}
impl crate::IsEnum for Ic1f {}
#[doc = "Field `IC1F` reader - Input capture 1 filter"]
pub type Ic1fR = crate::FieldReader<Ic1f>;
impl Ic1fR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Ic1f {
match self.bits {
0 => Ic1f::Fdiv1,
1 => Ic1f::Fdiv1N2,
2 => Ic1f::Fdiv1N4,
3 => Ic1f::Fdiv1N8,
4 => Ic1f::Fdiv2N6,
5 => Ic1f::Fdiv2N8,
6 => Ic1f::Fdiv4N6,
7 => Ic1f::Fdiv4N8,
8 => Ic1f::Fdiv8N6,
9 => Ic1f::Fdiv8N8,
10 => Ic1f::Fdiv16N5,
11 => Ic1f::Fdiv16N6,
12 => Ic1f::Fdiv16N8,
13 => Ic1f::Fdiv32N5,
14 => Ic1f::Fdiv32N6,
15 => Ic1f::Fdiv32N8,
_ => unreachable!(),
}
}
#[doc = "FDIV1"]
#[inline(always)]
pub fn is_fdiv1(&self) -> bool {
*self == Ic1f::Fdiv1
}
#[doc = "FDIV1_N2"]
#[inline(always)]
pub fn is_fdiv1_n2(&self) -> bool {
*self == Ic1f::Fdiv1N2
}
#[doc = "FDIV1_N4"]
#[inline(always)]
pub fn is_fdiv1_n4(&self) -> bool {
*self == Ic1f::Fdiv1N4
}
#[doc = "FDIV1_N8"]
#[inline(always)]
pub fn is_fdiv1_n8(&self) -> bool {
*self == Ic1f::Fdiv1N8
}
#[doc = "FDIV2_N6"]
#[inline(always)]
pub fn is_fdiv2_n6(&self) -> bool {
*self == Ic1f::Fdiv2N6
}
#[doc = "FDIV2_N8"]
#[inline(always)]
pub fn is_fdiv2_n8(&self) -> bool {
*self == Ic1f::Fdiv2N8
}
#[doc = "FDIV4_N6"]
#[inline(always)]
pub fn is_fdiv4_n6(&self) -> bool {
*self == Ic1f::Fdiv4N6
}
#[doc = "FDIV4_N8"]
#[inline(always)]
pub fn is_fdiv4_n8(&self) -> bool {
*self == Ic1f::Fdiv4N8
}
#[doc = "FDIV8_N6"]
#[inline(always)]
pub fn is_fdiv8_n6(&self) -> bool {
*self == Ic1f::Fdiv8N6
}
#[doc = "FDIV8_N8"]
#[inline(always)]
pub fn is_fdiv8_n8(&self) -> bool {
*self == Ic1f::Fdiv8N8
}
#[doc = "FDIV16_N5"]
#[inline(always)]
pub fn is_fdiv16_n5(&self) -> bool {
*self == Ic1f::Fdiv16N5
}
#[doc = "FDIV16_N6"]
#[inline(always)]
pub fn is_fdiv16_n6(&self) -> bool {
*self == Ic1f::Fdiv16N6
}
#[doc = "FDIV16_N8"]
#[inline(always)]
pub fn is_fdiv16_n8(&self) -> bool {
*self == Ic1f::Fdiv16N8
}
#[doc = "FDIV32_N5"]
#[inline(always)]
pub fn is_fdiv32_n5(&self) -> bool {
*self == Ic1f::Fdiv32N5
}
#[doc = "FDIV32_N6"]
#[inline(always)]
pub fn is_fdiv32_n6(&self) -> bool {
*self == Ic1f::Fdiv32N6
}
#[doc = "FDIV32_N8"]
#[inline(always)]
pub fn is_fdiv32_n8(&self) -> bool {
*self == Ic1f::Fdiv32N8
}
}
#[doc = "Field `IC1F` writer - Input capture 1 filter"]
pub type Ic1fW<'a, REG> = crate::FieldWriter<'a, REG, 4, Ic1f, crate::Safe>;
impl<'a, REG> Ic1fW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "FDIV1"]
#[inline(always)]
pub fn fdiv1(self) -> &'a mut crate::W<REG> {
self.variant(Ic1f::Fdiv1)
}
#[doc = "FDIV1_N2"]
#[inline(always)]
pub fn fdiv1_n2(self) -> &'a mut crate::W<REG> {
self.variant(Ic1f::Fdiv1N2)
}
#[doc = "FDIV1_N4"]
#[inline(always)]
pub fn fdiv1_n4(self) -> &'a mut crate::W<REG> {
self.variant(Ic1f::Fdiv1N4)
}
#[doc = "FDIV1_N8"]
#[inline(always)]
pub fn fdiv1_n8(self) -> &'a mut crate::W<REG> {
self.variant(Ic1f::Fdiv1N8)
}
#[doc = "FDIV2_N6"]
#[inline(always)]
pub fn fdiv2_n6(self) -> &'a mut crate::W<REG> {
self.variant(Ic1f::Fdiv2N6)
}
#[doc = "FDIV2_N8"]
#[inline(always)]
pub fn fdiv2_n8(self) -> &'a mut crate::W<REG> {
self.variant(Ic1f::Fdiv2N8)
}
#[doc = "FDIV4_N6"]
#[inline(always)]
pub fn fdiv4_n6(self) -> &'a mut crate::W<REG> {
self.variant(Ic1f::Fdiv4N6)
}
#[doc = "FDIV4_N8"]
#[inline(always)]
pub fn fdiv4_n8(self) -> &'a mut crate::W<REG> {
self.variant(Ic1f::Fdiv4N8)
}
#[doc = "FDIV8_N6"]
#[inline(always)]
pub fn fdiv8_n6(self) -> &'a mut crate::W<REG> {
self.variant(Ic1f::Fdiv8N6)
}
#[doc = "FDIV8_N8"]
#[inline(always)]
pub fn fdiv8_n8(self) -> &'a mut crate::W<REG> {
self.variant(Ic1f::Fdiv8N8)
}
#[doc = "FDIV16_N5"]
#[inline(always)]
pub fn fdiv16_n5(self) -> &'a mut crate::W<REG> {
self.variant(Ic1f::Fdiv16N5)
}
#[doc = "FDIV16_N6"]
#[inline(always)]
pub fn fdiv16_n6(self) -> &'a mut crate::W<REG> {
self.variant(Ic1f::Fdiv16N6)
}
#[doc = "FDIV16_N8"]
#[inline(always)]
pub fn fdiv16_n8(self) -> &'a mut crate::W<REG> {
self.variant(Ic1f::Fdiv16N8)
}
#[doc = "FDIV32_N5"]
#[inline(always)]
pub fn fdiv32_n5(self) -> &'a mut crate::W<REG> {
self.variant(Ic1f::Fdiv32N5)
}
#[doc = "FDIV32_N6"]
#[inline(always)]
pub fn fdiv32_n6(self) -> &'a mut crate::W<REG> {
self.variant(Ic1f::Fdiv32N6)
}
#[doc = "FDIV32_N8"]
#[inline(always)]
pub fn fdiv32_n8(self) -> &'a mut crate::W<REG> {
self.variant(Ic1f::Fdiv32N8)
}
}
impl R {
#[doc = "Bits 0:1 - Capture/Compare 0 selection"]
#[inline(always)]
pub fn cc0s(&self) -> Cc0sR {
Cc0sR::new((self.bits & 3) as u8)
}
#[doc = "Bits 2:3 - Input capture 0 prescaler"]
#[inline(always)]
pub fn ic0psc(&self) -> Ic0pscR {
Ic0pscR::new(((self.bits >> 2) & 3) as u8)
}
#[doc = "Bits 4:7 - Input capture 0 filter"]
#[inline(always)]
pub fn ic0f(&self) -> Ic0fR {
Ic0fR::new(((self.bits >> 4) & 0x0f) as u8)
}
#[doc = "Bits 8:9 - Capture/Compare 1 selection"]
#[inline(always)]
pub fn cc1s(&self) -> Cc1sR {
Cc1sR::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bits 10:11 - Input capture 1 prescaler"]
#[inline(always)]
pub fn ic1psc(&self) -> Ic1pscR {
Ic1pscR::new(((self.bits >> 10) & 3) as u8)
}
#[doc = "Bits 12:15 - Input capture 1 filter"]
#[inline(always)]
pub fn ic1f(&self) -> Ic1fR {
Ic1fR::new(((self.bits >> 12) & 0x0f) as u8)
}
}
impl W {
#[doc = "Bits 0:1 - Capture/Compare 0 selection"]
#[inline(always)]
pub fn cc0s(&mut self) -> Cc0sW<Ccmr0InputSpec> {
Cc0sW::new(self, 0)
}
#[doc = "Bits 2:3 - Input capture 0 prescaler"]
#[inline(always)]
pub fn ic0psc(&mut self) -> Ic0pscW<Ccmr0InputSpec> {
Ic0pscW::new(self, 2)
}
#[doc = "Bits 4:7 - Input capture 0 filter"]
#[inline(always)]
pub fn ic0f(&mut self) -> Ic0fW<Ccmr0InputSpec> {
Ic0fW::new(self, 4)
}
#[doc = "Bits 8:9 - Capture/Compare 1 selection"]
#[inline(always)]
pub fn cc1s(&mut self) -> Cc1sW<Ccmr0InputSpec> {
Cc1sW::new(self, 8)
}
#[doc = "Bits 10:11 - Input capture 1 prescaler"]
#[inline(always)]
pub fn ic1psc(&mut self) -> Ic1pscW<Ccmr0InputSpec> {
Ic1pscW::new(self, 10)
}
#[doc = "Bits 12:15 - Input capture 1 filter"]
#[inline(always)]
pub fn ic1f(&mut self) -> Ic1fW<Ccmr0InputSpec> {
Ic1fW::new(self, 12)
}
}
#[doc = "Capture/compare mode register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ccmr0_input::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr0_input::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ccmr0InputSpec;
impl crate::RegisterSpec for Ccmr0InputSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ccmr0_input::R`](R) reader structure"]
impl crate::Readable for Ccmr0InputSpec {}
#[doc = "`write(|w| ..)` method takes [`ccmr0_input::W`](W) writer structure"]
impl crate::Writable for Ccmr0InputSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets CCMR0_input to value 0"]
impl crate::Resettable for Ccmr0InputSpec {}
}
#[doc = "CCMR0_output (rw) register accessor: Capture/compare mode register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ccmr0_output::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr0_output::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccmr0_output`] module"]
#[doc(alias = "CCMR0_output")]
pub type Ccmr0Output = crate::Reg<ccmr0_output::Ccmr0OutputSpec>;
#[doc = "Capture/compare mode register 0"]
pub mod ccmr0_output {
#[doc = "Register `CCMR0_output` reader"]
pub type R = crate::R<Ccmr0OutputSpec>;
#[doc = "Register `CCMR0_output` writer"]
pub type W = crate::W<Ccmr0OutputSpec>;
#[doc = "Capture/Compare 0 selection\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Cc0s {
#[doc = "0: Output"]
Output = 0,
#[doc = "1: Input direct"]
Inputdirect = 1,
#[doc = "2: Input indirect"]
Inputindirect = 2,
#[doc = "3: Input TRC"]
InputTrc = 3,
}
impl From<Cc0s> for u8 {
#[inline(always)]
fn from(variant: Cc0s) -> Self {
variant as _
}
}
impl crate::FieldSpec for Cc0s {
type Ux = u8;
}
impl crate::IsEnum for Cc0s {}
#[doc = "Field `CC0S` reader - Capture/Compare 0 selection"]
pub type Cc0sR = crate::FieldReader<Cc0s>;
impl Cc0sR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Cc0s {
match self.bits {
0 => Cc0s::Output,
1 => Cc0s::Inputdirect,
2 => Cc0s::Inputindirect,
3 => Cc0s::InputTrc,
_ => unreachable!(),
}
}
#[doc = "Output"]
#[inline(always)]
pub fn is_output(&self) -> bool {
*self == Cc0s::Output
}
#[doc = "Input direct"]
#[inline(always)]
pub fn is_inputdirect(&self) -> bool {
*self == Cc0s::Inputdirect
}
#[doc = "Input indirect"]
#[inline(always)]
pub fn is_inputindirect(&self) -> bool {
*self == Cc0s::Inputindirect
}
#[doc = "Input TRC"]
#[inline(always)]
pub fn is_input_trc(&self) -> bool {
*self == Cc0s::InputTrc
}
}
#[doc = "Field `CC0S` writer - Capture/Compare 0 selection"]
pub type Cc0sW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cc0s, crate::Safe>;
impl<'a, REG> Cc0sW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Output"]
#[inline(always)]
pub fn output(self) -> &'a mut crate::W<REG> {
self.variant(Cc0s::Output)
}
#[doc = "Input direct"]
#[inline(always)]
pub fn inputdirect(self) -> &'a mut crate::W<REG> {
self.variant(Cc0s::Inputdirect)
}
#[doc = "Input indirect"]
#[inline(always)]
pub fn inputindirect(self) -> &'a mut crate::W<REG> {
self.variant(Cc0s::Inputindirect)
}
#[doc = "Input TRC"]
#[inline(always)]
pub fn input_trc(self) -> &'a mut crate::W<REG> {
self.variant(Cc0s::InputTrc)
}
}
#[doc = "Field `OC0FE` reader - Output compare 0 fast enable"]
pub type Oc0feR = crate::BitReader;
#[doc = "Field `OC0FE` writer - Output compare 0 fast enable"]
pub type Oc0feW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OC0PE` reader - Output compare 0 preload enable"]
pub type Oc0peR = crate::BitReader;
#[doc = "Field `OC0PE` writer - Output compare 0 preload enable"]
pub type Oc0peW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Output compare 0 mode\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Oc0m {
#[doc = "0: Frozen"]
Frozen = 0,
#[doc = "1: Active"]
Active = 1,
#[doc = "2: Inactive"]
Inactive = 2,
#[doc = "3: Toggle"]
Toggle = 3,
#[doc = "4: Forced inactive"]
Forcedinactive = 4,
#[doc = "5: Forced active"]
Forcedactive = 5,
#[doc = "6: Pwm1"]
Pwm1 = 6,
#[doc = "7: Pwm2"]
Pwm2 = 7,
}
impl From<Oc0m> for u8 {
#[inline(always)]
fn from(variant: Oc0m) -> Self {
variant as _
}
}
impl crate::FieldSpec for Oc0m {
type Ux = u8;
}
impl crate::IsEnum for Oc0m {}
#[doc = "Field `OC0M` reader - Output compare 0 mode"]
pub type Oc0mR = crate::FieldReader<Oc0m>;
impl Oc0mR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Oc0m {
match self.bits {
0 => Oc0m::Frozen,
1 => Oc0m::Active,
2 => Oc0m::Inactive,
3 => Oc0m::Toggle,
4 => Oc0m::Forcedinactive,
5 => Oc0m::Forcedactive,
6 => Oc0m::Pwm1,
7 => Oc0m::Pwm2,
_ => unreachable!(),
}
}
#[doc = "Frozen"]
#[inline(always)]
pub fn is_frozen(&self) -> bool {
*self == Oc0m::Frozen
}
#[doc = "Active"]
#[inline(always)]
pub fn is_active(&self) -> bool {
*self == Oc0m::Active
}
#[doc = "Inactive"]
#[inline(always)]
pub fn is_inactive(&self) -> bool {
*self == Oc0m::Inactive
}
#[doc = "Toggle"]
#[inline(always)]
pub fn is_toggle(&self) -> bool {
*self == Oc0m::Toggle
}
#[doc = "Forced inactive"]
#[inline(always)]
pub fn is_forcedinactive(&self) -> bool {
*self == Oc0m::Forcedinactive
}
#[doc = "Forced active"]
#[inline(always)]
pub fn is_forcedactive(&self) -> bool {
*self == Oc0m::Forcedactive
}
#[doc = "Pwm1"]
#[inline(always)]
pub fn is_pwm1(&self) -> bool {
*self == Oc0m::Pwm1
}
#[doc = "Pwm2"]
#[inline(always)]
pub fn is_pwm2(&self) -> bool {
*self == Oc0m::Pwm2
}
}
#[doc = "Field `OC0M` writer - Output compare 0 mode"]
pub type Oc0mW<'a, REG> = crate::FieldWriter<'a, REG, 3, Oc0m, crate::Safe>;
impl<'a, REG> Oc0mW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Frozen"]
#[inline(always)]
pub fn frozen(self) -> &'a mut crate::W<REG> {
self.variant(Oc0m::Frozen)
}
#[doc = "Active"]
#[inline(always)]
pub fn active(self) -> &'a mut crate::W<REG> {
self.variant(Oc0m::Active)
}
#[doc = "Inactive"]
#[inline(always)]
pub fn inactive(self) -> &'a mut crate::W<REG> {
self.variant(Oc0m::Inactive)
}
#[doc = "Toggle"]
#[inline(always)]
pub fn toggle(self) -> &'a mut crate::W<REG> {
self.variant(Oc0m::Toggle)
}
#[doc = "Forced inactive"]
#[inline(always)]
pub fn forcedinactive(self) -> &'a mut crate::W<REG> {
self.variant(Oc0m::Forcedinactive)
}
#[doc = "Forced active"]
#[inline(always)]
pub fn forcedactive(self) -> &'a mut crate::W<REG> {
self.variant(Oc0m::Forcedactive)
}
#[doc = "Pwm1"]
#[inline(always)]
pub fn pwm1(self) -> &'a mut crate::W<REG> {
self.variant(Oc0m::Pwm1)
}
#[doc = "Pwm2"]
#[inline(always)]
pub fn pwm2(self) -> &'a mut crate::W<REG> {
self.variant(Oc0m::Pwm2)
}
}
#[doc = "Field `OC0CE` reader - Output compare 0 clear enable"]
pub type Oc0ceR = crate::BitReader;
#[doc = "Field `OC0CE` writer - Output compare 0 clear enable"]
pub type Oc0ceW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Capture/Compare 1 selection\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Cc1s {
#[doc = "0: Output"]
Output = 0,
#[doc = "1: Input direct"]
Inputdirect = 1,
#[doc = "2: Input indirect"]
Inputindirect = 2,
#[doc = "3: Input TRC"]
InputTrc = 3,
}
impl From<Cc1s> for u8 {
#[inline(always)]
fn from(variant: Cc1s) -> Self {
variant as _
}
}
impl crate::FieldSpec for Cc1s {
type Ux = u8;
}
impl crate::IsEnum for Cc1s {}
#[doc = "Field `CC1S` reader - Capture/Compare 1 selection"]
pub type Cc1sR = crate::FieldReader<Cc1s>;
impl Cc1sR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Cc1s {
match self.bits {
0 => Cc1s::Output,
1 => Cc1s::Inputdirect,
2 => Cc1s::Inputindirect,
3 => Cc1s::InputTrc,
_ => unreachable!(),
}
}
#[doc = "Output"]
#[inline(always)]
pub fn is_output(&self) -> bool {
*self == Cc1s::Output
}
#[doc = "Input direct"]
#[inline(always)]
pub fn is_inputdirect(&self) -> bool {
*self == Cc1s::Inputdirect
}
#[doc = "Input indirect"]
#[inline(always)]
pub fn is_inputindirect(&self) -> bool {
*self == Cc1s::Inputindirect
}
#[doc = "Input TRC"]
#[inline(always)]
pub fn is_input_trc(&self) -> bool {
*self == Cc1s::InputTrc
}
}
#[doc = "Field `CC1S` writer - Capture/Compare 1 selection"]
pub type Cc1sW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cc1s, crate::Safe>;
impl<'a, REG> Cc1sW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Output"]
#[inline(always)]
pub fn output(self) -> &'a mut crate::W<REG> {
self.variant(Cc1s::Output)
}
#[doc = "Input direct"]
#[inline(always)]
pub fn inputdirect(self) -> &'a mut crate::W<REG> {
self.variant(Cc1s::Inputdirect)
}
#[doc = "Input indirect"]
#[inline(always)]
pub fn inputindirect(self) -> &'a mut crate::W<REG> {
self.variant(Cc1s::Inputindirect)
}
#[doc = "Input TRC"]
#[inline(always)]
pub fn input_trc(self) -> &'a mut crate::W<REG> {
self.variant(Cc1s::InputTrc)
}
}
#[doc = "Field `OC1FE` reader - Output compare 1 fast enable"]
pub type Oc1feR = crate::BitReader;
#[doc = "Field `OC1FE` writer - Output compare 1 fast enable"]
pub type Oc1feW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OC1PE` reader - Output compare 1 preload enable"]
pub type Oc1peR = crate::BitReader;
#[doc = "Field `OC1PE` writer - Output compare 1 preload enable"]
pub type Oc1peW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Output compare 1 mode\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Oc1m {
#[doc = "0: Frozen"]
Frozen = 0,
#[doc = "1: Active"]
Active = 1,
#[doc = "2: Inactive"]
Inactive = 2,
#[doc = "3: Toggle"]
Toggle = 3,
#[doc = "4: Forced inactive"]
Forcedinactive = 4,
#[doc = "5: Forced active"]
Forcedactive = 5,
#[doc = "6: Pwm1"]
Pwm1 = 6,
#[doc = "7: Pwm2"]
Pwm2 = 7,
}
impl From<Oc1m> for u8 {
#[inline(always)]
fn from(variant: Oc1m) -> Self {
variant as _
}
}
impl crate::FieldSpec for Oc1m {
type Ux = u8;
}
impl crate::IsEnum for Oc1m {}
#[doc = "Field `OC1M` reader - Output compare 1 mode"]
pub type Oc1mR = crate::FieldReader<Oc1m>;
impl Oc1mR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Oc1m {
match self.bits {
0 => Oc1m::Frozen,
1 => Oc1m::Active,
2 => Oc1m::Inactive,
3 => Oc1m::Toggle,
4 => Oc1m::Forcedinactive,
5 => Oc1m::Forcedactive,
6 => Oc1m::Pwm1,
7 => Oc1m::Pwm2,
_ => unreachable!(),
}
}
#[doc = "Frozen"]
#[inline(always)]
pub fn is_frozen(&self) -> bool {
*self == Oc1m::Frozen
}
#[doc = "Active"]
#[inline(always)]
pub fn is_active(&self) -> bool {
*self == Oc1m::Active
}
#[doc = "Inactive"]
#[inline(always)]
pub fn is_inactive(&self) -> bool {
*self == Oc1m::Inactive
}
#[doc = "Toggle"]
#[inline(always)]
pub fn is_toggle(&self) -> bool {
*self == Oc1m::Toggle
}
#[doc = "Forced inactive"]
#[inline(always)]
pub fn is_forcedinactive(&self) -> bool {
*self == Oc1m::Forcedinactive
}
#[doc = "Forced active"]
#[inline(always)]
pub fn is_forcedactive(&self) -> bool {
*self == Oc1m::Forcedactive
}
#[doc = "Pwm1"]
#[inline(always)]
pub fn is_pwm1(&self) -> bool {
*self == Oc1m::Pwm1
}
#[doc = "Pwm2"]
#[inline(always)]
pub fn is_pwm2(&self) -> bool {
*self == Oc1m::Pwm2
}
}
#[doc = "Field `OC1M` writer - Output compare 1 mode"]
pub type Oc1mW<'a, REG> = crate::FieldWriter<'a, REG, 3, Oc1m, crate::Safe>;
impl<'a, REG> Oc1mW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Frozen"]
#[inline(always)]
pub fn frozen(self) -> &'a mut crate::W<REG> {
self.variant(Oc1m::Frozen)
}
#[doc = "Active"]
#[inline(always)]
pub fn active(self) -> &'a mut crate::W<REG> {
self.variant(Oc1m::Active)
}
#[doc = "Inactive"]
#[inline(always)]
pub fn inactive(self) -> &'a mut crate::W<REG> {
self.variant(Oc1m::Inactive)
}
#[doc = "Toggle"]
#[inline(always)]
pub fn toggle(self) -> &'a mut crate::W<REG> {
self.variant(Oc1m::Toggle)
}
#[doc = "Forced inactive"]
#[inline(always)]
pub fn forcedinactive(self) -> &'a mut crate::W<REG> {
self.variant(Oc1m::Forcedinactive)
}
#[doc = "Forced active"]
#[inline(always)]
pub fn forcedactive(self) -> &'a mut crate::W<REG> {
self.variant(Oc1m::Forcedactive)
}
#[doc = "Pwm1"]
#[inline(always)]
pub fn pwm1(self) -> &'a mut crate::W<REG> {
self.variant(Oc1m::Pwm1)
}
#[doc = "Pwm2"]
#[inline(always)]
pub fn pwm2(self) -> &'a mut crate::W<REG> {
self.variant(Oc1m::Pwm2)
}
}
#[doc = "Field `OC1CE` reader - Output compare 1 clear enable"]
pub type Oc1ceR = crate::BitReader;
#[doc = "Field `OC1CE` writer - Output compare 1 clear enable"]
pub type Oc1ceW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:1 - Capture/Compare 0 selection"]
#[inline(always)]
pub fn cc0s(&self) -> Cc0sR {
Cc0sR::new((self.bits & 3) as u8)
}
#[doc = "Bit 2 - Output compare 0 fast enable"]
#[inline(always)]
pub fn oc0fe(&self) -> Oc0feR {
Oc0feR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Output compare 0 preload enable"]
#[inline(always)]
pub fn oc0pe(&self) -> Oc0peR {
Oc0peR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bits 4:6 - Output compare 0 mode"]
#[inline(always)]
pub fn oc0m(&self) -> Oc0mR {
Oc0mR::new(((self.bits >> 4) & 7) as u8)
}
#[doc = "Bit 7 - Output compare 0 clear enable"]
#[inline(always)]
pub fn oc0ce(&self) -> Oc0ceR {
Oc0ceR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:9 - Capture/Compare 1 selection"]
#[inline(always)]
pub fn cc1s(&self) -> Cc1sR {
Cc1sR::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bit 10 - Output compare 1 fast enable"]
#[inline(always)]
pub fn oc1fe(&self) -> Oc1feR {
Oc1feR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - Output compare 1 preload enable"]
#[inline(always)]
pub fn oc1pe(&self) -> Oc1peR {
Oc1peR::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bits 12:14 - Output compare 1 mode"]
#[inline(always)]
pub fn oc1m(&self) -> Oc1mR {
Oc1mR::new(((self.bits >> 12) & 7) as u8)
}
#[doc = "Bit 15 - Output compare 1 clear enable"]
#[inline(always)]
pub fn oc1ce(&self) -> Oc1ceR {
Oc1ceR::new(((self.bits >> 15) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:1 - Capture/Compare 0 selection"]
#[inline(always)]
pub fn cc0s(&mut self) -> Cc0sW<Ccmr0OutputSpec> {
Cc0sW::new(self, 0)
}
#[doc = "Bit 2 - Output compare 0 fast enable"]
#[inline(always)]
pub fn oc0fe(&mut self) -> Oc0feW<Ccmr0OutputSpec> {
Oc0feW::new(self, 2)
}
#[doc = "Bit 3 - Output compare 0 preload enable"]
#[inline(always)]
pub fn oc0pe(&mut self) -> Oc0peW<Ccmr0OutputSpec> {
Oc0peW::new(self, 3)
}
#[doc = "Bits 4:6 - Output compare 0 mode"]
#[inline(always)]
pub fn oc0m(&mut self) -> Oc0mW<Ccmr0OutputSpec> {
Oc0mW::new(self, 4)
}
#[doc = "Bit 7 - Output compare 0 clear enable"]
#[inline(always)]
pub fn oc0ce(&mut self) -> Oc0ceW<Ccmr0OutputSpec> {
Oc0ceW::new(self, 7)
}
#[doc = "Bits 8:9 - Capture/Compare 1 selection"]
#[inline(always)]
pub fn cc1s(&mut self) -> Cc1sW<Ccmr0OutputSpec> {
Cc1sW::new(self, 8)
}
#[doc = "Bit 10 - Output compare 1 fast enable"]
#[inline(always)]
pub fn oc1fe(&mut self) -> Oc1feW<Ccmr0OutputSpec> {
Oc1feW::new(self, 10)
}
#[doc = "Bit 11 - Output compare 1 preload enable"]
#[inline(always)]
pub fn oc1pe(&mut self) -> Oc1peW<Ccmr0OutputSpec> {
Oc1peW::new(self, 11)
}
#[doc = "Bits 12:14 - Output compare 1 mode"]
#[inline(always)]
pub fn oc1m(&mut self) -> Oc1mW<Ccmr0OutputSpec> {
Oc1mW::new(self, 12)
}
#[doc = "Bit 15 - Output compare 1 clear enable"]
#[inline(always)]
pub fn oc1ce(&mut self) -> Oc1ceW<Ccmr0OutputSpec> {
Oc1ceW::new(self, 15)
}
}
#[doc = "Capture/compare mode register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ccmr0_output::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr0_output::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ccmr0OutputSpec;
impl crate::RegisterSpec for Ccmr0OutputSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ccmr0_output::R`](R) reader structure"]
impl crate::Readable for Ccmr0OutputSpec {}
#[doc = "`write(|w| ..)` method takes [`ccmr0_output::W`](W) writer structure"]
impl crate::Writable for Ccmr0OutputSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets CCMR0_output to value 0"]
impl crate::Resettable for Ccmr0OutputSpec {}
}
#[doc = "CCMR1_input (rw) register accessor: Capture/compare mode register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ccmr1_input::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr1_input::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccmr1_input`] module"]
#[doc(alias = "CCMR1_input")]
pub type Ccmr1Input = crate::Reg<ccmr1_input::Ccmr1InputSpec>;
#[doc = "Capture/compare mode register 1"]
pub mod ccmr1_input {
#[doc = "Register `CCMR1_input` reader"]
pub type R = crate::R<Ccmr1InputSpec>;
#[doc = "Register `CCMR1_input` writer"]
pub type W = crate::W<Ccmr1InputSpec>;
#[doc = "Capture/Compare 2 selection\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Cc2s {
#[doc = "0: Output"]
Output = 0,
#[doc = "1: Input direct"]
Inputdirect = 1,
#[doc = "2: Input indirect"]
Inputindirect = 2,
#[doc = "3: Input TRC"]
InputTrc = 3,
}
impl From<Cc2s> for u8 {
#[inline(always)]
fn from(variant: Cc2s) -> Self {
variant as _
}
}
impl crate::FieldSpec for Cc2s {
type Ux = u8;
}
impl crate::IsEnum for Cc2s {}
#[doc = "Field `CC2S` reader - Capture/Compare 2 selection"]
pub type Cc2sR = crate::FieldReader<Cc2s>;
impl Cc2sR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Cc2s {
match self.bits {
0 => Cc2s::Output,
1 => Cc2s::Inputdirect,
2 => Cc2s::Inputindirect,
3 => Cc2s::InputTrc,
_ => unreachable!(),
}
}
#[doc = "Output"]
#[inline(always)]
pub fn is_output(&self) -> bool {
*self == Cc2s::Output
}
#[doc = "Input direct"]
#[inline(always)]
pub fn is_inputdirect(&self) -> bool {
*self == Cc2s::Inputdirect
}
#[doc = "Input indirect"]
#[inline(always)]
pub fn is_inputindirect(&self) -> bool {
*self == Cc2s::Inputindirect
}
#[doc = "Input TRC"]
#[inline(always)]
pub fn is_input_trc(&self) -> bool {
*self == Cc2s::InputTrc
}
}
#[doc = "Field `CC2S` writer - Capture/Compare 2 selection"]
pub type Cc2sW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cc2s, crate::Safe>;
impl<'a, REG> Cc2sW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Output"]
#[inline(always)]
pub fn output(self) -> &'a mut crate::W<REG> {
self.variant(Cc2s::Output)
}
#[doc = "Input direct"]
#[inline(always)]
pub fn inputdirect(self) -> &'a mut crate::W<REG> {
self.variant(Cc2s::Inputdirect)
}
#[doc = "Input indirect"]
#[inline(always)]
pub fn inputindirect(self) -> &'a mut crate::W<REG> {
self.variant(Cc2s::Inputindirect)
}
#[doc = "Input TRC"]
#[inline(always)]
pub fn input_trc(self) -> &'a mut crate::W<REG> {
self.variant(Cc2s::InputTrc)
}
}
#[doc = "Input capture 2 prescaler\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Ic2psc {
#[doc = "0: Div 1"]
Div1 = 0,
#[doc = "1: Div 2"]
Div2 = 1,
#[doc = "2: Div 4"]
Div4 = 2,
#[doc = "3: Div 8"]
Div8 = 3,
}
impl From<Ic2psc> for u8 {
#[inline(always)]
fn from(variant: Ic2psc) -> Self {
variant as _
}
}
impl crate::FieldSpec for Ic2psc {
type Ux = u8;
}
impl crate::IsEnum for Ic2psc {}
#[doc = "Field `IC2PSC` reader - Input capture 2 prescaler"]
pub type Ic2pscR = crate::FieldReader<Ic2psc>;
impl Ic2pscR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Ic2psc {
match self.bits {
0 => Ic2psc::Div1,
1 => Ic2psc::Div2,
2 => Ic2psc::Div4,
3 => Ic2psc::Div8,
_ => unreachable!(),
}
}
#[doc = "Div 1"]
#[inline(always)]
pub fn is_div1(&self) -> bool {
*self == Ic2psc::Div1
}
#[doc = "Div 2"]
#[inline(always)]
pub fn is_div2(&self) -> bool {
*self == Ic2psc::Div2
}
#[doc = "Div 4"]
#[inline(always)]
pub fn is_div4(&self) -> bool {
*self == Ic2psc::Div4
}
#[doc = "Div 8"]
#[inline(always)]
pub fn is_div8(&self) -> bool {
*self == Ic2psc::Div8
}
}
#[doc = "Field `IC2PSC` writer - Input capture 2 prescaler"]
pub type Ic2pscW<'a, REG> = crate::FieldWriter<'a, REG, 2, Ic2psc, crate::Safe>;
impl<'a, REG> Ic2pscW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Div 1"]
#[inline(always)]
pub fn div1(self) -> &'a mut crate::W<REG> {
self.variant(Ic2psc::Div1)
}
#[doc = "Div 2"]
#[inline(always)]
pub fn div2(self) -> &'a mut crate::W<REG> {
self.variant(Ic2psc::Div2)
}
#[doc = "Div 4"]
#[inline(always)]
pub fn div4(self) -> &'a mut crate::W<REG> {
self.variant(Ic2psc::Div4)
}
#[doc = "Div 8"]
#[inline(always)]
pub fn div8(self) -> &'a mut crate::W<REG> {
self.variant(Ic2psc::Div8)
}
}
#[doc = "Input capture 2 filter\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Ic2f {
#[doc = "0: FDIV1"]
Fdiv1 = 0,
#[doc = "1: FDIV1_N2"]
Fdiv1N2 = 1,
#[doc = "2: FDIV1_N4"]
Fdiv1N4 = 2,
#[doc = "3: FDIV1_N8"]
Fdiv1N8 = 3,
#[doc = "4: FDIV2_N6"]
Fdiv2N6 = 4,
#[doc = "5: FDIV2_N8"]
Fdiv2N8 = 5,
#[doc = "6: FDIV4_N6"]
Fdiv4N6 = 6,
#[doc = "7: FDIV4_N8"]
Fdiv4N8 = 7,
#[doc = "8: FDIV8_N6"]
Fdiv8N6 = 8,
#[doc = "9: FDIV8_N8"]
Fdiv8N8 = 9,
#[doc = "10: FDIV16_N5"]
Fdiv16N5 = 10,
#[doc = "11: FDIV16_N6"]
Fdiv16N6 = 11,
#[doc = "12: FDIV16_N8"]
Fdiv16N8 = 12,
#[doc = "13: FDIV32_N5"]
Fdiv32N5 = 13,
#[doc = "14: FDIV32_N6"]
Fdiv32N6 = 14,
#[doc = "15: FDIV32_N8"]
Fdiv32N8 = 15,
}
impl From<Ic2f> for u8 {
#[inline(always)]
fn from(variant: Ic2f) -> Self {
variant as _
}
}
impl crate::FieldSpec for Ic2f {
type Ux = u8;
}
impl crate::IsEnum for Ic2f {}
#[doc = "Field `IC2F` reader - Input capture 2 filter"]
pub type Ic2fR = crate::FieldReader<Ic2f>;
impl Ic2fR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Ic2f {
match self.bits {
0 => Ic2f::Fdiv1,
1 => Ic2f::Fdiv1N2,
2 => Ic2f::Fdiv1N4,
3 => Ic2f::Fdiv1N8,
4 => Ic2f::Fdiv2N6,
5 => Ic2f::Fdiv2N8,
6 => Ic2f::Fdiv4N6,
7 => Ic2f::Fdiv4N8,
8 => Ic2f::Fdiv8N6,
9 => Ic2f::Fdiv8N8,
10 => Ic2f::Fdiv16N5,
11 => Ic2f::Fdiv16N6,
12 => Ic2f::Fdiv16N8,
13 => Ic2f::Fdiv32N5,
14 => Ic2f::Fdiv32N6,
15 => Ic2f::Fdiv32N8,
_ => unreachable!(),
}
}
#[doc = "FDIV1"]
#[inline(always)]
pub fn is_fdiv1(&self) -> bool {
*self == Ic2f::Fdiv1
}
#[doc = "FDIV1_N2"]
#[inline(always)]
pub fn is_fdiv1_n2(&self) -> bool {
*self == Ic2f::Fdiv1N2
}
#[doc = "FDIV1_N4"]
#[inline(always)]
pub fn is_fdiv1_n4(&self) -> bool {
*self == Ic2f::Fdiv1N4
}
#[doc = "FDIV1_N8"]
#[inline(always)]
pub fn is_fdiv1_n8(&self) -> bool {
*self == Ic2f::Fdiv1N8
}
#[doc = "FDIV2_N6"]
#[inline(always)]
pub fn is_fdiv2_n6(&self) -> bool {
*self == Ic2f::Fdiv2N6
}
#[doc = "FDIV2_N8"]
#[inline(always)]
pub fn is_fdiv2_n8(&self) -> bool {
*self == Ic2f::Fdiv2N8
}
#[doc = "FDIV4_N6"]
#[inline(always)]
pub fn is_fdiv4_n6(&self) -> bool {
*self == Ic2f::Fdiv4N6
}
#[doc = "FDIV4_N8"]
#[inline(always)]
pub fn is_fdiv4_n8(&self) -> bool {
*self == Ic2f::Fdiv4N8
}
#[doc = "FDIV8_N6"]
#[inline(always)]
pub fn is_fdiv8_n6(&self) -> bool {
*self == Ic2f::Fdiv8N6
}
#[doc = "FDIV8_N8"]
#[inline(always)]
pub fn is_fdiv8_n8(&self) -> bool {
*self == Ic2f::Fdiv8N8
}
#[doc = "FDIV16_N5"]
#[inline(always)]
pub fn is_fdiv16_n5(&self) -> bool {
*self == Ic2f::Fdiv16N5
}
#[doc = "FDIV16_N6"]
#[inline(always)]
pub fn is_fdiv16_n6(&self) -> bool {
*self == Ic2f::Fdiv16N6
}
#[doc = "FDIV16_N8"]
#[inline(always)]
pub fn is_fdiv16_n8(&self) -> bool {
*self == Ic2f::Fdiv16N8
}
#[doc = "FDIV32_N5"]
#[inline(always)]
pub fn is_fdiv32_n5(&self) -> bool {
*self == Ic2f::Fdiv32N5
}
#[doc = "FDIV32_N6"]
#[inline(always)]
pub fn is_fdiv32_n6(&self) -> bool {
*self == Ic2f::Fdiv32N6
}
#[doc = "FDIV32_N8"]
#[inline(always)]
pub fn is_fdiv32_n8(&self) -> bool {
*self == Ic2f::Fdiv32N8
}
}
#[doc = "Field `IC2F` writer - Input capture 2 filter"]
pub type Ic2fW<'a, REG> = crate::FieldWriter<'a, REG, 4, Ic2f, crate::Safe>;
impl<'a, REG> Ic2fW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "FDIV1"]
#[inline(always)]
pub fn fdiv1(self) -> &'a mut crate::W<REG> {
self.variant(Ic2f::Fdiv1)
}
#[doc = "FDIV1_N2"]
#[inline(always)]
pub fn fdiv1_n2(self) -> &'a mut crate::W<REG> {
self.variant(Ic2f::Fdiv1N2)
}
#[doc = "FDIV1_N4"]
#[inline(always)]
pub fn fdiv1_n4(self) -> &'a mut crate::W<REG> {
self.variant(Ic2f::Fdiv1N4)
}
#[doc = "FDIV1_N8"]
#[inline(always)]
pub fn fdiv1_n8(self) -> &'a mut crate::W<REG> {
self.variant(Ic2f::Fdiv1N8)
}
#[doc = "FDIV2_N6"]
#[inline(always)]
pub fn fdiv2_n6(self) -> &'a mut crate::W<REG> {
self.variant(Ic2f::Fdiv2N6)
}
#[doc = "FDIV2_N8"]
#[inline(always)]
pub fn fdiv2_n8(self) -> &'a mut crate::W<REG> {
self.variant(Ic2f::Fdiv2N8)
}
#[doc = "FDIV4_N6"]
#[inline(always)]
pub fn fdiv4_n6(self) -> &'a mut crate::W<REG> {
self.variant(Ic2f::Fdiv4N6)
}
#[doc = "FDIV4_N8"]
#[inline(always)]
pub fn fdiv4_n8(self) -> &'a mut crate::W<REG> {
self.variant(Ic2f::Fdiv4N8)
}
#[doc = "FDIV8_N6"]
#[inline(always)]
pub fn fdiv8_n6(self) -> &'a mut crate::W<REG> {
self.variant(Ic2f::Fdiv8N6)
}
#[doc = "FDIV8_N8"]
#[inline(always)]
pub fn fdiv8_n8(self) -> &'a mut crate::W<REG> {
self.variant(Ic2f::Fdiv8N8)
}
#[doc = "FDIV16_N5"]
#[inline(always)]
pub fn fdiv16_n5(self) -> &'a mut crate::W<REG> {
self.variant(Ic2f::Fdiv16N5)
}
#[doc = "FDIV16_N6"]
#[inline(always)]
pub fn fdiv16_n6(self) -> &'a mut crate::W<REG> {
self.variant(Ic2f::Fdiv16N6)
}
#[doc = "FDIV16_N8"]
#[inline(always)]
pub fn fdiv16_n8(self) -> &'a mut crate::W<REG> {
self.variant(Ic2f::Fdiv16N8)
}
#[doc = "FDIV32_N5"]
#[inline(always)]
pub fn fdiv32_n5(self) -> &'a mut crate::W<REG> {
self.variant(Ic2f::Fdiv32N5)
}
#[doc = "FDIV32_N6"]
#[inline(always)]
pub fn fdiv32_n6(self) -> &'a mut crate::W<REG> {
self.variant(Ic2f::Fdiv32N6)
}
#[doc = "FDIV32_N8"]
#[inline(always)]
pub fn fdiv32_n8(self) -> &'a mut crate::W<REG> {
self.variant(Ic2f::Fdiv32N8)
}
}
#[doc = "Capture/Compare 3 selection\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Cc3s {
#[doc = "0: Output"]
Output = 0,
#[doc = "1: Input direct"]
Inputdirect = 1,
#[doc = "2: Input indirect"]
Inputindirect = 2,
#[doc = "3: Input TRC"]
InputTrc = 3,
}
impl From<Cc3s> for u8 {
#[inline(always)]
fn from(variant: Cc3s) -> Self {
variant as _
}
}
impl crate::FieldSpec for Cc3s {
type Ux = u8;
}
impl crate::IsEnum for Cc3s {}
#[doc = "Field `CC3S` reader - Capture/Compare 3 selection"]
pub type Cc3sR = crate::FieldReader<Cc3s>;
impl Cc3sR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Cc3s {
match self.bits {
0 => Cc3s::Output,
1 => Cc3s::Inputdirect,
2 => Cc3s::Inputindirect,
3 => Cc3s::InputTrc,
_ => unreachable!(),
}
}
#[doc = "Output"]
#[inline(always)]
pub fn is_output(&self) -> bool {
*self == Cc3s::Output
}
#[doc = "Input direct"]
#[inline(always)]
pub fn is_inputdirect(&self) -> bool {
*self == Cc3s::Inputdirect
}
#[doc = "Input indirect"]
#[inline(always)]
pub fn is_inputindirect(&self) -> bool {
*self == Cc3s::Inputindirect
}
#[doc = "Input TRC"]
#[inline(always)]
pub fn is_input_trc(&self) -> bool {
*self == Cc3s::InputTrc
}
}
#[doc = "Field `CC3S` writer - Capture/Compare 3 selection"]
pub type Cc3sW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cc3s, crate::Safe>;
impl<'a, REG> Cc3sW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Output"]
#[inline(always)]
pub fn output(self) -> &'a mut crate::W<REG> {
self.variant(Cc3s::Output)
}
#[doc = "Input direct"]
#[inline(always)]
pub fn inputdirect(self) -> &'a mut crate::W<REG> {
self.variant(Cc3s::Inputdirect)
}
#[doc = "Input indirect"]
#[inline(always)]
pub fn inputindirect(self) -> &'a mut crate::W<REG> {
self.variant(Cc3s::Inputindirect)
}
#[doc = "Input TRC"]
#[inline(always)]
pub fn input_trc(self) -> &'a mut crate::W<REG> {
self.variant(Cc3s::InputTrc)
}
}
#[doc = "Input capture 3 prescaler\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Ic3psc {
#[doc = "0: Div 1"]
Div1 = 0,
#[doc = "1: Div 2"]
Div2 = 1,
#[doc = "2: Div 4"]
Div4 = 2,
#[doc = "3: Div 8"]
Div8 = 3,
}
impl From<Ic3psc> for u8 {
#[inline(always)]
fn from(variant: Ic3psc) -> Self {
variant as _
}
}
impl crate::FieldSpec for Ic3psc {
type Ux = u8;
}
impl crate::IsEnum for Ic3psc {}
#[doc = "Field `IC3PSC` reader - Input capture 3 prescaler"]
pub type Ic3pscR = crate::FieldReader<Ic3psc>;
impl Ic3pscR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Ic3psc {
match self.bits {
0 => Ic3psc::Div1,
1 => Ic3psc::Div2,
2 => Ic3psc::Div4,
3 => Ic3psc::Div8,
_ => unreachable!(),
}
}
#[doc = "Div 1"]
#[inline(always)]
pub fn is_div1(&self) -> bool {
*self == Ic3psc::Div1
}
#[doc = "Div 2"]
#[inline(always)]
pub fn is_div2(&self) -> bool {
*self == Ic3psc::Div2
}
#[doc = "Div 4"]
#[inline(always)]
pub fn is_div4(&self) -> bool {
*self == Ic3psc::Div4
}
#[doc = "Div 8"]
#[inline(always)]
pub fn is_div8(&self) -> bool {
*self == Ic3psc::Div8
}
}
#[doc = "Field `IC3PSC` writer - Input capture 3 prescaler"]
pub type Ic3pscW<'a, REG> = crate::FieldWriter<'a, REG, 2, Ic3psc, crate::Safe>;
impl<'a, REG> Ic3pscW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Div 1"]
#[inline(always)]
pub fn div1(self) -> &'a mut crate::W<REG> {
self.variant(Ic3psc::Div1)
}
#[doc = "Div 2"]
#[inline(always)]
pub fn div2(self) -> &'a mut crate::W<REG> {
self.variant(Ic3psc::Div2)
}
#[doc = "Div 4"]
#[inline(always)]
pub fn div4(self) -> &'a mut crate::W<REG> {
self.variant(Ic3psc::Div4)
}
#[doc = "Div 8"]
#[inline(always)]
pub fn div8(self) -> &'a mut crate::W<REG> {
self.variant(Ic3psc::Div8)
}
}
#[doc = "Input capture 3 filter\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Ic3f {
#[doc = "0: FDIV1"]
Fdiv1 = 0,
#[doc = "1: FDIV1_N2"]
Fdiv1N2 = 1,
#[doc = "2: FDIV1_N4"]
Fdiv1N4 = 2,
#[doc = "3: FDIV1_N8"]
Fdiv1N8 = 3,
#[doc = "4: FDIV2_N6"]
Fdiv2N6 = 4,
#[doc = "5: FDIV2_N8"]
Fdiv2N8 = 5,
#[doc = "6: FDIV4_N6"]
Fdiv4N6 = 6,
#[doc = "7: FDIV4_N8"]
Fdiv4N8 = 7,
#[doc = "8: FDIV8_N6"]
Fdiv8N6 = 8,
#[doc = "9: FDIV8_N8"]
Fdiv8N8 = 9,
#[doc = "10: FDIV16_N5"]
Fdiv16N5 = 10,
#[doc = "11: FDIV16_N6"]
Fdiv16N6 = 11,
#[doc = "12: FDIV16_N8"]
Fdiv16N8 = 12,
#[doc = "13: FDIV32_N5"]
Fdiv32N5 = 13,
#[doc = "14: FDIV32_N6"]
Fdiv32N6 = 14,
#[doc = "15: FDIV32_N8"]
Fdiv32N8 = 15,
}
impl From<Ic3f> for u8 {
#[inline(always)]
fn from(variant: Ic3f) -> Self {
variant as _
}
}
impl crate::FieldSpec for Ic3f {
type Ux = u8;
}
impl crate::IsEnum for Ic3f {}
#[doc = "Field `IC3F` reader - Input capture 3 filter"]
pub type Ic3fR = crate::FieldReader<Ic3f>;
impl Ic3fR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Ic3f {
match self.bits {
0 => Ic3f::Fdiv1,
1 => Ic3f::Fdiv1N2,
2 => Ic3f::Fdiv1N4,
3 => Ic3f::Fdiv1N8,
4 => Ic3f::Fdiv2N6,
5 => Ic3f::Fdiv2N8,
6 => Ic3f::Fdiv4N6,
7 => Ic3f::Fdiv4N8,
8 => Ic3f::Fdiv8N6,
9 => Ic3f::Fdiv8N8,
10 => Ic3f::Fdiv16N5,
11 => Ic3f::Fdiv16N6,
12 => Ic3f::Fdiv16N8,
13 => Ic3f::Fdiv32N5,
14 => Ic3f::Fdiv32N6,
15 => Ic3f::Fdiv32N8,
_ => unreachable!(),
}
}
#[doc = "FDIV1"]
#[inline(always)]
pub fn is_fdiv1(&self) -> bool {
*self == Ic3f::Fdiv1
}
#[doc = "FDIV1_N2"]
#[inline(always)]
pub fn is_fdiv1_n2(&self) -> bool {
*self == Ic3f::Fdiv1N2
}
#[doc = "FDIV1_N4"]
#[inline(always)]
pub fn is_fdiv1_n4(&self) -> bool {
*self == Ic3f::Fdiv1N4
}
#[doc = "FDIV1_N8"]
#[inline(always)]
pub fn is_fdiv1_n8(&self) -> bool {
*self == Ic3f::Fdiv1N8
}
#[doc = "FDIV2_N6"]
#[inline(always)]
pub fn is_fdiv2_n6(&self) -> bool {
*self == Ic3f::Fdiv2N6
}
#[doc = "FDIV2_N8"]
#[inline(always)]
pub fn is_fdiv2_n8(&self) -> bool {
*self == Ic3f::Fdiv2N8
}
#[doc = "FDIV4_N6"]
#[inline(always)]
pub fn is_fdiv4_n6(&self) -> bool {
*self == Ic3f::Fdiv4N6
}
#[doc = "FDIV4_N8"]
#[inline(always)]
pub fn is_fdiv4_n8(&self) -> bool {
*self == Ic3f::Fdiv4N8
}
#[doc = "FDIV8_N6"]
#[inline(always)]
pub fn is_fdiv8_n6(&self) -> bool {
*self == Ic3f::Fdiv8N6
}
#[doc = "FDIV8_N8"]
#[inline(always)]
pub fn is_fdiv8_n8(&self) -> bool {
*self == Ic3f::Fdiv8N8
}
#[doc = "FDIV16_N5"]
#[inline(always)]
pub fn is_fdiv16_n5(&self) -> bool {
*self == Ic3f::Fdiv16N5
}
#[doc = "FDIV16_N6"]
#[inline(always)]
pub fn is_fdiv16_n6(&self) -> bool {
*self == Ic3f::Fdiv16N6
}
#[doc = "FDIV16_N8"]
#[inline(always)]
pub fn is_fdiv16_n8(&self) -> bool {
*self == Ic3f::Fdiv16N8
}
#[doc = "FDIV32_N5"]
#[inline(always)]
pub fn is_fdiv32_n5(&self) -> bool {
*self == Ic3f::Fdiv32N5
}
#[doc = "FDIV32_N6"]
#[inline(always)]
pub fn is_fdiv32_n6(&self) -> bool {
*self == Ic3f::Fdiv32N6
}
#[doc = "FDIV32_N8"]
#[inline(always)]
pub fn is_fdiv32_n8(&self) -> bool {
*self == Ic3f::Fdiv32N8
}
}
#[doc = "Field `IC3F` writer - Input capture 3 filter"]
pub type Ic3fW<'a, REG> = crate::FieldWriter<'a, REG, 4, Ic3f, crate::Safe>;
impl<'a, REG> Ic3fW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "FDIV1"]
#[inline(always)]
pub fn fdiv1(self) -> &'a mut crate::W<REG> {
self.variant(Ic3f::Fdiv1)
}
#[doc = "FDIV1_N2"]
#[inline(always)]
pub fn fdiv1_n2(self) -> &'a mut crate::W<REG> {
self.variant(Ic3f::Fdiv1N2)
}
#[doc = "FDIV1_N4"]
#[inline(always)]
pub fn fdiv1_n4(self) -> &'a mut crate::W<REG> {
self.variant(Ic3f::Fdiv1N4)
}
#[doc = "FDIV1_N8"]
#[inline(always)]
pub fn fdiv1_n8(self) -> &'a mut crate::W<REG> {
self.variant(Ic3f::Fdiv1N8)
}
#[doc = "FDIV2_N6"]
#[inline(always)]
pub fn fdiv2_n6(self) -> &'a mut crate::W<REG> {
self.variant(Ic3f::Fdiv2N6)
}
#[doc = "FDIV2_N8"]
#[inline(always)]
pub fn fdiv2_n8(self) -> &'a mut crate::W<REG> {
self.variant(Ic3f::Fdiv2N8)
}
#[doc = "FDIV4_N6"]
#[inline(always)]
pub fn fdiv4_n6(self) -> &'a mut crate::W<REG> {
self.variant(Ic3f::Fdiv4N6)
}
#[doc = "FDIV4_N8"]
#[inline(always)]
pub fn fdiv4_n8(self) -> &'a mut crate::W<REG> {
self.variant(Ic3f::Fdiv4N8)
}
#[doc = "FDIV8_N6"]
#[inline(always)]
pub fn fdiv8_n6(self) -> &'a mut crate::W<REG> {
self.variant(Ic3f::Fdiv8N6)
}
#[doc = "FDIV8_N8"]
#[inline(always)]
pub fn fdiv8_n8(self) -> &'a mut crate::W<REG> {
self.variant(Ic3f::Fdiv8N8)
}
#[doc = "FDIV16_N5"]
#[inline(always)]
pub fn fdiv16_n5(self) -> &'a mut crate::W<REG> {
self.variant(Ic3f::Fdiv16N5)
}
#[doc = "FDIV16_N6"]
#[inline(always)]
pub fn fdiv16_n6(self) -> &'a mut crate::W<REG> {
self.variant(Ic3f::Fdiv16N6)
}
#[doc = "FDIV16_N8"]
#[inline(always)]
pub fn fdiv16_n8(self) -> &'a mut crate::W<REG> {
self.variant(Ic3f::Fdiv16N8)
}
#[doc = "FDIV32_N5"]
#[inline(always)]
pub fn fdiv32_n5(self) -> &'a mut crate::W<REG> {
self.variant(Ic3f::Fdiv32N5)
}
#[doc = "FDIV32_N6"]
#[inline(always)]
pub fn fdiv32_n6(self) -> &'a mut crate::W<REG> {
self.variant(Ic3f::Fdiv32N6)
}
#[doc = "FDIV32_N8"]
#[inline(always)]
pub fn fdiv32_n8(self) -> &'a mut crate::W<REG> {
self.variant(Ic3f::Fdiv32N8)
}
}
impl R {
#[doc = "Bits 0:1 - Capture/Compare 2 selection"]
#[inline(always)]
pub fn cc2s(&self) -> Cc2sR {
Cc2sR::new((self.bits & 3) as u8)
}
#[doc = "Bits 2:3 - Input capture 2 prescaler"]
#[inline(always)]
pub fn ic2psc(&self) -> Ic2pscR {
Ic2pscR::new(((self.bits >> 2) & 3) as u8)
}
#[doc = "Bits 4:7 - Input capture 2 filter"]
#[inline(always)]
pub fn ic2f(&self) -> Ic2fR {
Ic2fR::new(((self.bits >> 4) & 0x0f) as u8)
}
#[doc = "Bits 8:9 - Capture/Compare 3 selection"]
#[inline(always)]
pub fn cc3s(&self) -> Cc3sR {
Cc3sR::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bits 10:11 - Input capture 3 prescaler"]
#[inline(always)]
pub fn ic3psc(&self) -> Ic3pscR {
Ic3pscR::new(((self.bits >> 10) & 3) as u8)
}
#[doc = "Bits 12:15 - Input capture 3 filter"]
#[inline(always)]
pub fn ic3f(&self) -> Ic3fR {
Ic3fR::new(((self.bits >> 12) & 0x0f) as u8)
}
}
impl W {
#[doc = "Bits 0:1 - Capture/Compare 2 selection"]
#[inline(always)]
pub fn cc2s(&mut self) -> Cc2sW<Ccmr1InputSpec> {
Cc2sW::new(self, 0)
}
#[doc = "Bits 2:3 - Input capture 2 prescaler"]
#[inline(always)]
pub fn ic2psc(&mut self) -> Ic2pscW<Ccmr1InputSpec> {
Ic2pscW::new(self, 2)
}
#[doc = "Bits 4:7 - Input capture 2 filter"]
#[inline(always)]
pub fn ic2f(&mut self) -> Ic2fW<Ccmr1InputSpec> {
Ic2fW::new(self, 4)
}
#[doc = "Bits 8:9 - Capture/Compare 3 selection"]
#[inline(always)]
pub fn cc3s(&mut self) -> Cc3sW<Ccmr1InputSpec> {
Cc3sW::new(self, 8)
}
#[doc = "Bits 10:11 - Input capture 3 prescaler"]
#[inline(always)]
pub fn ic3psc(&mut self) -> Ic3pscW<Ccmr1InputSpec> {
Ic3pscW::new(self, 10)
}
#[doc = "Bits 12:15 - Input capture 3 filter"]
#[inline(always)]
pub fn ic3f(&mut self) -> Ic3fW<Ccmr1InputSpec> {
Ic3fW::new(self, 12)
}
}
#[doc = "Capture/compare mode register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ccmr1_input::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr1_input::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ccmr1InputSpec;
impl crate::RegisterSpec for Ccmr1InputSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ccmr1_input::R`](R) reader structure"]
impl crate::Readable for Ccmr1InputSpec {}
#[doc = "`write(|w| ..)` method takes [`ccmr1_input::W`](W) writer structure"]
impl crate::Writable for Ccmr1InputSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets CCMR1_input to value 0"]
impl crate::Resettable for Ccmr1InputSpec {}
}
#[doc = "CCMR1_output (rw) register accessor: Capture/compare mode register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ccmr1_output::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr1_output::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccmr1_output`] module"]
#[doc(alias = "CCMR1_output")]
pub type Ccmr1Output = crate::Reg<ccmr1_output::Ccmr1OutputSpec>;
#[doc = "Capture/compare mode register 1"]
pub mod ccmr1_output {
#[doc = "Register `CCMR1_output` reader"]
pub type R = crate::R<Ccmr1OutputSpec>;
#[doc = "Register `CCMR1_output` writer"]
pub type W = crate::W<Ccmr1OutputSpec>;
#[doc = "Capture/Compare 2 selection\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Cc2s {
#[doc = "0: Output"]
Output = 0,
#[doc = "1: Input direct"]
Inputdirect = 1,
#[doc = "2: Input indirect"]
Inputindirect = 2,
#[doc = "3: Input TRC"]
InputTrc = 3,
}
impl From<Cc2s> for u8 {
#[inline(always)]
fn from(variant: Cc2s) -> Self {
variant as _
}
}
impl crate::FieldSpec for Cc2s {
type Ux = u8;
}
impl crate::IsEnum for Cc2s {}
#[doc = "Field `CC2S` reader - Capture/Compare 2 selection"]
pub type Cc2sR = crate::FieldReader<Cc2s>;
impl Cc2sR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Cc2s {
match self.bits {
0 => Cc2s::Output,
1 => Cc2s::Inputdirect,
2 => Cc2s::Inputindirect,
3 => Cc2s::InputTrc,
_ => unreachable!(),
}
}
#[doc = "Output"]
#[inline(always)]
pub fn is_output(&self) -> bool {
*self == Cc2s::Output
}
#[doc = "Input direct"]
#[inline(always)]
pub fn is_inputdirect(&self) -> bool {
*self == Cc2s::Inputdirect
}
#[doc = "Input indirect"]
#[inline(always)]
pub fn is_inputindirect(&self) -> bool {
*self == Cc2s::Inputindirect
}
#[doc = "Input TRC"]
#[inline(always)]
pub fn is_input_trc(&self) -> bool {
*self == Cc2s::InputTrc
}
}
#[doc = "Field `CC2S` writer - Capture/Compare 2 selection"]
pub type Cc2sW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cc2s, crate::Safe>;
impl<'a, REG> Cc2sW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Output"]
#[inline(always)]
pub fn output(self) -> &'a mut crate::W<REG> {
self.variant(Cc2s::Output)
}
#[doc = "Input direct"]
#[inline(always)]
pub fn inputdirect(self) -> &'a mut crate::W<REG> {
self.variant(Cc2s::Inputdirect)
}
#[doc = "Input indirect"]
#[inline(always)]
pub fn inputindirect(self) -> &'a mut crate::W<REG> {
self.variant(Cc2s::Inputindirect)
}
#[doc = "Input TRC"]
#[inline(always)]
pub fn input_trc(self) -> &'a mut crate::W<REG> {
self.variant(Cc2s::InputTrc)
}
}
#[doc = "Field `OC2FE` reader - Output compare 2 fast enable"]
pub type Oc2feR = crate::BitReader;
#[doc = "Field `OC2FE` writer - Output compare 2 fast enable"]
pub type Oc2feW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OC2PE` reader - Output compare 2 preload enable"]
pub type Oc2peR = crate::BitReader;
#[doc = "Field `OC2PE` writer - Output compare 2 preload enable"]
pub type Oc2peW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Output compare 2 mode\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Oc2m {
#[doc = "0: Frozen"]
Frozen = 0,
#[doc = "1: Active"]
Active = 1,
#[doc = "2: Inactive"]
Inactive = 2,
#[doc = "3: Toggle"]
Toggle = 3,
#[doc = "4: Forced inactive"]
Forcedinactive = 4,
#[doc = "5: Forced active"]
Forcedactive = 5,
#[doc = "6: Pwm1"]
Pwm1 = 6,
#[doc = "7: Pwm2"]
Pwm2 = 7,
}
impl From<Oc2m> for u8 {
#[inline(always)]
fn from(variant: Oc2m) -> Self {
variant as _
}
}
impl crate::FieldSpec for Oc2m {
type Ux = u8;
}
impl crate::IsEnum for Oc2m {}
#[doc = "Field `OC2M` reader - Output compare 2 mode"]
pub type Oc2mR = crate::FieldReader<Oc2m>;
impl Oc2mR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Oc2m {
match self.bits {
0 => Oc2m::Frozen,
1 => Oc2m::Active,
2 => Oc2m::Inactive,
3 => Oc2m::Toggle,
4 => Oc2m::Forcedinactive,
5 => Oc2m::Forcedactive,
6 => Oc2m::Pwm1,
7 => Oc2m::Pwm2,
_ => unreachable!(),
}
}
#[doc = "Frozen"]
#[inline(always)]
pub fn is_frozen(&self) -> bool {
*self == Oc2m::Frozen
}
#[doc = "Active"]
#[inline(always)]
pub fn is_active(&self) -> bool {
*self == Oc2m::Active
}
#[doc = "Inactive"]
#[inline(always)]
pub fn is_inactive(&self) -> bool {
*self == Oc2m::Inactive
}
#[doc = "Toggle"]
#[inline(always)]
pub fn is_toggle(&self) -> bool {
*self == Oc2m::Toggle
}
#[doc = "Forced inactive"]
#[inline(always)]
pub fn is_forcedinactive(&self) -> bool {
*self == Oc2m::Forcedinactive
}
#[doc = "Forced active"]
#[inline(always)]
pub fn is_forcedactive(&self) -> bool {
*self == Oc2m::Forcedactive
}
#[doc = "Pwm1"]
#[inline(always)]
pub fn is_pwm1(&self) -> bool {
*self == Oc2m::Pwm1
}
#[doc = "Pwm2"]
#[inline(always)]
pub fn is_pwm2(&self) -> bool {
*self == Oc2m::Pwm2
}
}
#[doc = "Field `OC2M` writer - Output compare 2 mode"]
pub type Oc2mW<'a, REG> = crate::FieldWriter<'a, REG, 3, Oc2m, crate::Safe>;
impl<'a, REG> Oc2mW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Frozen"]
#[inline(always)]
pub fn frozen(self) -> &'a mut crate::W<REG> {
self.variant(Oc2m::Frozen)
}
#[doc = "Active"]
#[inline(always)]
pub fn active(self) -> &'a mut crate::W<REG> {
self.variant(Oc2m::Active)
}
#[doc = "Inactive"]
#[inline(always)]
pub fn inactive(self) -> &'a mut crate::W<REG> {
self.variant(Oc2m::Inactive)
}
#[doc = "Toggle"]
#[inline(always)]
pub fn toggle(self) -> &'a mut crate::W<REG> {
self.variant(Oc2m::Toggle)
}
#[doc = "Forced inactive"]
#[inline(always)]
pub fn forcedinactive(self) -> &'a mut crate::W<REG> {
self.variant(Oc2m::Forcedinactive)
}
#[doc = "Forced active"]
#[inline(always)]
pub fn forcedactive(self) -> &'a mut crate::W<REG> {
self.variant(Oc2m::Forcedactive)
}
#[doc = "Pwm1"]
#[inline(always)]
pub fn pwm1(self) -> &'a mut crate::W<REG> {
self.variant(Oc2m::Pwm1)
}
#[doc = "Pwm2"]
#[inline(always)]
pub fn pwm2(self) -> &'a mut crate::W<REG> {
self.variant(Oc2m::Pwm2)
}
}
#[doc = "Field `OC2CE` reader - Output compare 2 clear enable"]
pub type Oc2ceR = crate::BitReader;
#[doc = "Field `OC2CE` writer - Output compare 2 clear enable"]
pub type Oc2ceW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Capture/Compare 3 selection\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Cc3s {
#[doc = "0: Output"]
Output = 0,
#[doc = "1: Input direct"]
Inputdirect = 1,
#[doc = "2: Input indirect"]
Inputindirect = 2,
#[doc = "3: Input TRC"]
InputTrc = 3,
}
impl From<Cc3s> for u8 {
#[inline(always)]
fn from(variant: Cc3s) -> Self {
variant as _
}
}
impl crate::FieldSpec for Cc3s {
type Ux = u8;
}
impl crate::IsEnum for Cc3s {}
#[doc = "Field `CC3S` reader - Capture/Compare 3 selection"]
pub type Cc3sR = crate::FieldReader<Cc3s>;
impl Cc3sR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Cc3s {
match self.bits {
0 => Cc3s::Output,
1 => Cc3s::Inputdirect,
2 => Cc3s::Inputindirect,
3 => Cc3s::InputTrc,
_ => unreachable!(),
}
}
#[doc = "Output"]
#[inline(always)]
pub fn is_output(&self) -> bool {
*self == Cc3s::Output
}
#[doc = "Input direct"]
#[inline(always)]
pub fn is_inputdirect(&self) -> bool {
*self == Cc3s::Inputdirect
}
#[doc = "Input indirect"]
#[inline(always)]
pub fn is_inputindirect(&self) -> bool {
*self == Cc3s::Inputindirect
}
#[doc = "Input TRC"]
#[inline(always)]
pub fn is_input_trc(&self) -> bool {
*self == Cc3s::InputTrc
}
}
#[doc = "Field `CC3S` writer - Capture/Compare 3 selection"]
pub type Cc3sW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cc3s, crate::Safe>;
impl<'a, REG> Cc3sW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Output"]
#[inline(always)]
pub fn output(self) -> &'a mut crate::W<REG> {
self.variant(Cc3s::Output)
}
#[doc = "Input direct"]
#[inline(always)]
pub fn inputdirect(self) -> &'a mut crate::W<REG> {
self.variant(Cc3s::Inputdirect)
}
#[doc = "Input indirect"]
#[inline(always)]
pub fn inputindirect(self) -> &'a mut crate::W<REG> {
self.variant(Cc3s::Inputindirect)
}
#[doc = "Input TRC"]
#[inline(always)]
pub fn input_trc(self) -> &'a mut crate::W<REG> {
self.variant(Cc3s::InputTrc)
}
}
#[doc = "Field `OC3FE` reader - Output compare 3 fast enable"]
pub type Oc3feR = crate::BitReader;
#[doc = "Field `OC3FE` writer - Output compare 3 fast enable"]
pub type Oc3feW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OC3PE` reader - Output compare 3 preload enable"]
pub type Oc3peR = crate::BitReader;
#[doc = "Field `OC3PE` writer - Output compare 3 preload enable"]
pub type Oc3peW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Output compare 3 mode\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Oc3m {
#[doc = "0: Frozen"]
Frozen = 0,
#[doc = "1: Active"]
Active = 1,
#[doc = "2: Inactive"]
Inactive = 2,
#[doc = "3: Toggle"]
Toggle = 3,
#[doc = "4: Forced inactive"]
Forcedinactive = 4,
#[doc = "5: Forced active"]
Forcedactive = 5,
#[doc = "6: Pwm1"]
Pwm1 = 6,
#[doc = "7: Pwm2"]
Pwm2 = 7,
}
impl From<Oc3m> for u8 {
#[inline(always)]
fn from(variant: Oc3m) -> Self {
variant as _
}
}
impl crate::FieldSpec for Oc3m {
type Ux = u8;
}
impl crate::IsEnum for Oc3m {}
#[doc = "Field `OC3M` reader - Output compare 3 mode"]
pub type Oc3mR = crate::FieldReader<Oc3m>;
impl Oc3mR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Oc3m {
match self.bits {
0 => Oc3m::Frozen,
1 => Oc3m::Active,
2 => Oc3m::Inactive,
3 => Oc3m::Toggle,
4 => Oc3m::Forcedinactive,
5 => Oc3m::Forcedactive,
6 => Oc3m::Pwm1,
7 => Oc3m::Pwm2,
_ => unreachable!(),
}
}
#[doc = "Frozen"]
#[inline(always)]
pub fn is_frozen(&self) -> bool {
*self == Oc3m::Frozen
}
#[doc = "Active"]
#[inline(always)]
pub fn is_active(&self) -> bool {
*self == Oc3m::Active
}
#[doc = "Inactive"]
#[inline(always)]
pub fn is_inactive(&self) -> bool {
*self == Oc3m::Inactive
}
#[doc = "Toggle"]
#[inline(always)]
pub fn is_toggle(&self) -> bool {
*self == Oc3m::Toggle
}
#[doc = "Forced inactive"]
#[inline(always)]
pub fn is_forcedinactive(&self) -> bool {
*self == Oc3m::Forcedinactive
}
#[doc = "Forced active"]
#[inline(always)]
pub fn is_forcedactive(&self) -> bool {
*self == Oc3m::Forcedactive
}
#[doc = "Pwm1"]
#[inline(always)]
pub fn is_pwm1(&self) -> bool {
*self == Oc3m::Pwm1
}
#[doc = "Pwm2"]
#[inline(always)]
pub fn is_pwm2(&self) -> bool {
*self == Oc3m::Pwm2
}
}
#[doc = "Field `OC3M` writer - Output compare 3 mode"]
pub type Oc3mW<'a, REG> = crate::FieldWriter<'a, REG, 3, Oc3m, crate::Safe>;
impl<'a, REG> Oc3mW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Frozen"]
#[inline(always)]
pub fn frozen(self) -> &'a mut crate::W<REG> {
self.variant(Oc3m::Frozen)
}
#[doc = "Active"]
#[inline(always)]
pub fn active(self) -> &'a mut crate::W<REG> {
self.variant(Oc3m::Active)
}
#[doc = "Inactive"]
#[inline(always)]
pub fn inactive(self) -> &'a mut crate::W<REG> {
self.variant(Oc3m::Inactive)
}
#[doc = "Toggle"]
#[inline(always)]
pub fn toggle(self) -> &'a mut crate::W<REG> {
self.variant(Oc3m::Toggle)
}
#[doc = "Forced inactive"]
#[inline(always)]
pub fn forcedinactive(self) -> &'a mut crate::W<REG> {
self.variant(Oc3m::Forcedinactive)
}
#[doc = "Forced active"]
#[inline(always)]
pub fn forcedactive(self) -> &'a mut crate::W<REG> {
self.variant(Oc3m::Forcedactive)
}
#[doc = "Pwm1"]
#[inline(always)]
pub fn pwm1(self) -> &'a mut crate::W<REG> {
self.variant(Oc3m::Pwm1)
}
#[doc = "Pwm2"]
#[inline(always)]
pub fn pwm2(self) -> &'a mut crate::W<REG> {
self.variant(Oc3m::Pwm2)
}
}
#[doc = "Field `OC3CE` reader - Output compare 3 clear enable"]
pub type Oc3ceR = crate::BitReader;
#[doc = "Field `OC3CE` writer - Output compare 3 clear enable"]
pub type Oc3ceW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:1 - Capture/Compare 2 selection"]
#[inline(always)]
pub fn cc2s(&self) -> Cc2sR {
Cc2sR::new((self.bits & 3) as u8)
}
#[doc = "Bit 2 - Output compare 2 fast enable"]
#[inline(always)]
pub fn oc2fe(&self) -> Oc2feR {
Oc2feR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Output compare 2 preload enable"]
#[inline(always)]
pub fn oc2pe(&self) -> Oc2peR {
Oc2peR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bits 4:6 - Output compare 2 mode"]
#[inline(always)]
pub fn oc2m(&self) -> Oc2mR {
Oc2mR::new(((self.bits >> 4) & 7) as u8)
}
#[doc = "Bit 7 - Output compare 2 clear enable"]
#[inline(always)]
pub fn oc2ce(&self) -> Oc2ceR {
Oc2ceR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bits 8:9 - Capture/Compare 3 selection"]
#[inline(always)]
pub fn cc3s(&self) -> Cc3sR {
Cc3sR::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bit 10 - Output compare 3 fast enable"]
#[inline(always)]
pub fn oc3fe(&self) -> Oc3feR {
Oc3feR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - Output compare 3 preload enable"]
#[inline(always)]
pub fn oc3pe(&self) -> Oc3peR {
Oc3peR::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bits 12:14 - Output compare 3 mode"]
#[inline(always)]
pub fn oc3m(&self) -> Oc3mR {
Oc3mR::new(((self.bits >> 12) & 7) as u8)
}
#[doc = "Bit 15 - Output compare 3 clear enable"]
#[inline(always)]
pub fn oc3ce(&self) -> Oc3ceR {
Oc3ceR::new(((self.bits >> 15) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:1 - Capture/Compare 2 selection"]
#[inline(always)]
pub fn cc2s(&mut self) -> Cc2sW<Ccmr1OutputSpec> {
Cc2sW::new(self, 0)
}
#[doc = "Bit 2 - Output compare 2 fast enable"]
#[inline(always)]
pub fn oc2fe(&mut self) -> Oc2feW<Ccmr1OutputSpec> {
Oc2feW::new(self, 2)
}
#[doc = "Bit 3 - Output compare 2 preload enable"]
#[inline(always)]
pub fn oc2pe(&mut self) -> Oc2peW<Ccmr1OutputSpec> {
Oc2peW::new(self, 3)
}
#[doc = "Bits 4:6 - Output compare 2 mode"]
#[inline(always)]
pub fn oc2m(&mut self) -> Oc2mW<Ccmr1OutputSpec> {
Oc2mW::new(self, 4)
}
#[doc = "Bit 7 - Output compare 2 clear enable"]
#[inline(always)]
pub fn oc2ce(&mut self) -> Oc2ceW<Ccmr1OutputSpec> {
Oc2ceW::new(self, 7)
}
#[doc = "Bits 8:9 - Capture/Compare 3 selection"]
#[inline(always)]
pub fn cc3s(&mut self) -> Cc3sW<Ccmr1OutputSpec> {
Cc3sW::new(self, 8)
}
#[doc = "Bit 10 - Output compare 3 fast enable"]
#[inline(always)]
pub fn oc3fe(&mut self) -> Oc3feW<Ccmr1OutputSpec> {
Oc3feW::new(self, 10)
}
#[doc = "Bit 11 - Output compare 3 preload enable"]
#[inline(always)]
pub fn oc3pe(&mut self) -> Oc3peW<Ccmr1OutputSpec> {
Oc3peW::new(self, 11)
}
#[doc = "Bits 12:14 - Output compare 3 mode"]
#[inline(always)]
pub fn oc3m(&mut self) -> Oc3mW<Ccmr1OutputSpec> {
Oc3mW::new(self, 12)
}
#[doc = "Bit 15 - Output compare 3 clear enable"]
#[inline(always)]
pub fn oc3ce(&mut self) -> Oc3ceW<Ccmr1OutputSpec> {
Oc3ceW::new(self, 15)
}
}
#[doc = "Capture/compare mode register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ccmr1_output::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr1_output::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ccmr1OutputSpec;
impl crate::RegisterSpec for Ccmr1OutputSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ccmr1_output::R`](R) reader structure"]
impl crate::Readable for Ccmr1OutputSpec {}
#[doc = "`write(|w| ..)` method takes [`ccmr1_output::W`](W) writer structure"]
impl crate::Writable for Ccmr1OutputSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets CCMR1_output to value 0"]
impl crate::Resettable for Ccmr1OutputSpec {}
}
#[doc = "CCER (rw) register accessor: Capture/compare enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`ccer::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccer::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccer`] module"]
#[doc(alias = "CCER")]
pub type Ccer = crate::Reg<ccer::CcerSpec>;
#[doc = "Capture/compare enable register"]
pub mod ccer {
#[doc = "Register `CCER` reader"]
pub type R = crate::R<CcerSpec>;
#[doc = "Register `CCER` writer"]
pub type W = crate::W<CcerSpec>;
#[doc = "Field `CC0E` reader - Capture/Compare 0 output enable"]
pub type Cc0eR = crate::BitReader;
#[doc = "Field `CC0E` writer - Capture/Compare 0 output enable"]
pub type Cc0eW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Capture/Compare 0 output polarity\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Cc0p {
#[doc = "0: Active High"]
ActiveHigh = 0,
#[doc = "1: Active Low"]
ActiveLow = 1,
}
impl From<Cc0p> for bool {
#[inline(always)]
fn from(variant: Cc0p) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `CC0P` reader - Capture/Compare 0 output polarity"]
pub type Cc0pR = crate::BitReader<Cc0p>;
impl Cc0pR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Cc0p {
match self.bits {
false => Cc0p::ActiveHigh,
true => Cc0p::ActiveLow,
}
}
#[doc = "Active High"]
#[inline(always)]
pub fn is_active_high(&self) -> bool {
*self == Cc0p::ActiveHigh
}
#[doc = "Active Low"]
#[inline(always)]
pub fn is_active_low(&self) -> bool {
*self == Cc0p::ActiveLow
}
}
#[doc = "Field `CC0P` writer - Capture/Compare 0 output polarity"]
pub type Cc0pW<'a, REG> = crate::BitWriter<'a, REG, Cc0p>;
impl<'a, REG> Cc0pW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Active High"]
#[inline(always)]
pub fn active_high(self) -> &'a mut crate::W<REG> {
self.variant(Cc0p::ActiveHigh)
}
#[doc = "Active Low"]
#[inline(always)]
pub fn active_low(self) -> &'a mut crate::W<REG> {
self.variant(Cc0p::ActiveLow)
}
}
#[doc = "Field `CC0NE` reader - Capture/Compare 0 complementary output enable"]
pub type Cc0neR = crate::BitReader;
#[doc = "Field `CC0NE` writer - Capture/Compare 0 complementary output enable"]
pub type Cc0neW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Capture/Compare 0 complementary output polarity\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Cc0np {
#[doc = "0: Active High"]
ActiveHigh = 0,
#[doc = "1: Active Low"]
ActiveLow = 1,
}
impl From<Cc0np> for bool {
#[inline(always)]
fn from(variant: Cc0np) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `CC0NP` reader - Capture/Compare 0 complementary output polarity"]
pub type Cc0npR = crate::BitReader<Cc0np>;
impl Cc0npR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Cc0np {
match self.bits {
false => Cc0np::ActiveHigh,
true => Cc0np::ActiveLow,
}
}
#[doc = "Active High"]
#[inline(always)]
pub fn is_active_high(&self) -> bool {
*self == Cc0np::ActiveHigh
}
#[doc = "Active Low"]
#[inline(always)]
pub fn is_active_low(&self) -> bool {
*self == Cc0np::ActiveLow
}
}
#[doc = "Field `CC0NP` writer - Capture/Compare 0 complementary output polarity"]
pub type Cc0npW<'a, REG> = crate::BitWriter<'a, REG, Cc0np>;
impl<'a, REG> Cc0npW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Active High"]
#[inline(always)]
pub fn active_high(self) -> &'a mut crate::W<REG> {
self.variant(Cc0np::ActiveHigh)
}
#[doc = "Active Low"]
#[inline(always)]
pub fn active_low(self) -> &'a mut crate::W<REG> {
self.variant(Cc0np::ActiveLow)
}
}
#[doc = "Field `CC1E` reader - Capture/Compare 1 output enable"]
pub type Cc1eR = crate::BitReader;
#[doc = "Field `CC1E` writer - Capture/Compare 1 output enable"]
pub type Cc1eW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Capture/Compare 1 output polarity\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Cc1p {
#[doc = "0: Active High"]
ActiveHigh = 0,
#[doc = "1: Active Low"]
ActiveLow = 1,
}
impl From<Cc1p> for bool {
#[inline(always)]
fn from(variant: Cc1p) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `CC1P` reader - Capture/Compare 1 output polarity"]
pub type Cc1pR = crate::BitReader<Cc1p>;
impl Cc1pR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Cc1p {
match self.bits {
false => Cc1p::ActiveHigh,
true => Cc1p::ActiveLow,
}
}
#[doc = "Active High"]
#[inline(always)]
pub fn is_active_high(&self) -> bool {
*self == Cc1p::ActiveHigh
}
#[doc = "Active Low"]
#[inline(always)]
pub fn is_active_low(&self) -> bool {
*self == Cc1p::ActiveLow
}
}
#[doc = "Field `CC1P` writer - Capture/Compare 1 output polarity"]
pub type Cc1pW<'a, REG> = crate::BitWriter<'a, REG, Cc1p>;
impl<'a, REG> Cc1pW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Active High"]
#[inline(always)]
pub fn active_high(self) -> &'a mut crate::W<REG> {
self.variant(Cc1p::ActiveHigh)
}
#[doc = "Active Low"]
#[inline(always)]
pub fn active_low(self) -> &'a mut crate::W<REG> {
self.variant(Cc1p::ActiveLow)
}
}
#[doc = "Field `CC1NE` reader - Capture/Compare 1 complementary output enable"]
pub type Cc1neR = crate::BitReader;
#[doc = "Field `CC1NE` writer - Capture/Compare 1 complementary output enable"]
pub type Cc1neW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Capture/Compare 1 complementary output polarity\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Cc1np {
#[doc = "0: Active High"]
ActiveHigh = 0,
#[doc = "1: Active Low"]
ActiveLow = 1,
}
impl From<Cc1np> for bool {
#[inline(always)]
fn from(variant: Cc1np) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `CC1NP` reader - Capture/Compare 1 complementary output polarity"]
pub type Cc1npR = crate::BitReader<Cc1np>;
impl Cc1npR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Cc1np {
match self.bits {
false => Cc1np::ActiveHigh,
true => Cc1np::ActiveLow,
}
}
#[doc = "Active High"]
#[inline(always)]
pub fn is_active_high(&self) -> bool {
*self == Cc1np::ActiveHigh
}
#[doc = "Active Low"]
#[inline(always)]
pub fn is_active_low(&self) -> bool {
*self == Cc1np::ActiveLow
}
}
#[doc = "Field `CC1NP` writer - Capture/Compare 1 complementary output polarity"]
pub type Cc1npW<'a, REG> = crate::BitWriter<'a, REG, Cc1np>;
impl<'a, REG> Cc1npW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Active High"]
#[inline(always)]
pub fn active_high(self) -> &'a mut crate::W<REG> {
self.variant(Cc1np::ActiveHigh)
}
#[doc = "Active Low"]
#[inline(always)]
pub fn active_low(self) -> &'a mut crate::W<REG> {
self.variant(Cc1np::ActiveLow)
}
}
#[doc = "Field `CC2E` reader - Capture/Compare 2 output enable"]
pub type Cc2eR = crate::BitReader;
#[doc = "Field `CC2E` writer - Capture/Compare 2 output enable"]
pub type Cc2eW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Capture/Compare 2 output polarity\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Cc2p {
#[doc = "0: Active High"]
ActiveHigh = 0,
#[doc = "1: Active Low"]
ActiveLow = 1,
}
impl From<Cc2p> for bool {
#[inline(always)]
fn from(variant: Cc2p) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `CC2P` reader - Capture/Compare 2 output polarity"]
pub type Cc2pR = crate::BitReader<Cc2p>;
impl Cc2pR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Cc2p {
match self.bits {
false => Cc2p::ActiveHigh,
true => Cc2p::ActiveLow,
}
}
#[doc = "Active High"]
#[inline(always)]
pub fn is_active_high(&self) -> bool {
*self == Cc2p::ActiveHigh
}
#[doc = "Active Low"]
#[inline(always)]
pub fn is_active_low(&self) -> bool {
*self == Cc2p::ActiveLow
}
}
#[doc = "Field `CC2P` writer - Capture/Compare 2 output polarity"]
pub type Cc2pW<'a, REG> = crate::BitWriter<'a, REG, Cc2p>;
impl<'a, REG> Cc2pW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Active High"]
#[inline(always)]
pub fn active_high(self) -> &'a mut crate::W<REG> {
self.variant(Cc2p::ActiveHigh)
}
#[doc = "Active Low"]
#[inline(always)]
pub fn active_low(self) -> &'a mut crate::W<REG> {
self.variant(Cc2p::ActiveLow)
}
}
#[doc = "Field `CC2NE` reader - Capture/Compare 2 complementary output enable"]
pub type Cc2neR = crate::BitReader;
#[doc = "Field `CC2NE` writer - Capture/Compare 2 complementary output enable"]
pub type Cc2neW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Capture/Compare 2 complementary output polarity\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Cc2np {
#[doc = "0: Active High"]
ActiveHigh = 0,
#[doc = "1: Active Low"]
ActiveLow = 1,
}
impl From<Cc2np> for bool {
#[inline(always)]
fn from(variant: Cc2np) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `CC2NP` reader - Capture/Compare 2 complementary output polarity"]
pub type Cc2npR = crate::BitReader<Cc2np>;
impl Cc2npR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Cc2np {
match self.bits {
false => Cc2np::ActiveHigh,
true => Cc2np::ActiveLow,
}
}
#[doc = "Active High"]
#[inline(always)]
pub fn is_active_high(&self) -> bool {
*self == Cc2np::ActiveHigh
}
#[doc = "Active Low"]
#[inline(always)]
pub fn is_active_low(&self) -> bool {
*self == Cc2np::ActiveLow
}
}
#[doc = "Field `CC2NP` writer - Capture/Compare 2 complementary output polarity"]
pub type Cc2npW<'a, REG> = crate::BitWriter<'a, REG, Cc2np>;
impl<'a, REG> Cc2npW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Active High"]
#[inline(always)]
pub fn active_high(self) -> &'a mut crate::W<REG> {
self.variant(Cc2np::ActiveHigh)
}
#[doc = "Active Low"]
#[inline(always)]
pub fn active_low(self) -> &'a mut crate::W<REG> {
self.variant(Cc2np::ActiveLow)
}
}
#[doc = "Field `CC3E` reader - Capture/Compare 3 output enable"]
pub type Cc3eR = crate::BitReader;
#[doc = "Field `CC3E` writer - Capture/Compare 3 output enable"]
pub type Cc3eW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Capture/Compare 3 output polarity\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Cc3p {
#[doc = "0: Active High"]
ActiveHigh = 0,
#[doc = "1: Active Low"]
ActiveLow = 1,
}
impl From<Cc3p> for bool {
#[inline(always)]
fn from(variant: Cc3p) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `CC3P` reader - Capture/Compare 3 output polarity"]
pub type Cc3pR = crate::BitReader<Cc3p>;
impl Cc3pR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Cc3p {
match self.bits {
false => Cc3p::ActiveHigh,
true => Cc3p::ActiveLow,
}
}
#[doc = "Active High"]
#[inline(always)]
pub fn is_active_high(&self) -> bool {
*self == Cc3p::ActiveHigh
}
#[doc = "Active Low"]
#[inline(always)]
pub fn is_active_low(&self) -> bool {
*self == Cc3p::ActiveLow
}
}
#[doc = "Field `CC3P` writer - Capture/Compare 3 output polarity"]
pub type Cc3pW<'a, REG> = crate::BitWriter<'a, REG, Cc3p>;
impl<'a, REG> Cc3pW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Active High"]
#[inline(always)]
pub fn active_high(self) -> &'a mut crate::W<REG> {
self.variant(Cc3p::ActiveHigh)
}
#[doc = "Active Low"]
#[inline(always)]
pub fn active_low(self) -> &'a mut crate::W<REG> {
self.variant(Cc3p::ActiveLow)
}
}
#[doc = "Field `CC3NE` reader - Capture/Compare 3 complementary output enable"]
pub type Cc3neR = crate::BitReader;
#[doc = "Field `CC3NE` writer - Capture/Compare 3 complementary output enable"]
pub type Cc3neW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Capture/Compare 3 complementary output polarity\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Cc3np {
#[doc = "0: Active High"]
ActiveHigh = 0,
#[doc = "1: Active Low"]
ActiveLow = 1,
}
impl From<Cc3np> for bool {
#[inline(always)]
fn from(variant: Cc3np) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `CC3NP` reader - Capture/Compare 3 complementary output polarity"]
pub type Cc3npR = crate::BitReader<Cc3np>;
impl Cc3npR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Cc3np {
match self.bits {
false => Cc3np::ActiveHigh,
true => Cc3np::ActiveLow,
}
}
#[doc = "Active High"]
#[inline(always)]
pub fn is_active_high(&self) -> bool {
*self == Cc3np::ActiveHigh
}
#[doc = "Active Low"]
#[inline(always)]
pub fn is_active_low(&self) -> bool {
*self == Cc3np::ActiveLow
}
}
#[doc = "Field `CC3NP` writer - Capture/Compare 3 complementary output polarity"]
pub type Cc3npW<'a, REG> = crate::BitWriter<'a, REG, Cc3np>;
impl<'a, REG> Cc3npW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Active High"]
#[inline(always)]
pub fn active_high(self) -> &'a mut crate::W<REG> {
self.variant(Cc3np::ActiveHigh)
}
#[doc = "Active Low"]
#[inline(always)]
pub fn active_low(self) -> &'a mut crate::W<REG> {
self.variant(Cc3np::ActiveLow)
}
}
impl R {
#[doc = "Bit 0 - Capture/Compare 0 output enable"]
#[inline(always)]
pub fn cc0e(&self) -> Cc0eR {
Cc0eR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Capture/Compare 0 output polarity"]
#[inline(always)]
pub fn cc0p(&self) -> Cc0pR {
Cc0pR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Capture/Compare 0 complementary output enable"]
#[inline(always)]
pub fn cc0ne(&self) -> Cc0neR {
Cc0neR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Capture/Compare 0 complementary output polarity"]
#[inline(always)]
pub fn cc0np(&self) -> Cc0npR {
Cc0npR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Capture/Compare 1 output enable"]
#[inline(always)]
pub fn cc1e(&self) -> Cc1eR {
Cc1eR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Capture/Compare 1 output polarity"]
#[inline(always)]
pub fn cc1p(&self) -> Cc1pR {
Cc1pR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Capture/Compare 1 complementary output enable"]
#[inline(always)]
pub fn cc1ne(&self) -> Cc1neR {
Cc1neR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Capture/Compare 1 complementary output polarity"]
#[inline(always)]
pub fn cc1np(&self) -> Cc1npR {
Cc1npR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - Capture/Compare 2 output enable"]
#[inline(always)]
pub fn cc2e(&self) -> Cc2eR {
Cc2eR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - Capture/Compare 2 output polarity"]
#[inline(always)]
pub fn cc2p(&self) -> Cc2pR {
Cc2pR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - Capture/Compare 2 complementary output enable"]
#[inline(always)]
pub fn cc2ne(&self) -> Cc2neR {
Cc2neR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - Capture/Compare 2 complementary output polarity"]
#[inline(always)]
pub fn cc2np(&self) -> Cc2npR {
Cc2npR::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12 - Capture/Compare 3 output enable"]
#[inline(always)]
pub fn cc3e(&self) -> Cc3eR {
Cc3eR::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13 - Capture/Compare 3 output polarity"]
#[inline(always)]
pub fn cc3p(&self) -> Cc3pR {
Cc3pR::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - Capture/Compare 3 complementary output enable"]
#[inline(always)]
pub fn cc3ne(&self) -> Cc3neR {
Cc3neR::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15 - Capture/Compare 3 complementary output polarity"]
#[inline(always)]
pub fn cc3np(&self) -> Cc3npR {
Cc3npR::new(((self.bits >> 15) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Capture/Compare 0 output enable"]
#[inline(always)]
pub fn cc0e(&mut self) -> Cc0eW<CcerSpec> {
Cc0eW::new(self, 0)
}
#[doc = "Bit 1 - Capture/Compare 0 output polarity"]
#[inline(always)]
pub fn cc0p(&mut self) -> Cc0pW<CcerSpec> {
Cc0pW::new(self, 1)
}
#[doc = "Bit 2 - Capture/Compare 0 complementary output enable"]
#[inline(always)]
pub fn cc0ne(&mut self) -> Cc0neW<CcerSpec> {
Cc0neW::new(self, 2)
}
#[doc = "Bit 3 - Capture/Compare 0 complementary output polarity"]
#[inline(always)]
pub fn cc0np(&mut self) -> Cc0npW<CcerSpec> {
Cc0npW::new(self, 3)
}
#[doc = "Bit 4 - Capture/Compare 1 output enable"]
#[inline(always)]
pub fn cc1e(&mut self) -> Cc1eW<CcerSpec> {
Cc1eW::new(self, 4)
}
#[doc = "Bit 5 - Capture/Compare 1 output polarity"]
#[inline(always)]
pub fn cc1p(&mut self) -> Cc1pW<CcerSpec> {
Cc1pW::new(self, 5)
}
#[doc = "Bit 6 - Capture/Compare 1 complementary output enable"]
#[inline(always)]
pub fn cc1ne(&mut self) -> Cc1neW<CcerSpec> {
Cc1neW::new(self, 6)
}
#[doc = "Bit 7 - Capture/Compare 1 complementary output polarity"]
#[inline(always)]
pub fn cc1np(&mut self) -> Cc1npW<CcerSpec> {
Cc1npW::new(self, 7)
}
#[doc = "Bit 8 - Capture/Compare 2 output enable"]
#[inline(always)]
pub fn cc2e(&mut self) -> Cc2eW<CcerSpec> {
Cc2eW::new(self, 8)
}
#[doc = "Bit 9 - Capture/Compare 2 output polarity"]
#[inline(always)]
pub fn cc2p(&mut self) -> Cc2pW<CcerSpec> {
Cc2pW::new(self, 9)
}
#[doc = "Bit 10 - Capture/Compare 2 complementary output enable"]
#[inline(always)]
pub fn cc2ne(&mut self) -> Cc2neW<CcerSpec> {
Cc2neW::new(self, 10)
}
#[doc = "Bit 11 - Capture/Compare 2 complementary output polarity"]
#[inline(always)]
pub fn cc2np(&mut self) -> Cc2npW<CcerSpec> {
Cc2npW::new(self, 11)
}
#[doc = "Bit 12 - Capture/Compare 3 output enable"]
#[inline(always)]
pub fn cc3e(&mut self) -> Cc3eW<CcerSpec> {
Cc3eW::new(self, 12)
}
#[doc = "Bit 13 - Capture/Compare 3 output polarity"]
#[inline(always)]
pub fn cc3p(&mut self) -> Cc3pW<CcerSpec> {
Cc3pW::new(self, 13)
}
#[doc = "Bit 14 - Capture/Compare 3 complementary output enable"]
#[inline(always)]
pub fn cc3ne(&mut self) -> Cc3neW<CcerSpec> {
Cc3neW::new(self, 14)
}
#[doc = "Bit 15 - Capture/Compare 3 complementary output polarity"]
#[inline(always)]
pub fn cc3np(&mut self) -> Cc3npW<CcerSpec> {
Cc3npW::new(self, 15)
}
}
#[doc = "Capture/compare enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`ccer::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccer::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CcerSpec;
impl crate::RegisterSpec for CcerSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ccer::R`](R) reader structure"]
impl crate::Readable for CcerSpec {}
#[doc = "`write(|w| ..)` method takes [`ccer::W`](W) writer structure"]
impl crate::Writable for CcerSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets CCER to value 0"]
impl crate::Resettable for CcerSpec {}
}
#[doc = "CNT (rw) register accessor: Counter\n\nYou can [`read`](crate::Reg::read) this register and get [`cnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cnt`] module"]
#[doc(alias = "CNT")]
pub type Cnt = crate::Reg<cnt::CntSpec>;
#[doc = "Counter"]
pub mod cnt {
#[doc = "Register `CNT` reader"]
pub type R = crate::R<CntSpec>;
#[doc = "Register `CNT` writer"]
pub type W = crate::W<CntSpec>;
#[doc = "Field `CNT` reader - Counter"]
pub type CntR = crate::FieldReader<u32>;
#[doc = "Field `CNT` writer - Counter"]
pub type CntW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - Counter"]
#[inline(always)]
pub fn cnt(&self) -> CntR {
CntR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - Counter"]
#[inline(always)]
pub fn cnt(&mut self) -> CntW<CntSpec> {
CntW::new(self, 0)
}
}
#[doc = "Counter\n\nYou can [`read`](crate::Reg::read) this register and get [`cnt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cnt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CntSpec;
impl crate::RegisterSpec for CntSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cnt::R`](R) reader structure"]
impl crate::Readable for CntSpec {}
#[doc = "`write(|w| ..)` method takes [`cnt::W`](W) writer structure"]
impl crate::Writable for CntSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets CNT to value 0"]
impl crate::Resettable for CntSpec {}
}
#[doc = "PSC (rw) register accessor: Prescaler\n\nYou can [`read`](crate::Reg::read) this register and get [`psc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@psc`] module"]
#[doc(alias = "PSC")]
pub type Psc = crate::Reg<psc::PscSpec>;
#[doc = "Prescaler"]
pub mod psc {
#[doc = "Register `PSC` reader"]
pub type R = crate::R<PscSpec>;
#[doc = "Register `PSC` writer"]
pub type W = crate::W<PscSpec>;
#[doc = "Field `PSC` reader - Prescaler"]
pub type PscR = crate::FieldReader<u16>;
#[doc = "Field `PSC` writer - Prescaler"]
pub type PscW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - Prescaler"]
#[inline(always)]
pub fn psc(&self) -> PscR {
PscR::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15 - Prescaler"]
#[inline(always)]
pub fn psc(&mut self) -> PscW<PscSpec> {
PscW::new(self, 0)
}
}
#[doc = "Prescaler\n\nYou can [`read`](crate::Reg::read) this register and get [`psc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PscSpec;
impl crate::RegisterSpec for PscSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`psc::R`](R) reader structure"]
impl crate::Readable for PscSpec {}
#[doc = "`write(|w| ..)` method takes [`psc::W`](W) writer structure"]
impl crate::Writable for PscSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets PSC to value 0"]
impl crate::Resettable for PscSpec {}
}
#[doc = "ARR (rw) register accessor: Auto reload register\n\nYou can [`read`](crate::Reg::read) this register and get [`arr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`arr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@arr`] module"]
#[doc(alias = "ARR")]
pub type Arr = crate::Reg<arr::ArrSpec>;
#[doc = "Auto reload register"]
pub mod arr {
#[doc = "Register `ARR` reader"]
pub type R = crate::R<ArrSpec>;
#[doc = "Register `ARR` writer"]
pub type W = crate::W<ArrSpec>;
#[doc = "Field `ARR` reader - Auto reload register"]
pub type ArrR = crate::FieldReader<u32>;
#[doc = "Field `ARR` writer - Auto reload register"]
pub type ArrW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - Auto reload register"]
#[inline(always)]
pub fn arr(&self) -> ArrR {
ArrR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - Auto reload register"]
#[inline(always)]
pub fn arr(&mut self) -> ArrW<ArrSpec> {
ArrW::new(self, 0)
}
}
#[doc = "Auto reload register\n\nYou can [`read`](crate::Reg::read) this register and get [`arr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`arr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ArrSpec;
impl crate::RegisterSpec for ArrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`arr::R`](R) reader structure"]
impl crate::Readable for ArrSpec {}
#[doc = "`write(|w| ..)` method takes [`arr::W`](W) writer structure"]
impl crate::Writable for ArrSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ARR to value 0"]
impl crate::Resettable for ArrSpec {}
}
#[doc = "RCR (rw) register accessor: Repetition counter register\n\nYou can [`read`](crate::Reg::read) this register and get [`rcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rcr`] module"]
#[doc(alias = "RCR")]
pub type Rcr = crate::Reg<rcr::RcrSpec>;
#[doc = "Repetition counter register"]
pub mod rcr {
#[doc = "Register `RCR` reader"]
pub type R = crate::R<RcrSpec>;
#[doc = "Register `RCR` writer"]
pub type W = crate::W<RcrSpec>;
#[doc = "Field `RCR` reader - Repetition counter register"]
pub type RcrR = crate::FieldReader<u16>;
#[doc = "Field `RCR` writer - Repetition counter register"]
pub type RcrW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - Repetition counter register"]
#[inline(always)]
pub fn rcr(&self) -> RcrR {
RcrR::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15 - Repetition counter register"]
#[inline(always)]
pub fn rcr(&mut self) -> RcrW<RcrSpec> {
RcrW::new(self, 0)
}
}
#[doc = "Repetition counter register\n\nYou can [`read`](crate::Reg::read) this register and get [`rcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RcrSpec;
impl crate::RegisterSpec for RcrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rcr::R`](R) reader structure"]
impl crate::Readable for RcrSpec {}
#[doc = "`write(|w| ..)` method takes [`rcr::W`](W) writer structure"]
impl crate::Writable for RcrSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets RCR to value 0"]
impl crate::Resettable for RcrSpec {}
}
#[doc = "CCR0 (rw) register accessor: Capture compare register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ccr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccr0`] module"]
#[doc(alias = "CCR0")]
pub type Ccr0 = crate::Reg<ccr0::Ccr0Spec>;
#[doc = "Capture compare register 0"]
pub mod ccr0 {
#[doc = "Register `CCR0` reader"]
pub type R = crate::R<Ccr0Spec>;
#[doc = "Register `CCR0` writer"]
pub type W = crate::W<Ccr0Spec>;
#[doc = "Field `CCR0` reader - Capture compare register 0"]
pub type Ccr0R = crate::FieldReader<u32>;
#[doc = "Field `CCR0` writer - Capture compare register 0"]
pub type Ccr0W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - Capture compare register 0"]
#[inline(always)]
pub fn ccr0(&self) -> Ccr0R {
Ccr0R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - Capture compare register 0"]
#[inline(always)]
pub fn ccr0(&mut self) -> Ccr0W<Ccr0Spec> {
Ccr0W::new(self, 0)
}
}
#[doc = "Capture compare register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ccr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ccr0Spec;
impl crate::RegisterSpec for Ccr0Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ccr0::R`](R) reader structure"]
impl crate::Readable for Ccr0Spec {}
#[doc = "`write(|w| ..)` method takes [`ccr0::W`](W) writer structure"]
impl crate::Writable for Ccr0Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets CCR0 to value 0"]
impl crate::Resettable for Ccr0Spec {}
}
#[doc = "CCR1 (rw) register accessor: Capture compare register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ccr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccr1`] module"]
#[doc(alias = "CCR1")]
pub type Ccr1 = crate::Reg<ccr1::Ccr1Spec>;
#[doc = "Capture compare register 1"]
pub mod ccr1 {
#[doc = "Register `CCR1` reader"]
pub type R = crate::R<Ccr1Spec>;
#[doc = "Register `CCR1` writer"]
pub type W = crate::W<Ccr1Spec>;
#[doc = "Field `CCR1` reader - Capture compare register 1"]
pub type Ccr1R = crate::FieldReader<u32>;
#[doc = "Field `CCR1` writer - Capture compare register 1"]
pub type Ccr1W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - Capture compare register 1"]
#[inline(always)]
pub fn ccr1(&self) -> Ccr1R {
Ccr1R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - Capture compare register 1"]
#[inline(always)]
pub fn ccr1(&mut self) -> Ccr1W<Ccr1Spec> {
Ccr1W::new(self, 0)
}
}
#[doc = "Capture compare register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ccr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ccr1Spec;
impl crate::RegisterSpec for Ccr1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ccr1::R`](R) reader structure"]
impl crate::Readable for Ccr1Spec {}
#[doc = "`write(|w| ..)` method takes [`ccr1::W`](W) writer structure"]
impl crate::Writable for Ccr1Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets CCR1 to value 0"]
impl crate::Resettable for Ccr1Spec {}
}
#[doc = "CCR2 (rw) register accessor: Capture compare register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`ccr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccr2`] module"]
#[doc(alias = "CCR2")]
pub type Ccr2 = crate::Reg<ccr2::Ccr2Spec>;
#[doc = "Capture compare register 2"]
pub mod ccr2 {
#[doc = "Register `CCR2` reader"]
pub type R = crate::R<Ccr2Spec>;
#[doc = "Register `CCR2` writer"]
pub type W = crate::W<Ccr2Spec>;
#[doc = "Field `CCR2` reader - Capture compare register 2"]
pub type Ccr2R = crate::FieldReader<u32>;
#[doc = "Field `CCR2` writer - Capture compare register 2"]
pub type Ccr2W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - Capture compare register 2"]
#[inline(always)]
pub fn ccr2(&self) -> Ccr2R {
Ccr2R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - Capture compare register 2"]
#[inline(always)]
pub fn ccr2(&mut self) -> Ccr2W<Ccr2Spec> {
Ccr2W::new(self, 0)
}
}
#[doc = "Capture compare register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`ccr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ccr2Spec;
impl crate::RegisterSpec for Ccr2Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ccr2::R`](R) reader structure"]
impl crate::Readable for Ccr2Spec {}
#[doc = "`write(|w| ..)` method takes [`ccr2::W`](W) writer structure"]
impl crate::Writable for Ccr2Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets CCR2 to value 0"]
impl crate::Resettable for Ccr2Spec {}
}
#[doc = "CCR3 (rw) register accessor: Capture compare register 3\n\nYou can [`read`](crate::Reg::read) this register and get [`ccr3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccr3`] module"]
#[doc(alias = "CCR3")]
pub type Ccr3 = crate::Reg<ccr3::Ccr3Spec>;
#[doc = "Capture compare register 3"]
pub mod ccr3 {
#[doc = "Register `CCR3` reader"]
pub type R = crate::R<Ccr3Spec>;
#[doc = "Register `CCR3` writer"]
pub type W = crate::W<Ccr3Spec>;
#[doc = "Field `CCR3` reader - Capture compare register 3"]
pub type Ccr3R = crate::FieldReader<u32>;
#[doc = "Field `CCR3` writer - Capture compare register 3"]
pub type Ccr3W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - Capture compare register 3"]
#[inline(always)]
pub fn ccr3(&self) -> Ccr3R {
Ccr3R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - Capture compare register 3"]
#[inline(always)]
pub fn ccr3(&mut self) -> Ccr3W<Ccr3Spec> {
Ccr3W::new(self, 0)
}
}
#[doc = "Capture compare register 3\n\nYou can [`read`](crate::Reg::read) this register and get [`ccr3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ccr3Spec;
impl crate::RegisterSpec for Ccr3Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ccr3::R`](R) reader structure"]
impl crate::Readable for Ccr3Spec {}
#[doc = "`write(|w| ..)` method takes [`ccr3::W`](W) writer structure"]
impl crate::Writable for Ccr3Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets CCR3 to value 0"]
impl crate::Resettable for Ccr3Spec {}
}
#[doc = "BDTR (rw) register accessor: Break and dead time register\n\nYou can [`read`](crate::Reg::read) this register and get [`bdtr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bdtr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bdtr`] module"]
#[doc(alias = "BDTR")]
pub type Bdtr = crate::Reg<bdtr::BdtrSpec>;
#[doc = "Break and dead time register"]
pub mod bdtr {
#[doc = "Register `BDTR` reader"]
pub type R = crate::R<BdtrSpec>;
#[doc = "Register `BDTR` writer"]
pub type W = crate::W<BdtrSpec>;
#[doc = "Field `DTG` reader - Dead-Time generator setup"]
pub type DtgR = crate::FieldReader;
#[doc = "Field `DTG` writer - Dead-Time generator setup"]
pub type DtgW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Lock configuration\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Lock {
#[doc = "0: Lock Off"]
LockOff = 0,
#[doc = "1: Lock Level 1"]
LockLevel1 = 1,
#[doc = "2: Lock Level 2"]
LockLevel2 = 2,
#[doc = "3: Lock Level 3"]
LockLevel3 = 3,
}
impl From<Lock> for u8 {
#[inline(always)]
fn from(variant: Lock) -> Self {
variant as _
}
}
impl crate::FieldSpec for Lock {
type Ux = u8;
}
impl crate::IsEnum for Lock {}
#[doc = "Field `LOCK` reader - Lock configuration"]
pub type LockR = crate::FieldReader<Lock>;
impl LockR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Lock {
match self.bits {
0 => Lock::LockOff,
1 => Lock::LockLevel1,
2 => Lock::LockLevel2,
3 => Lock::LockLevel3,
_ => unreachable!(),
}
}
#[doc = "Lock Off"]
#[inline(always)]
pub fn is_lock_off(&self) -> bool {
*self == Lock::LockOff
}
#[doc = "Lock Level 1"]
#[inline(always)]
pub fn is_lock_level1(&self) -> bool {
*self == Lock::LockLevel1
}
#[doc = "Lock Level 2"]
#[inline(always)]
pub fn is_lock_level2(&self) -> bool {
*self == Lock::LockLevel2
}
#[doc = "Lock Level 3"]
#[inline(always)]
pub fn is_lock_level3(&self) -> bool {
*self == Lock::LockLevel3
}
}
#[doc = "Field `LOCK` writer - Lock configuration"]
pub type LockW<'a, REG> = crate::FieldWriter<'a, REG, 2, Lock, crate::Safe>;
impl<'a, REG> LockW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Lock Off"]
#[inline(always)]
pub fn lock_off(self) -> &'a mut crate::W<REG> {
self.variant(Lock::LockOff)
}
#[doc = "Lock Level 1"]
#[inline(always)]
pub fn lock_level1(self) -> &'a mut crate::W<REG> {
self.variant(Lock::LockLevel1)
}
#[doc = "Lock Level 2"]
#[inline(always)]
pub fn lock_level2(self) -> &'a mut crate::W<REG> {
self.variant(Lock::LockLevel2)
}
#[doc = "Lock Level 3"]
#[inline(always)]
pub fn lock_level3(self) -> &'a mut crate::W<REG> {
self.variant(Lock::LockLevel3)
}
}
#[doc = "Field `OSSI` reader - Off-State selection for idle mode"]
pub type OssiR = crate::BitReader;
#[doc = "Field `OSSI` writer - Off-State selection for idle mode"]
pub type OssiW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OSSR` reader - Off-State selection for run mode"]
pub type OssrR = crate::BitReader;
#[doc = "Field `OSSR` writer - Off-State selection for run mode"]
pub type OssrW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `BKE` reader - Break enable"]
pub type BkeR = crate::BitReader;
#[doc = "Field `BKE` writer - Break enable"]
pub type BkeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Break polarity\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Bkp {
#[doc = "0: Active Low"]
ActiveLow = 0,
#[doc = "1: Active High"]
ActiveHigh = 1,
}
impl From<Bkp> for bool {
#[inline(always)]
fn from(variant: Bkp) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `BKP` reader - Break polarity"]
pub type BkpR = crate::BitReader<Bkp>;
impl BkpR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Bkp {
match self.bits {
false => Bkp::ActiveLow,
true => Bkp::ActiveHigh,
}
}
#[doc = "Active Low"]
#[inline(always)]
pub fn is_active_low(&self) -> bool {
*self == Bkp::ActiveLow
}
#[doc = "Active High"]
#[inline(always)]
pub fn is_active_high(&self) -> bool {
*self == Bkp::ActiveHigh
}
}
#[doc = "Field `BKP` writer - Break polarity"]
pub type BkpW<'a, REG> = crate::BitWriter<'a, REG, Bkp>;
impl<'a, REG> BkpW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Active Low"]
#[inline(always)]
pub fn active_low(self) -> &'a mut crate::W<REG> {
self.variant(Bkp::ActiveLow)
}
#[doc = "Active High"]
#[inline(always)]
pub fn active_high(self) -> &'a mut crate::W<REG> {
self.variant(Bkp::ActiveHigh)
}
}
#[doc = "Field `AOE` reader - Automatic output enable"]
pub type AoeR = crate::BitReader;
#[doc = "Field `AOE` writer - Automatic output enable"]
pub type AoeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MOE` reader - Main output enable"]
pub type MoeR = crate::BitReader;
#[doc = "Field `MOE` writer - Main output enable"]
pub type MoeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Break filter\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Bkf {
#[doc = "0: FDIV1"]
Fdiv1 = 0,
#[doc = "1: FDIV1_N2"]
Fdiv1N2 = 1,
#[doc = "2: FDIV1_N4"]
Fdiv1N4 = 2,
#[doc = "3: FDIV1_N8"]
Fdiv1N8 = 3,
#[doc = "4: FDIV2_N6"]
Fdiv2N6 = 4,
#[doc = "5: FDIV2_N8"]
Fdiv2N8 = 5,
#[doc = "6: FDIV4_N6"]
Fdiv4N6 = 6,
#[doc = "7: FDIV4_N8"]
Fdiv4N8 = 7,
#[doc = "8: FDIV8_N6"]
Fdiv8N6 = 8,
#[doc = "9: FDIV8_N8"]
Fdiv8N8 = 9,
#[doc = "10: FDIV16_N5"]
Fdiv16N5 = 10,
#[doc = "11: FDIV16_N6"]
Fdiv16N6 = 11,
#[doc = "12: FDIV16_N8"]
Fdiv16N8 = 12,
#[doc = "13: FDIV32_N5"]
Fdiv32N5 = 13,
#[doc = "14: FDIV32_N6"]
Fdiv32N6 = 14,
#[doc = "15: FDIV32_N8"]
Fdiv32N8 = 15,
}
impl From<Bkf> for u8 {
#[inline(always)]
fn from(variant: Bkf) -> Self {
variant as _
}
}
impl crate::FieldSpec for Bkf {
type Ux = u8;
}
impl crate::IsEnum for Bkf {}
#[doc = "Field `BKF` reader - Break filter"]
pub type BkfR = crate::FieldReader<Bkf>;
impl BkfR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Bkf {
match self.bits {
0 => Bkf::Fdiv1,
1 => Bkf::Fdiv1N2,
2 => Bkf::Fdiv1N4,
3 => Bkf::Fdiv1N8,
4 => Bkf::Fdiv2N6,
5 => Bkf::Fdiv2N8,
6 => Bkf::Fdiv4N6,
7 => Bkf::Fdiv4N8,
8 => Bkf::Fdiv8N6,
9 => Bkf::Fdiv8N8,
10 => Bkf::Fdiv16N5,
11 => Bkf::Fdiv16N6,
12 => Bkf::Fdiv16N8,
13 => Bkf::Fdiv32N5,
14 => Bkf::Fdiv32N6,
15 => Bkf::Fdiv32N8,
_ => unreachable!(),
}
}
#[doc = "FDIV1"]
#[inline(always)]
pub fn is_fdiv1(&self) -> bool {
*self == Bkf::Fdiv1
}
#[doc = "FDIV1_N2"]
#[inline(always)]
pub fn is_fdiv1_n2(&self) -> bool {
*self == Bkf::Fdiv1N2
}
#[doc = "FDIV1_N4"]
#[inline(always)]
pub fn is_fdiv1_n4(&self) -> bool {
*self == Bkf::Fdiv1N4
}
#[doc = "FDIV1_N8"]
#[inline(always)]
pub fn is_fdiv1_n8(&self) -> bool {
*self == Bkf::Fdiv1N8
}
#[doc = "FDIV2_N6"]
#[inline(always)]
pub fn is_fdiv2_n6(&self) -> bool {
*self == Bkf::Fdiv2N6
}
#[doc = "FDIV2_N8"]
#[inline(always)]
pub fn is_fdiv2_n8(&self) -> bool {
*self == Bkf::Fdiv2N8
}
#[doc = "FDIV4_N6"]
#[inline(always)]
pub fn is_fdiv4_n6(&self) -> bool {
*self == Bkf::Fdiv4N6
}
#[doc = "FDIV4_N8"]
#[inline(always)]
pub fn is_fdiv4_n8(&self) -> bool {
*self == Bkf::Fdiv4N8
}
#[doc = "FDIV8_N6"]
#[inline(always)]
pub fn is_fdiv8_n6(&self) -> bool {
*self == Bkf::Fdiv8N6
}
#[doc = "FDIV8_N8"]
#[inline(always)]
pub fn is_fdiv8_n8(&self) -> bool {
*self == Bkf::Fdiv8N8
}
#[doc = "FDIV16_N5"]
#[inline(always)]
pub fn is_fdiv16_n5(&self) -> bool {
*self == Bkf::Fdiv16N5
}
#[doc = "FDIV16_N6"]
#[inline(always)]
pub fn is_fdiv16_n6(&self) -> bool {
*self == Bkf::Fdiv16N6
}
#[doc = "FDIV16_N8"]
#[inline(always)]
pub fn is_fdiv16_n8(&self) -> bool {
*self == Bkf::Fdiv16N8
}
#[doc = "FDIV32_N5"]
#[inline(always)]
pub fn is_fdiv32_n5(&self) -> bool {
*self == Bkf::Fdiv32N5
}
#[doc = "FDIV32_N6"]
#[inline(always)]
pub fn is_fdiv32_n6(&self) -> bool {
*self == Bkf::Fdiv32N6
}
#[doc = "FDIV32_N8"]
#[inline(always)]
pub fn is_fdiv32_n8(&self) -> bool {
*self == Bkf::Fdiv32N8
}
}
#[doc = "Field `BKF` writer - Break filter"]
pub type BkfW<'a, REG> = crate::FieldWriter<'a, REG, 4, Bkf, crate::Safe>;
impl<'a, REG> BkfW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "FDIV1"]
#[inline(always)]
pub fn fdiv1(self) -> &'a mut crate::W<REG> {
self.variant(Bkf::Fdiv1)
}
#[doc = "FDIV1_N2"]
#[inline(always)]
pub fn fdiv1_n2(self) -> &'a mut crate::W<REG> {
self.variant(Bkf::Fdiv1N2)
}
#[doc = "FDIV1_N4"]
#[inline(always)]
pub fn fdiv1_n4(self) -> &'a mut crate::W<REG> {
self.variant(Bkf::Fdiv1N4)
}
#[doc = "FDIV1_N8"]
#[inline(always)]
pub fn fdiv1_n8(self) -> &'a mut crate::W<REG> {
self.variant(Bkf::Fdiv1N8)
}
#[doc = "FDIV2_N6"]
#[inline(always)]
pub fn fdiv2_n6(self) -> &'a mut crate::W<REG> {
self.variant(Bkf::Fdiv2N6)
}
#[doc = "FDIV2_N8"]
#[inline(always)]
pub fn fdiv2_n8(self) -> &'a mut crate::W<REG> {
self.variant(Bkf::Fdiv2N8)
}
#[doc = "FDIV4_N6"]
#[inline(always)]
pub fn fdiv4_n6(self) -> &'a mut crate::W<REG> {
self.variant(Bkf::Fdiv4N6)
}
#[doc = "FDIV4_N8"]
#[inline(always)]
pub fn fdiv4_n8(self) -> &'a mut crate::W<REG> {
self.variant(Bkf::Fdiv4N8)
}
#[doc = "FDIV8_N6"]
#[inline(always)]
pub fn fdiv8_n6(self) -> &'a mut crate::W<REG> {
self.variant(Bkf::Fdiv8N6)
}
#[doc = "FDIV8_N8"]
#[inline(always)]
pub fn fdiv8_n8(self) -> &'a mut crate::W<REG> {
self.variant(Bkf::Fdiv8N8)
}
#[doc = "FDIV16_N5"]
#[inline(always)]
pub fn fdiv16_n5(self) -> &'a mut crate::W<REG> {
self.variant(Bkf::Fdiv16N5)
}
#[doc = "FDIV16_N6"]
#[inline(always)]
pub fn fdiv16_n6(self) -> &'a mut crate::W<REG> {
self.variant(Bkf::Fdiv16N6)
}
#[doc = "FDIV16_N8"]
#[inline(always)]
pub fn fdiv16_n8(self) -> &'a mut crate::W<REG> {
self.variant(Bkf::Fdiv16N8)
}
#[doc = "FDIV32_N5"]
#[inline(always)]
pub fn fdiv32_n5(self) -> &'a mut crate::W<REG> {
self.variant(Bkf::Fdiv32N5)
}
#[doc = "FDIV32_N6"]
#[inline(always)]
pub fn fdiv32_n6(self) -> &'a mut crate::W<REG> {
self.variant(Bkf::Fdiv32N6)
}
#[doc = "FDIV32_N8"]
#[inline(always)]
pub fn fdiv32_n8(self) -> &'a mut crate::W<REG> {
self.variant(Bkf::Fdiv32N8)
}
}
impl R {
#[doc = "Bits 0:7 - Dead-Time generator setup"]
#[inline(always)]
pub fn dtg(&self) -> DtgR {
DtgR::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:9 - Lock configuration"]
#[inline(always)]
pub fn lock(&self) -> LockR {
LockR::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bit 10 - Off-State selection for idle mode"]
#[inline(always)]
pub fn ossi(&self) -> OssiR {
OssiR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - Off-State selection for run mode"]
#[inline(always)]
pub fn ossr(&self) -> OssrR {
OssrR::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12 - Break enable"]
#[inline(always)]
pub fn bke(&self) -> BkeR {
BkeR::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13 - Break polarity"]
#[inline(always)]
pub fn bkp(&self) -> BkpR {
BkpR::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - Automatic output enable"]
#[inline(always)]
pub fn aoe(&self) -> AoeR {
AoeR::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15 - Main output enable"]
#[inline(always)]
pub fn moe(&self) -> MoeR {
MoeR::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bits 16:19 - Break filter"]
#[inline(always)]
pub fn bkf(&self) -> BkfR {
BkfR::new(((self.bits >> 16) & 0x0f) as u8)
}
}
impl W {
#[doc = "Bits 0:7 - Dead-Time generator setup"]
#[inline(always)]
pub fn dtg(&mut self) -> DtgW<BdtrSpec> {
DtgW::new(self, 0)
}
#[doc = "Bits 8:9 - Lock configuration"]
#[inline(always)]
pub fn lock(&mut self) -> LockW<BdtrSpec> {
LockW::new(self, 8)
}
#[doc = "Bit 10 - Off-State selection for idle mode"]
#[inline(always)]
pub fn ossi(&mut self) -> OssiW<BdtrSpec> {
OssiW::new(self, 10)
}
#[doc = "Bit 11 - Off-State selection for run mode"]
#[inline(always)]
pub fn ossr(&mut self) -> OssrW<BdtrSpec> {
OssrW::new(self, 11)
}
#[doc = "Bit 12 - Break enable"]
#[inline(always)]
pub fn bke(&mut self) -> BkeW<BdtrSpec> {
BkeW::new(self, 12)
}
#[doc = "Bit 13 - Break polarity"]
#[inline(always)]
pub fn bkp(&mut self) -> BkpW<BdtrSpec> {
BkpW::new(self, 13)
}
#[doc = "Bit 14 - Automatic output enable"]
#[inline(always)]
pub fn aoe(&mut self) -> AoeW<BdtrSpec> {
AoeW::new(self, 14)
}
#[doc = "Bit 15 - Main output enable"]
#[inline(always)]
pub fn moe(&mut self) -> MoeW<BdtrSpec> {
MoeW::new(self, 15)
}
#[doc = "Bits 16:19 - Break filter"]
#[inline(always)]
pub fn bkf(&mut self) -> BkfW<BdtrSpec> {
BkfW::new(self, 16)
}
}
#[doc = "Break and dead time register\n\nYou can [`read`](crate::Reg::read) this register and get [`bdtr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bdtr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct BdtrSpec;
impl crate::RegisterSpec for BdtrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`bdtr::R`](R) reader structure"]
impl crate::Readable for BdtrSpec {}
#[doc = "`write(|w| ..)` method takes [`bdtr::W`](W) writer structure"]
impl crate::Writable for BdtrSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets BDTR to value 0"]
impl crate::Resettable for BdtrSpec {}
}
}
#[doc = "GPTIMER registers"]
pub type Gptimer1 = crate::Periph<gptimer0::RegisterBlock, 0x4002_1000>;
impl core::fmt::Debug for Gptimer1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Gptimer1").finish()
}
}
#[doc = "GPTIMER registers"]
pub use self::gptimer0 as gptimer1;
#[doc = "GPTIMER registers"]
pub type Gptimer2 = crate::Periph<gptimer0::RegisterBlock, 0x4002_2000>;
impl core::fmt::Debug for Gptimer2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Gptimer2").finish()
}
}
#[doc = "GPTIMER registers"]
pub use self::gptimer0 as gptimer2;
#[doc = "GPTIMER registers"]
pub type Gptimer3 = crate::Periph<gptimer0::RegisterBlock, 0x4002_3000>;
impl core::fmt::Debug for Gptimer3 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Gptimer3").finish()
}
}
#[doc = "GPTIMER registers"]
pub use self::gptimer0 as gptimer3;
#[doc = "GPTIMER registers"]
pub type Gptimer4 = crate::Periph<gptimer0::RegisterBlock, 0x4002_4000>;
impl core::fmt::Debug for Gptimer4 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Gptimer4").finish()
}
}
#[doc = "GPTIMER registers"]
pub use self::gptimer0 as gptimer4;
#[doc = "UART registers"]
pub type Uart0 = crate::Periph<uart0::RegisterBlock, 0x4002_5000>;
impl core::fmt::Debug for Uart0 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Uart0").finish()
}
}
#[doc = "UART registers"]
pub mod uart0 {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
dr: Dr,
rsr_ecr: RsrEcr,
_reserved2: [u8; 0x10],
fr: Fr,
_reserved3: [u8; 0x08],
ibrd: Ibrd,
fbrd: Fbrd,
lcr_h: LcrH,
cr: Cr,
ifls: Ifls,
imsc: Imsc,
ris: Ris,
mis: Mis,
icr: Icr,
dmacr: Dmacr,
}
impl RegisterBlock {
#[doc = "0x00 - Data register"]
#[inline(always)]
pub const fn dr(&self) -> &Dr {
&self.dr
}
#[doc = "0x04 - Receive status register/error clear register"]
#[inline(always)]
pub const fn rsr_ecr(&self) -> &RsrEcr {
&self.rsr_ecr
}
#[doc = "0x18 - Flag register"]
#[inline(always)]
pub const fn fr(&self) -> &Fr {
&self.fr
}
#[doc = "0x24 - Integer baud rate register"]
#[inline(always)]
pub const fn ibrd(&self) -> &Ibrd {
&self.ibrd
}
#[doc = "0x28 - Fractional baud rate register"]
#[inline(always)]
pub const fn fbrd(&self) -> &Fbrd {
&self.fbrd
}
#[doc = "0x2c - Line control register"]
#[inline(always)]
pub const fn lcr_h(&self) -> &LcrH {
&self.lcr_h
}
#[doc = "0x30 - Control register"]
#[inline(always)]
pub const fn cr(&self) -> &Cr {
&self.cr
}
#[doc = "0x34 - Interrupt FIFO level select register"]
#[inline(always)]
pub const fn ifls(&self) -> &Ifls {
&self.ifls
}
#[doc = "0x38 - Interrupt mask set/clear register"]
#[inline(always)]
pub const fn imsc(&self) -> &Imsc {
&self.imsc
}
#[doc = "0x3c - Raw interrupt status register"]
#[inline(always)]
pub const fn ris(&self) -> &Ris {
&self.ris
}
#[doc = "0x40 - Masked interrupt status register"]
#[inline(always)]
pub const fn mis(&self) -> &Mis {
&self.mis
}
#[doc = "0x44 - Interrupt clear register"]
#[inline(always)]
pub const fn icr(&self) -> &Icr {
&self.icr
}
#[doc = "0x48 - DMA control register"]
#[inline(always)]
pub const fn dmacr(&self) -> &Dmacr {
&self.dmacr
}
}
#[doc = "DR (rw) register accessor: Data register\n\nYou can [`read`](crate::Reg::read) this register and get [`dr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dr`] module"]
#[doc(alias = "DR")]
pub type Dr = crate::Reg<dr::DrSpec>;
#[doc = "Data register"]
pub mod dr {
#[doc = "Register `DR` reader"]
pub type R = crate::R<DrSpec>;
#[doc = "Register `DR` writer"]
pub type W = crate::W<DrSpec>;
#[doc = "Field `DR` reader - Data register"]
pub type DrR = crate::FieldReader;
#[doc = "Field `DR` writer - Data register"]
pub type DrW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `FE` reader - Framing error"]
pub type FeR = crate::BitReader;
#[doc = "Field `FE` writer - Framing error"]
pub type FeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PE` reader - Parity error"]
pub type PeR = crate::BitReader;
#[doc = "Field `PE` writer - Parity error"]
pub type PeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `BE` reader - Break error"]
pub type BeR = crate::BitReader;
#[doc = "Field `BE` writer - Break error"]
pub type BeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OE` reader - Overrun error"]
pub type OeR = crate::BitReader;
#[doc = "Field `OE` writer - Overrun error"]
pub type OeW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:7 - Data register"]
#[inline(always)]
pub fn dr(&self) -> DrR {
DrR::new((self.bits & 0xff) as u8)
}
#[doc = "Bit 8 - Framing error"]
#[inline(always)]
pub fn fe(&self) -> FeR {
FeR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - Parity error"]
#[inline(always)]
pub fn pe(&self) -> PeR {
PeR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - Break error"]
#[inline(always)]
pub fn be(&self) -> BeR {
BeR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - Overrun error"]
#[inline(always)]
pub fn oe(&self) -> OeR {
OeR::new(((self.bits >> 11) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:7 - Data register"]
#[inline(always)]
pub fn dr(&mut self) -> DrW<DrSpec> {
DrW::new(self, 0)
}
#[doc = "Bit 8 - Framing error"]
#[inline(always)]
pub fn fe(&mut self) -> FeW<DrSpec> {
FeW::new(self, 8)
}
#[doc = "Bit 9 - Parity error"]
#[inline(always)]
pub fn pe(&mut self) -> PeW<DrSpec> {
PeW::new(self, 9)
}
#[doc = "Bit 10 - Break error"]
#[inline(always)]
pub fn be(&mut self) -> BeW<DrSpec> {
BeW::new(self, 10)
}
#[doc = "Bit 11 - Overrun error"]
#[inline(always)]
pub fn oe(&mut self) -> OeW<DrSpec> {
OeW::new(self, 11)
}
}
#[doc = "Data register\n\nYou can [`read`](crate::Reg::read) this register and get [`dr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DrSpec;
impl crate::RegisterSpec for DrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`dr::R`](R) reader structure"]
impl crate::Readable for DrSpec {}
#[doc = "`write(|w| ..)` method takes [`dr::W`](W) writer structure"]
impl crate::Writable for DrSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets DR to value 0"]
impl crate::Resettable for DrSpec {}
}
#[doc = "RSR_ECR (rw) register accessor: Receive status register/error clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`rsr_ecr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rsr_ecr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsr_ecr`] module"]
#[doc(alias = "RSR_ECR")]
pub type RsrEcr = crate::Reg<rsr_ecr::RsrEcrSpec>;
#[doc = "Receive status register/error clear register"]
pub mod rsr_ecr {
#[doc = "Register `RSR_ECR` reader"]
pub type R = crate::R<RsrEcrSpec>;
#[doc = "Register `RSR_ECR` writer"]
pub type W = crate::W<RsrEcrSpec>;
#[doc = "Field `FE` reader - Framing error"]
pub type FeR = crate::BitReader;
#[doc = "Field `FE` writer - Framing error"]
pub type FeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PE` reader - Parity error"]
pub type PeR = crate::BitReader;
#[doc = "Field `PE` writer - Parity error"]
pub type PeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `BE` reader - Break error"]
pub type BeR = crate::BitReader;
#[doc = "Field `BE` writer - Break error"]
pub type BeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OE` reader - Overrun error"]
pub type OeR = crate::BitReader;
#[doc = "Field `OE` writer - Overrun error"]
pub type OeW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - Framing error"]
#[inline(always)]
pub fn fe(&self) -> FeR {
FeR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Parity error"]
#[inline(always)]
pub fn pe(&self) -> PeR {
PeR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Break error"]
#[inline(always)]
pub fn be(&self) -> BeR {
BeR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Overrun error"]
#[inline(always)]
pub fn oe(&self) -> OeR {
OeR::new(((self.bits >> 3) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Framing error"]
#[inline(always)]
pub fn fe(&mut self) -> FeW<RsrEcrSpec> {
FeW::new(self, 0)
}
#[doc = "Bit 1 - Parity error"]
#[inline(always)]
pub fn pe(&mut self) -> PeW<RsrEcrSpec> {
PeW::new(self, 1)
}
#[doc = "Bit 2 - Break error"]
#[inline(always)]
pub fn be(&mut self) -> BeW<RsrEcrSpec> {
BeW::new(self, 2)
}
#[doc = "Bit 3 - Overrun error"]
#[inline(always)]
pub fn oe(&mut self) -> OeW<RsrEcrSpec> {
OeW::new(self, 3)
}
}
#[doc = "Receive status register/error clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`rsr_ecr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rsr_ecr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RsrEcrSpec;
impl crate::RegisterSpec for RsrEcrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rsr_ecr::R`](R) reader structure"]
impl crate::Readable for RsrEcrSpec {}
#[doc = "`write(|w| ..)` method takes [`rsr_ecr::W`](W) writer structure"]
impl crate::Writable for RsrEcrSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets RSR_ECR to value 0"]
impl crate::Resettable for RsrEcrSpec {}
}
#[doc = "FR (r) register accessor: Flag register\n\nYou can [`read`](crate::Reg::read) this register and get [`fr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fr`] module"]
#[doc(alias = "FR")]
pub type Fr = crate::Reg<fr::FrSpec>;
#[doc = "Flag register"]
pub mod fr {
#[doc = "Register `FR` reader"]
pub type R = crate::R<FrSpec>;
#[doc = "Field `CTS` reader - Clear to send"]
pub type CtsR = crate::BitReader;
#[doc = "Field `BUSY` reader - UART busy transmitting data"]
pub type BusyR = crate::BitReader;
#[doc = "Field `RXFE` reader - Receive FIFO empty"]
pub type RxfeR = crate::BitReader;
#[doc = "Field `TXFF` reader - Transmit FIFO full"]
pub type TxffR = crate::BitReader;
#[doc = "Field `RXFF` reader - Receive FIFO full"]
pub type RxffR = crate::BitReader;
#[doc = "Field `TXFE` reader - Transmit FIFO empty"]
pub type TxfeR = crate::BitReader;
impl R {
#[doc = "Bit 0 - Clear to send"]
#[inline(always)]
pub fn cts(&self) -> CtsR {
CtsR::new((self.bits & 1) != 0)
}
#[doc = "Bit 3 - UART busy transmitting data"]
#[inline(always)]
pub fn busy(&self) -> BusyR {
BusyR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Receive FIFO empty"]
#[inline(always)]
pub fn rxfe(&self) -> RxfeR {
RxfeR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Transmit FIFO full"]
#[inline(always)]
pub fn txff(&self) -> TxffR {
TxffR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Receive FIFO full"]
#[inline(always)]
pub fn rxff(&self) -> RxffR {
RxffR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Transmit FIFO empty"]
#[inline(always)]
pub fn txfe(&self) -> TxfeR {
TxfeR::new(((self.bits >> 7) & 1) != 0)
}
}
#[doc = "Flag register\n\nYou can [`read`](crate::Reg::read) this register and get [`fr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FrSpec;
impl crate::RegisterSpec for FrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`fr::R`](R) reader structure"]
impl crate::Readable for FrSpec {}
#[doc = "`reset()` method sets FR to value 0"]
impl crate::Resettable for FrSpec {}
}
#[doc = "IBRD (rw) register accessor: Integer baud rate register\n\nYou can [`read`](crate::Reg::read) this register and get [`ibrd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ibrd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ibrd`] module"]
#[doc(alias = "IBRD")]
pub type Ibrd = crate::Reg<ibrd::IbrdSpec>;
#[doc = "Integer baud rate register"]
pub mod ibrd {
#[doc = "Register `IBRD` reader"]
pub type R = crate::R<IbrdSpec>;
#[doc = "Register `IBRD` writer"]
pub type W = crate::W<IbrdSpec>;
#[doc = "Field `IBRD` reader - Integer baud rate register"]
pub type IbrdR = crate::FieldReader<u16>;
#[doc = "Field `IBRD` writer - Integer baud rate register"]
pub type IbrdW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - Integer baud rate register"]
#[inline(always)]
pub fn ibrd(&self) -> IbrdR {
IbrdR::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15 - Integer baud rate register"]
#[inline(always)]
pub fn ibrd(&mut self) -> IbrdW<IbrdSpec> {
IbrdW::new(self, 0)
}
}
#[doc = "Integer baud rate register\n\nYou can [`read`](crate::Reg::read) this register and get [`ibrd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ibrd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IbrdSpec;
impl crate::RegisterSpec for IbrdSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ibrd::R`](R) reader structure"]
impl crate::Readable for IbrdSpec {}
#[doc = "`write(|w| ..)` method takes [`ibrd::W`](W) writer structure"]
impl crate::Writable for IbrdSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets IBRD to value 0"]
impl crate::Resettable for IbrdSpec {}
}
#[doc = "FBRD (rw) register accessor: Fractional baud rate register\n\nYou can [`read`](crate::Reg::read) this register and get [`fbrd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fbrd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fbrd`] module"]
#[doc(alias = "FBRD")]
pub type Fbrd = crate::Reg<fbrd::FbrdSpec>;
#[doc = "Fractional baud rate register"]
pub mod fbrd {
#[doc = "Register `FBRD` reader"]
pub type R = crate::R<FbrdSpec>;
#[doc = "Register `FBRD` writer"]
pub type W = crate::W<FbrdSpec>;
#[doc = "Field `FBRD` reader - Fractional baud rate register"]
pub type FbrdR = crate::FieldReader;
#[doc = "Field `FBRD` writer - Fractional baud rate register"]
pub type FbrdW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
impl R {
#[doc = "Bits 0:5 - Fractional baud rate register"]
#[inline(always)]
pub fn fbrd(&self) -> FbrdR {
FbrdR::new((self.bits & 0x3f) as u8)
}
}
impl W {
#[doc = "Bits 0:5 - Fractional baud rate register"]
#[inline(always)]
pub fn fbrd(&mut self) -> FbrdW<FbrdSpec> {
FbrdW::new(self, 0)
}
}
#[doc = "Fractional baud rate register\n\nYou can [`read`](crate::Reg::read) this register and get [`fbrd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fbrd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FbrdSpec;
impl crate::RegisterSpec for FbrdSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`fbrd::R`](R) reader structure"]
impl crate::Readable for FbrdSpec {}
#[doc = "`write(|w| ..)` method takes [`fbrd::W`](W) writer structure"]
impl crate::Writable for FbrdSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets FBRD to value 0"]
impl crate::Resettable for FbrdSpec {}
}
#[doc = "LCR_H (rw) register accessor: Line control register\n\nYou can [`read`](crate::Reg::read) this register and get [`lcr_h::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lcr_h::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lcr_h`] module"]
#[doc(alias = "LCR_H")]
pub type LcrH = crate::Reg<lcr_h::LcrHSpec>;
#[doc = "Line control register"]
pub mod lcr_h {
#[doc = "Register `LCR_H` reader"]
pub type R = crate::R<LcrHSpec>;
#[doc = "Register `LCR_H` writer"]
pub type W = crate::W<LcrHSpec>;
#[doc = "Field `BRK` reader - Send break"]
pub type BrkR = crate::BitReader;
#[doc = "Field `BRK` writer - Send break"]
pub type BrkW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PEN` reader - Parity enable"]
pub type PenR = crate::BitReader;
#[doc = "Field `PEN` writer - Parity enable"]
pub type PenW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Even parity select\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Eps {
#[doc = "0: Odd parity"]
Oddparity = 0,
#[doc = "1: Even parity"]
Evenparity = 1,
}
impl From<Eps> for bool {
#[inline(always)]
fn from(variant: Eps) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `EPS` reader - Even parity select"]
pub type EpsR = crate::BitReader<Eps>;
impl EpsR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Eps {
match self.bits {
false => Eps::Oddparity,
true => Eps::Evenparity,
}
}
#[doc = "Odd parity"]
#[inline(always)]
pub fn is_oddparity(&self) -> bool {
*self == Eps::Oddparity
}
#[doc = "Even parity"]
#[inline(always)]
pub fn is_evenparity(&self) -> bool {
*self == Eps::Evenparity
}
}
#[doc = "Field `EPS` writer - Even parity select"]
pub type EpsW<'a, REG> = crate::BitWriter<'a, REG, Eps>;
impl<'a, REG> EpsW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Odd parity"]
#[inline(always)]
pub fn oddparity(self) -> &'a mut crate::W<REG> {
self.variant(Eps::Oddparity)
}
#[doc = "Even parity"]
#[inline(always)]
pub fn evenparity(self) -> &'a mut crate::W<REG> {
self.variant(Eps::Evenparity)
}
}
#[doc = "Two stop bits select\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Stp2 {
#[doc = "0: 1 stop bit"]
_1stopbit = 0,
#[doc = "1: 2 stop bits"]
_2stopbits = 1,
}
impl From<Stp2> for bool {
#[inline(always)]
fn from(variant: Stp2) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `STP2` reader - Two stop bits select"]
pub type Stp2R = crate::BitReader<Stp2>;
impl Stp2R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Stp2 {
match self.bits {
false => Stp2::_1stopbit,
true => Stp2::_2stopbits,
}
}
#[doc = "1 stop bit"]
#[inline(always)]
pub fn is_1stopbit(&self) -> bool {
*self == Stp2::_1stopbit
}
#[doc = "2 stop bits"]
#[inline(always)]
pub fn is_2stopbits(&self) -> bool {
*self == Stp2::_2stopbits
}
}
#[doc = "Field `STP2` writer - Two stop bits select"]
pub type Stp2W<'a, REG> = crate::BitWriter<'a, REG, Stp2>;
impl<'a, REG> Stp2W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "1 stop bit"]
#[inline(always)]
pub fn _1stopbit(self) -> &'a mut crate::W<REG> {
self.variant(Stp2::_1stopbit)
}
#[doc = "2 stop bits"]
#[inline(always)]
pub fn _2stopbits(self) -> &'a mut crate::W<REG> {
self.variant(Stp2::_2stopbits)
}
}
#[doc = "Field `FEN` reader - Enable FIFOs"]
pub type FenR = crate::BitReader;
#[doc = "Field `FEN` writer - Enable FIFOs"]
pub type FenW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Word length, data bits in a frame\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Wlen {
#[doc = "0: 5 bits"]
_5bits = 0,
#[doc = "1: 6 bits"]
_6bits = 1,
#[doc = "2: 7 bits"]
_7bits = 2,
#[doc = "3: 8 bits"]
_8bits = 3,
}
impl From<Wlen> for u8 {
#[inline(always)]
fn from(variant: Wlen) -> Self {
variant as _
}
}
impl crate::FieldSpec for Wlen {
type Ux = u8;
}
impl crate::IsEnum for Wlen {}
#[doc = "Field `WLEN` reader - Word length, data bits in a frame"]
pub type WlenR = crate::FieldReader<Wlen>;
impl WlenR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Wlen {
match self.bits {
0 => Wlen::_5bits,
1 => Wlen::_6bits,
2 => Wlen::_7bits,
3 => Wlen::_8bits,
_ => unreachable!(),
}
}
#[doc = "5 bits"]
#[inline(always)]
pub fn is_5bits(&self) -> bool {
*self == Wlen::_5bits
}
#[doc = "6 bits"]
#[inline(always)]
pub fn is_6bits(&self) -> bool {
*self == Wlen::_6bits
}
#[doc = "7 bits"]
#[inline(always)]
pub fn is_7bits(&self) -> bool {
*self == Wlen::_7bits
}
#[doc = "8 bits"]
#[inline(always)]
pub fn is_8bits(&self) -> bool {
*self == Wlen::_8bits
}
}
#[doc = "Field `WLEN` writer - Word length, data bits in a frame"]
pub type WlenW<'a, REG> = crate::FieldWriter<'a, REG, 2, Wlen, crate::Safe>;
impl<'a, REG> WlenW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "5 bits"]
#[inline(always)]
pub fn _5bits(self) -> &'a mut crate::W<REG> {
self.variant(Wlen::_5bits)
}
#[doc = "6 bits"]
#[inline(always)]
pub fn _6bits(self) -> &'a mut crate::W<REG> {
self.variant(Wlen::_6bits)
}
#[doc = "7 bits"]
#[inline(always)]
pub fn _7bits(self) -> &'a mut crate::W<REG> {
self.variant(Wlen::_7bits)
}
#[doc = "8 bits"]
#[inline(always)]
pub fn _8bits(self) -> &'a mut crate::W<REG> {
self.variant(Wlen::_8bits)
}
}
#[doc = "Field `SPS` reader - Stick parity select"]
pub type SpsR = crate::BitReader;
#[doc = "Field `SPS` writer - Stick parity select"]
pub type SpsW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - Send break"]
#[inline(always)]
pub fn brk(&self) -> BrkR {
BrkR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Parity enable"]
#[inline(always)]
pub fn pen(&self) -> PenR {
PenR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Even parity select"]
#[inline(always)]
pub fn eps(&self) -> EpsR {
EpsR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Two stop bits select"]
#[inline(always)]
pub fn stp2(&self) -> Stp2R {
Stp2R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Enable FIFOs"]
#[inline(always)]
pub fn fen(&self) -> FenR {
FenR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bits 5:6 - Word length, data bits in a frame"]
#[inline(always)]
pub fn wlen(&self) -> WlenR {
WlenR::new(((self.bits >> 5) & 3) as u8)
}
#[doc = "Bit 7 - Stick parity select"]
#[inline(always)]
pub fn sps(&self) -> SpsR {
SpsR::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Send break"]
#[inline(always)]
pub fn brk(&mut self) -> BrkW<LcrHSpec> {
BrkW::new(self, 0)
}
#[doc = "Bit 1 - Parity enable"]
#[inline(always)]
pub fn pen(&mut self) -> PenW<LcrHSpec> {
PenW::new(self, 1)
}
#[doc = "Bit 2 - Even parity select"]
#[inline(always)]
pub fn eps(&mut self) -> EpsW<LcrHSpec> {
EpsW::new(self, 2)
}
#[doc = "Bit 3 - Two stop bits select"]
#[inline(always)]
pub fn stp2(&mut self) -> Stp2W<LcrHSpec> {
Stp2W::new(self, 3)
}
#[doc = "Bit 4 - Enable FIFOs"]
#[inline(always)]
pub fn fen(&mut self) -> FenW<LcrHSpec> {
FenW::new(self, 4)
}
#[doc = "Bits 5:6 - Word length, data bits in a frame"]
#[inline(always)]
pub fn wlen(&mut self) -> WlenW<LcrHSpec> {
WlenW::new(self, 5)
}
#[doc = "Bit 7 - Stick parity select"]
#[inline(always)]
pub fn sps(&mut self) -> SpsW<LcrHSpec> {
SpsW::new(self, 7)
}
}
#[doc = "Line control register\n\nYou can [`read`](crate::Reg::read) this register and get [`lcr_h::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lcr_h::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct LcrHSpec;
impl crate::RegisterSpec for LcrHSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`lcr_h::R`](R) reader structure"]
impl crate::Readable for LcrHSpec {}
#[doc = "`write(|w| ..)` method takes [`lcr_h::W`](W) writer structure"]
impl crate::Writable for LcrHSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets LCR_H to value 0"]
impl crate::Resettable for LcrHSpec {}
}
#[doc = "CR (rw) register accessor: Control register\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr`] module"]
#[doc(alias = "CR")]
pub type Cr = crate::Reg<cr::CrSpec>;
#[doc = "Control register"]
pub mod cr {
#[doc = "Register `CR` reader"]
pub type R = crate::R<CrSpec>;
#[doc = "Register `CR` writer"]
pub type W = crate::W<CrSpec>;
#[doc = "Field `UART_EN` reader - UART enable"]
pub type UartEnR = crate::BitReader;
#[doc = "Field `UART_EN` writer - UART enable"]
pub type UartEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `LBE` reader - Loop back enable"]
pub type LbeR = crate::BitReader;
#[doc = "Field `LBE` writer - Loop back enable"]
pub type LbeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TXE` reader - Transmit enable"]
pub type TxeR = crate::BitReader;
#[doc = "Field `TXE` writer - Transmit enable"]
pub type TxeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RXE` reader - Receive enable"]
pub type RxeR = crate::BitReader;
#[doc = "Field `RXE` writer - Receive enable"]
pub type RxeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RTS` reader - Request to send"]
pub type RtsR = crate::BitReader;
#[doc = "Field `RTS` writer - Request to send"]
pub type RtsW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RTS_EN` reader - RTS hardware flow control enable"]
pub type RtsEnR = crate::BitReader;
#[doc = "Field `RTS_EN` writer - RTS hardware flow control enable"]
pub type RtsEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CTS_EN` reader - CTS hardware flow control enable"]
pub type CtsEnR = crate::BitReader;
#[doc = "Field `CTS_EN` writer - CTS hardware flow control enable"]
pub type CtsEnW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - UART enable"]
#[inline(always)]
pub fn uart_en(&self) -> UartEnR {
UartEnR::new((self.bits & 1) != 0)
}
#[doc = "Bit 7 - Loop back enable"]
#[inline(always)]
pub fn lbe(&self) -> LbeR {
LbeR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - Transmit enable"]
#[inline(always)]
pub fn txe(&self) -> TxeR {
TxeR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - Receive enable"]
#[inline(always)]
pub fn rxe(&self) -> RxeR {
RxeR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 11 - Request to send"]
#[inline(always)]
pub fn rts(&self) -> RtsR {
RtsR::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 14 - RTS hardware flow control enable"]
#[inline(always)]
pub fn rts_en(&self) -> RtsEnR {
RtsEnR::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15 - CTS hardware flow control enable"]
#[inline(always)]
pub fn cts_en(&self) -> CtsEnR {
CtsEnR::new(((self.bits >> 15) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - UART enable"]
#[inline(always)]
pub fn uart_en(&mut self) -> UartEnW<CrSpec> {
UartEnW::new(self, 0)
}
#[doc = "Bit 7 - Loop back enable"]
#[inline(always)]
pub fn lbe(&mut self) -> LbeW<CrSpec> {
LbeW::new(self, 7)
}
#[doc = "Bit 8 - Transmit enable"]
#[inline(always)]
pub fn txe(&mut self) -> TxeW<CrSpec> {
TxeW::new(self, 8)
}
#[doc = "Bit 9 - Receive enable"]
#[inline(always)]
pub fn rxe(&mut self) -> RxeW<CrSpec> {
RxeW::new(self, 9)
}
#[doc = "Bit 11 - Request to send"]
#[inline(always)]
pub fn rts(&mut self) -> RtsW<CrSpec> {
RtsW::new(self, 11)
}
#[doc = "Bit 14 - RTS hardware flow control enable"]
#[inline(always)]
pub fn rts_en(&mut self) -> RtsEnW<CrSpec> {
RtsEnW::new(self, 14)
}
#[doc = "Bit 15 - CTS hardware flow control enable"]
#[inline(always)]
pub fn cts_en(&mut self) -> CtsEnW<CrSpec> {
CtsEnW::new(self, 15)
}
}
#[doc = "Control register\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CrSpec;
impl crate::RegisterSpec for CrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cr::R`](R) reader structure"]
impl crate::Readable for CrSpec {}
#[doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"]
impl crate::Writable for CrSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets CR to value 0"]
impl crate::Resettable for CrSpec {}
}
#[doc = "IFLS (rw) register accessor: Interrupt FIFO level select register\n\nYou can [`read`](crate::Reg::read) this register and get [`ifls::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ifls::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ifls`] module"]
#[doc(alias = "IFLS")]
pub type Ifls = crate::Reg<ifls::IflsSpec>;
#[doc = "Interrupt FIFO level select register"]
pub mod ifls {
#[doc = "Register `IFLS` reader"]
pub type R = crate::R<IflsSpec>;
#[doc = "Register `IFLS` writer"]
pub type W = crate::W<IflsSpec>;
#[doc = "Transmit interrupt FIFO level select\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Txiflsel {
#[doc = "0: `>= 1/8`"]
Ge1_8 = 0,
#[doc = "1: `>= 1/4`"]
Ge1_4 = 1,
#[doc = "2: `>= 1/2`"]
Ge1_2 = 2,
#[doc = "3: `>= 3/4`"]
Ge3_4 = 3,
#[doc = "4: `>= 7/8`"]
Ge7_8 = 4,
}
impl From<Txiflsel> for u8 {
#[inline(always)]
fn from(variant: Txiflsel) -> Self {
variant as _
}
}
impl crate::FieldSpec for Txiflsel {
type Ux = u8;
}
impl crate::IsEnum for Txiflsel {}
#[doc = "Field `TXIFLSEL` reader - Transmit interrupt FIFO level select"]
pub type TxiflselR = crate::FieldReader<Txiflsel>;
impl TxiflselR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<Txiflsel> {
match self.bits {
0 => Some(Txiflsel::Ge1_8),
1 => Some(Txiflsel::Ge1_4),
2 => Some(Txiflsel::Ge1_2),
3 => Some(Txiflsel::Ge3_4),
4 => Some(Txiflsel::Ge7_8),
_ => None,
}
}
#[doc = "`>= 1/8`"]
#[inline(always)]
pub fn is_ge_1_8(&self) -> bool {
*self == Txiflsel::Ge1_8
}
#[doc = "`>= 1/4`"]
#[inline(always)]
pub fn is_ge_1_4(&self) -> bool {
*self == Txiflsel::Ge1_4
}
#[doc = "`>= 1/2`"]
#[inline(always)]
pub fn is_ge_1_2(&self) -> bool {
*self == Txiflsel::Ge1_2
}
#[doc = "`>= 3/4`"]
#[inline(always)]
pub fn is_ge_3_4(&self) -> bool {
*self == Txiflsel::Ge3_4
}
#[doc = "`>= 7/8`"]
#[inline(always)]
pub fn is_ge_7_8(&self) -> bool {
*self == Txiflsel::Ge7_8
}
}
#[doc = "Field `TXIFLSEL` writer - Transmit interrupt FIFO level select"]
pub type TxiflselW<'a, REG> = crate::FieldWriter<'a, REG, 3, Txiflsel>;
impl<'a, REG> TxiflselW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "`>= 1/8`"]
#[inline(always)]
pub fn ge_1_8(self) -> &'a mut crate::W<REG> {
self.variant(Txiflsel::Ge1_8)
}
#[doc = "`>= 1/4`"]
#[inline(always)]
pub fn ge_1_4(self) -> &'a mut crate::W<REG> {
self.variant(Txiflsel::Ge1_4)
}
#[doc = "`>= 1/2`"]
#[inline(always)]
pub fn ge_1_2(self) -> &'a mut crate::W<REG> {
self.variant(Txiflsel::Ge1_2)
}
#[doc = "`>= 3/4`"]
#[inline(always)]
pub fn ge_3_4(self) -> &'a mut crate::W<REG> {
self.variant(Txiflsel::Ge3_4)
}
#[doc = "`>= 7/8`"]
#[inline(always)]
pub fn ge_7_8(self) -> &'a mut crate::W<REG> {
self.variant(Txiflsel::Ge7_8)
}
}
#[doc = "Receive interrupt FIFO level select\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Rxiflsel {
#[doc = "0: `>= 1/8`"]
Ge1_8 = 0,
#[doc = "1: `>= 1/4`"]
Ge1_4 = 1,
#[doc = "2: `>= 1/2`"]
Ge1_2 = 2,
#[doc = "3: `>= 3/4`"]
Ge3_4 = 3,
#[doc = "4: `>= 7/8`"]
Ge7_8 = 4,
}
impl From<Rxiflsel> for u8 {
#[inline(always)]
fn from(variant: Rxiflsel) -> Self {
variant as _
}
}
impl crate::FieldSpec for Rxiflsel {
type Ux = u8;
}
impl crate::IsEnum for Rxiflsel {}
#[doc = "Field `RXIFLSEL` reader - Receive interrupt FIFO level select"]
pub type RxiflselR = crate::FieldReader<Rxiflsel>;
impl RxiflselR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<Rxiflsel> {
match self.bits {
0 => Some(Rxiflsel::Ge1_8),
1 => Some(Rxiflsel::Ge1_4),
2 => Some(Rxiflsel::Ge1_2),
3 => Some(Rxiflsel::Ge3_4),
4 => Some(Rxiflsel::Ge7_8),
_ => None,
}
}
#[doc = "`>= 1/8`"]
#[inline(always)]
pub fn is_ge_1_8(&self) -> bool {
*self == Rxiflsel::Ge1_8
}
#[doc = "`>= 1/4`"]
#[inline(always)]
pub fn is_ge_1_4(&self) -> bool {
*self == Rxiflsel::Ge1_4
}
#[doc = "`>= 1/2`"]
#[inline(always)]
pub fn is_ge_1_2(&self) -> bool {
*self == Rxiflsel::Ge1_2
}
#[doc = "`>= 3/4`"]
#[inline(always)]
pub fn is_ge_3_4(&self) -> bool {
*self == Rxiflsel::Ge3_4
}
#[doc = "`>= 7/8`"]
#[inline(always)]
pub fn is_ge_7_8(&self) -> bool {
*self == Rxiflsel::Ge7_8
}
}
#[doc = "Field `RXIFLSEL` writer - Receive interrupt FIFO level select"]
pub type RxiflselW<'a, REG> = crate::FieldWriter<'a, REG, 3, Rxiflsel>;
impl<'a, REG> RxiflselW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "`>= 1/8`"]
#[inline(always)]
pub fn ge_1_8(self) -> &'a mut crate::W<REG> {
self.variant(Rxiflsel::Ge1_8)
}
#[doc = "`>= 1/4`"]
#[inline(always)]
pub fn ge_1_4(self) -> &'a mut crate::W<REG> {
self.variant(Rxiflsel::Ge1_4)
}
#[doc = "`>= 1/2`"]
#[inline(always)]
pub fn ge_1_2(self) -> &'a mut crate::W<REG> {
self.variant(Rxiflsel::Ge1_2)
}
#[doc = "`>= 3/4`"]
#[inline(always)]
pub fn ge_3_4(self) -> &'a mut crate::W<REG> {
self.variant(Rxiflsel::Ge3_4)
}
#[doc = "`>= 7/8`"]
#[inline(always)]
pub fn ge_7_8(self) -> &'a mut crate::W<REG> {
self.variant(Rxiflsel::Ge7_8)
}
}
impl R {
#[doc = "Bits 0:2 - Transmit interrupt FIFO level select"]
#[inline(always)]
pub fn txiflsel(&self) -> TxiflselR {
TxiflselR::new((self.bits & 7) as u8)
}
#[doc = "Bits 3:5 - Receive interrupt FIFO level select"]
#[inline(always)]
pub fn rxiflsel(&self) -> RxiflselR {
RxiflselR::new(((self.bits >> 3) & 7) as u8)
}
}
impl W {
#[doc = "Bits 0:2 - Transmit interrupt FIFO level select"]
#[inline(always)]
pub fn txiflsel(&mut self) -> TxiflselW<IflsSpec> {
TxiflselW::new(self, 0)
}
#[doc = "Bits 3:5 - Receive interrupt FIFO level select"]
#[inline(always)]
pub fn rxiflsel(&mut self) -> RxiflselW<IflsSpec> {
RxiflselW::new(self, 3)
}
}
#[doc = "Interrupt FIFO level select register\n\nYou can [`read`](crate::Reg::read) this register and get [`ifls::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ifls::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IflsSpec;
impl crate::RegisterSpec for IflsSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ifls::R`](R) reader structure"]
impl crate::Readable for IflsSpec {}
#[doc = "`write(|w| ..)` method takes [`ifls::W`](W) writer structure"]
impl crate::Writable for IflsSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets IFLS to value 0"]
impl crate::Resettable for IflsSpec {}
}
#[doc = "IMSC (rw) register accessor: Interrupt mask set/clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`imsc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`imsc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@imsc`] module"]
#[doc(alias = "IMSC")]
pub type Imsc = crate::Reg<imsc::ImscSpec>;
#[doc = "Interrupt mask set/clear register"]
pub mod imsc {
#[doc = "Register `IMSC` reader"]
pub type R = crate::R<ImscSpec>;
#[doc = "Register `IMSC` writer"]
pub type W = crate::W<ImscSpec>;
#[doc = "Field `CTSM` reader - nUARTCTS modem interrupt mask"]
pub type CtsmR = crate::BitReader;
#[doc = "Field `CTSM` writer - nUARTCTS modem interrupt mask"]
pub type CtsmW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RX` reader - Receive interrupt mask"]
pub type RxR = crate::BitReader;
#[doc = "Field `RX` writer - Receive interrupt mask"]
pub type RxW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TX` reader - Transmit interrupt mask"]
pub type TxR = crate::BitReader;
#[doc = "Field `TX` writer - Transmit interrupt mask"]
pub type TxW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RT` reader - Receive timeout interrupt mask"]
pub type RtR = crate::BitReader;
#[doc = "Field `RT` writer - Receive timeout interrupt mask"]
pub type RtW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `FE` reader - Framing error interrupt mask"]
pub type FeR = crate::BitReader;
#[doc = "Field `FE` writer - Framing error interrupt mask"]
pub type FeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PE` reader - Parity error interrupt mask"]
pub type PeR = crate::BitReader;
#[doc = "Field `PE` writer - Parity error interrupt mask"]
pub type PeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `BE` reader - Break error interrupt mask"]
pub type BeR = crate::BitReader;
#[doc = "Field `BE` writer - Break error interrupt mask"]
pub type BeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OE` reader - Overrun error interrupt mask"]
pub type OeR = crate::BitReader;
#[doc = "Field `OE` writer - Overrun error interrupt mask"]
pub type OeW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 1 - nUARTCTS modem interrupt mask"]
#[inline(always)]
pub fn ctsm(&self) -> CtsmR {
CtsmR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 4 - Receive interrupt mask"]
#[inline(always)]
pub fn rx(&self) -> RxR {
RxR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Transmit interrupt mask"]
#[inline(always)]
pub fn tx(&self) -> TxR {
TxR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Receive timeout interrupt mask"]
#[inline(always)]
pub fn rt(&self) -> RtR {
RtR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Framing error interrupt mask"]
#[inline(always)]
pub fn fe(&self) -> FeR {
FeR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - Parity error interrupt mask"]
#[inline(always)]
pub fn pe(&self) -> PeR {
PeR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - Break error interrupt mask"]
#[inline(always)]
pub fn be(&self) -> BeR {
BeR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - Overrun error interrupt mask"]
#[inline(always)]
pub fn oe(&self) -> OeR {
OeR::new(((self.bits >> 10) & 1) != 0)
}
}
impl W {
#[doc = "Bit 1 - nUARTCTS modem interrupt mask"]
#[inline(always)]
pub fn ctsm(&mut self) -> CtsmW<ImscSpec> {
CtsmW::new(self, 1)
}
#[doc = "Bit 4 - Receive interrupt mask"]
#[inline(always)]
pub fn rx(&mut self) -> RxW<ImscSpec> {
RxW::new(self, 4)
}
#[doc = "Bit 5 - Transmit interrupt mask"]
#[inline(always)]
pub fn tx(&mut self) -> TxW<ImscSpec> {
TxW::new(self, 5)
}
#[doc = "Bit 6 - Receive timeout interrupt mask"]
#[inline(always)]
pub fn rt(&mut self) -> RtW<ImscSpec> {
RtW::new(self, 6)
}
#[doc = "Bit 7 - Framing error interrupt mask"]
#[inline(always)]
pub fn fe(&mut self) -> FeW<ImscSpec> {
FeW::new(self, 7)
}
#[doc = "Bit 8 - Parity error interrupt mask"]
#[inline(always)]
pub fn pe(&mut self) -> PeW<ImscSpec> {
PeW::new(self, 8)
}
#[doc = "Bit 9 - Break error interrupt mask"]
#[inline(always)]
pub fn be(&mut self) -> BeW<ImscSpec> {
BeW::new(self, 9)
}
#[doc = "Bit 10 - Overrun error interrupt mask"]
#[inline(always)]
pub fn oe(&mut self) -> OeW<ImscSpec> {
OeW::new(self, 10)
}
}
#[doc = "Interrupt mask set/clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`imsc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`imsc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ImscSpec;
impl crate::RegisterSpec for ImscSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`imsc::R`](R) reader structure"]
impl crate::Readable for ImscSpec {}
#[doc = "`write(|w| ..)` method takes [`imsc::W`](W) writer structure"]
impl crate::Writable for ImscSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets IMSC to value 0"]
impl crate::Resettable for ImscSpec {}
}
#[doc = "RIS (rw) register accessor: Raw interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`ris::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ris::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ris`] module"]
#[doc(alias = "RIS")]
pub type Ris = crate::Reg<ris::RisSpec>;
#[doc = "Raw interrupt status register"]
pub mod ris {
#[doc = "Register `RIS` reader"]
pub type R = crate::R<RisSpec>;
#[doc = "Register `RIS` writer"]
pub type W = crate::W<RisSpec>;
#[doc = "Field `CTSM` reader - nUARTCTS modem interrupt status"]
pub type CtsmR = crate::BitReader;
#[doc = "Field `CTSM` writer - nUARTCTS modem interrupt status"]
pub type CtsmW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RX` reader - Receive interrupt status"]
pub type RxR = crate::BitReader;
#[doc = "Field `RX` writer - Receive interrupt status"]
pub type RxW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TX` reader - Transmit interrupt status"]
pub type TxR = crate::BitReader;
#[doc = "Field `TX` writer - Transmit interrupt status"]
pub type TxW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RT` reader - Receive timeout interrupt status"]
pub type RtR = crate::BitReader;
#[doc = "Field `RT` writer - Receive timeout interrupt status"]
pub type RtW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `FE` reader - Framing error interrupt status"]
pub type FeR = crate::BitReader;
#[doc = "Field `FE` writer - Framing error interrupt status"]
pub type FeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PE` reader - Parity error interrupt status"]
pub type PeR = crate::BitReader;
#[doc = "Field `PE` writer - Parity error interrupt status"]
pub type PeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `BE` reader - Break error interrupt status"]
pub type BeR = crate::BitReader;
#[doc = "Field `BE` writer - Break error interrupt status"]
pub type BeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OE` reader - Overrun error interrupt status"]
pub type OeR = crate::BitReader;
#[doc = "Field `OE` writer - Overrun error interrupt status"]
pub type OeW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 1 - nUARTCTS modem interrupt status"]
#[inline(always)]
pub fn ctsm(&self) -> CtsmR {
CtsmR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 4 - Receive interrupt status"]
#[inline(always)]
pub fn rx(&self) -> RxR {
RxR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Transmit interrupt status"]
#[inline(always)]
pub fn tx(&self) -> TxR {
TxR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Receive timeout interrupt status"]
#[inline(always)]
pub fn rt(&self) -> RtR {
RtR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Framing error interrupt status"]
#[inline(always)]
pub fn fe(&self) -> FeR {
FeR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - Parity error interrupt status"]
#[inline(always)]
pub fn pe(&self) -> PeR {
PeR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - Break error interrupt status"]
#[inline(always)]
pub fn be(&self) -> BeR {
BeR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - Overrun error interrupt status"]
#[inline(always)]
pub fn oe(&self) -> OeR {
OeR::new(((self.bits >> 10) & 1) != 0)
}
}
impl W {
#[doc = "Bit 1 - nUARTCTS modem interrupt status"]
#[inline(always)]
pub fn ctsm(&mut self) -> CtsmW<RisSpec> {
CtsmW::new(self, 1)
}
#[doc = "Bit 4 - Receive interrupt status"]
#[inline(always)]
pub fn rx(&mut self) -> RxW<RisSpec> {
RxW::new(self, 4)
}
#[doc = "Bit 5 - Transmit interrupt status"]
#[inline(always)]
pub fn tx(&mut self) -> TxW<RisSpec> {
TxW::new(self, 5)
}
#[doc = "Bit 6 - Receive timeout interrupt status"]
#[inline(always)]
pub fn rt(&mut self) -> RtW<RisSpec> {
RtW::new(self, 6)
}
#[doc = "Bit 7 - Framing error interrupt status"]
#[inline(always)]
pub fn fe(&mut self) -> FeW<RisSpec> {
FeW::new(self, 7)
}
#[doc = "Bit 8 - Parity error interrupt status"]
#[inline(always)]
pub fn pe(&mut self) -> PeW<RisSpec> {
PeW::new(self, 8)
}
#[doc = "Bit 9 - Break error interrupt status"]
#[inline(always)]
pub fn be(&mut self) -> BeW<RisSpec> {
BeW::new(self, 9)
}
#[doc = "Bit 10 - Overrun error interrupt status"]
#[inline(always)]
pub fn oe(&mut self) -> OeW<RisSpec> {
OeW::new(self, 10)
}
}
#[doc = "Raw interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`ris::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ris::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RisSpec;
impl crate::RegisterSpec for RisSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ris::R`](R) reader structure"]
impl crate::Readable for RisSpec {}
#[doc = "`write(|w| ..)` method takes [`ris::W`](W) writer structure"]
impl crate::Writable for RisSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets RIS to value 0"]
impl crate::Resettable for RisSpec {}
}
#[doc = "MIS (rw) register accessor: Masked interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`mis::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mis::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mis`] module"]
#[doc(alias = "MIS")]
pub type Mis = crate::Reg<mis::MisSpec>;
#[doc = "Masked interrupt status register"]
pub mod mis {
#[doc = "Register `MIS` reader"]
pub type R = crate::R<MisSpec>;
#[doc = "Register `MIS` writer"]
pub type W = crate::W<MisSpec>;
#[doc = "Field `CTSM` reader - nUARTCTS modem masked interrupt status"]
pub type CtsmR = crate::BitReader;
#[doc = "Field `CTSM` writer - nUARTCTS modem masked interrupt status"]
pub type CtsmW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RX` reader - Receive masked interrupt status"]
pub type RxR = crate::BitReader;
#[doc = "Field `RX` writer - Receive masked interrupt status"]
pub type RxW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TX` reader - Transmit masked interrupt status"]
pub type TxR = crate::BitReader;
#[doc = "Field `TX` writer - Transmit masked interrupt status"]
pub type TxW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RT` reader - Receive timeout masked interrupt status"]
pub type RtR = crate::BitReader;
#[doc = "Field `RT` writer - Receive timeout masked interrupt status"]
pub type RtW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `FE` reader - Framing error masked interrupt status"]
pub type FeR = crate::BitReader;
#[doc = "Field `FE` writer - Framing error masked interrupt status"]
pub type FeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PE` reader - Parity error masked interrupt status"]
pub type PeR = crate::BitReader;
#[doc = "Field `PE` writer - Parity error masked interrupt status"]
pub type PeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `BE` reader - Break error masked interrupt status"]
pub type BeR = crate::BitReader;
#[doc = "Field `BE` writer - Break error masked interrupt status"]
pub type BeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OE` reader - Overrun error masked interrupt status"]
pub type OeR = crate::BitReader;
#[doc = "Field `OE` writer - Overrun error masked interrupt status"]
pub type OeW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 1 - nUARTCTS modem masked interrupt status"]
#[inline(always)]
pub fn ctsm(&self) -> CtsmR {
CtsmR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 4 - Receive masked interrupt status"]
#[inline(always)]
pub fn rx(&self) -> RxR {
RxR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Transmit masked interrupt status"]
#[inline(always)]
pub fn tx(&self) -> TxR {
TxR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Receive timeout masked interrupt status"]
#[inline(always)]
pub fn rt(&self) -> RtR {
RtR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Framing error masked interrupt status"]
#[inline(always)]
pub fn fe(&self) -> FeR {
FeR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - Parity error masked interrupt status"]
#[inline(always)]
pub fn pe(&self) -> PeR {
PeR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - Break error masked interrupt status"]
#[inline(always)]
pub fn be(&self) -> BeR {
BeR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - Overrun error masked interrupt status"]
#[inline(always)]
pub fn oe(&self) -> OeR {
OeR::new(((self.bits >> 10) & 1) != 0)
}
}
impl W {
#[doc = "Bit 1 - nUARTCTS modem masked interrupt status"]
#[inline(always)]
pub fn ctsm(&mut self) -> CtsmW<MisSpec> {
CtsmW::new(self, 1)
}
#[doc = "Bit 4 - Receive masked interrupt status"]
#[inline(always)]
pub fn rx(&mut self) -> RxW<MisSpec> {
RxW::new(self, 4)
}
#[doc = "Bit 5 - Transmit masked interrupt status"]
#[inline(always)]
pub fn tx(&mut self) -> TxW<MisSpec> {
TxW::new(self, 5)
}
#[doc = "Bit 6 - Receive timeout masked interrupt status"]
#[inline(always)]
pub fn rt(&mut self) -> RtW<MisSpec> {
RtW::new(self, 6)
}
#[doc = "Bit 7 - Framing error masked interrupt status"]
#[inline(always)]
pub fn fe(&mut self) -> FeW<MisSpec> {
FeW::new(self, 7)
}
#[doc = "Bit 8 - Parity error masked interrupt status"]
#[inline(always)]
pub fn pe(&mut self) -> PeW<MisSpec> {
PeW::new(self, 8)
}
#[doc = "Bit 9 - Break error masked interrupt status"]
#[inline(always)]
pub fn be(&mut self) -> BeW<MisSpec> {
BeW::new(self, 9)
}
#[doc = "Bit 10 - Overrun error masked interrupt status"]
#[inline(always)]
pub fn oe(&mut self) -> OeW<MisSpec> {
OeW::new(self, 10)
}
}
#[doc = "Masked interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`mis::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mis::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MisSpec;
impl crate::RegisterSpec for MisSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`mis::R`](R) reader structure"]
impl crate::Readable for MisSpec {}
#[doc = "`write(|w| ..)` method takes [`mis::W`](W) writer structure"]
impl crate::Writable for MisSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets MIS to value 0"]
impl crate::Resettable for MisSpec {}
}
#[doc = "ICR (rw) register accessor: Interrupt clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`icr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@icr`] module"]
#[doc(alias = "ICR")]
pub type Icr = crate::Reg<icr::IcrSpec>;
#[doc = "Interrupt clear register"]
pub mod icr {
#[doc = "Register `ICR` reader"]
pub type R = crate::R<IcrSpec>;
#[doc = "Register `ICR` writer"]
pub type W = crate::W<IcrSpec>;
#[doc = "Field `CTSM` reader - nUARTCTS modem interrupt clear"]
pub type CtsmR = crate::BitReader;
#[doc = "Field `CTSM` writer - nUARTCTS modem interrupt clear"]
pub type CtsmW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RX` reader - Receive interrupt clear"]
pub type RxR = crate::BitReader;
#[doc = "Field `RX` writer - Receive interrupt clear"]
pub type RxW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TX` reader - Transmit interrupt clear"]
pub type TxR = crate::BitReader;
#[doc = "Field `TX` writer - Transmit interrupt clear"]
pub type TxW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RT` reader - Receive timeout interrupt clear"]
pub type RtR = crate::BitReader;
#[doc = "Field `RT` writer - Receive timeout interrupt clear"]
pub type RtW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `FE` reader - Framing error interrupt clear"]
pub type FeR = crate::BitReader;
#[doc = "Field `FE` writer - Framing error interrupt clear"]
pub type FeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PE` reader - Parity error interrupt clear"]
pub type PeR = crate::BitReader;
#[doc = "Field `PE` writer - Parity error interrupt clear"]
pub type PeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `BE` reader - Break error interrupt clear"]
pub type BeR = crate::BitReader;
#[doc = "Field `BE` writer - Break error interrupt clear"]
pub type BeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OE` reader - Overrun error interrupt clear"]
pub type OeR = crate::BitReader;
#[doc = "Field `OE` writer - Overrun error interrupt clear"]
pub type OeW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 1 - nUARTCTS modem interrupt clear"]
#[inline(always)]
pub fn ctsm(&self) -> CtsmR {
CtsmR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 4 - Receive interrupt clear"]
#[inline(always)]
pub fn rx(&self) -> RxR {
RxR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Transmit interrupt clear"]
#[inline(always)]
pub fn tx(&self) -> TxR {
TxR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Receive timeout interrupt clear"]
#[inline(always)]
pub fn rt(&self) -> RtR {
RtR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Framing error interrupt clear"]
#[inline(always)]
pub fn fe(&self) -> FeR {
FeR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - Parity error interrupt clear"]
#[inline(always)]
pub fn pe(&self) -> PeR {
PeR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - Break error interrupt clear"]
#[inline(always)]
pub fn be(&self) -> BeR {
BeR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - Overrun error interrupt clear"]
#[inline(always)]
pub fn oe(&self) -> OeR {
OeR::new(((self.bits >> 10) & 1) != 0)
}
}
impl W {
#[doc = "Bit 1 - nUARTCTS modem interrupt clear"]
#[inline(always)]
pub fn ctsm(&mut self) -> CtsmW<IcrSpec> {
CtsmW::new(self, 1)
}
#[doc = "Bit 4 - Receive interrupt clear"]
#[inline(always)]
pub fn rx(&mut self) -> RxW<IcrSpec> {
RxW::new(self, 4)
}
#[doc = "Bit 5 - Transmit interrupt clear"]
#[inline(always)]
pub fn tx(&mut self) -> TxW<IcrSpec> {
TxW::new(self, 5)
}
#[doc = "Bit 6 - Receive timeout interrupt clear"]
#[inline(always)]
pub fn rt(&mut self) -> RtW<IcrSpec> {
RtW::new(self, 6)
}
#[doc = "Bit 7 - Framing error interrupt clear"]
#[inline(always)]
pub fn fe(&mut self) -> FeW<IcrSpec> {
FeW::new(self, 7)
}
#[doc = "Bit 8 - Parity error interrupt clear"]
#[inline(always)]
pub fn pe(&mut self) -> PeW<IcrSpec> {
PeW::new(self, 8)
}
#[doc = "Bit 9 - Break error interrupt clear"]
#[inline(always)]
pub fn be(&mut self) -> BeW<IcrSpec> {
BeW::new(self, 9)
}
#[doc = "Bit 10 - Overrun error interrupt clear"]
#[inline(always)]
pub fn oe(&mut self) -> OeW<IcrSpec> {
OeW::new(self, 10)
}
}
#[doc = "Interrupt clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`icr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IcrSpec;
impl crate::RegisterSpec for IcrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`icr::R`](R) reader structure"]
impl crate::Readable for IcrSpec {}
#[doc = "`write(|w| ..)` method takes [`icr::W`](W) writer structure"]
impl crate::Writable for IcrSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ICR to value 0"]
impl crate::Resettable for IcrSpec {}
}
#[doc = "DMACR (rw) register accessor: DMA control register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmacr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmacr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmacr`] module"]
#[doc(alias = "DMACR")]
pub type Dmacr = crate::Reg<dmacr::DmacrSpec>;
#[doc = "DMA control register"]
pub mod dmacr {
#[doc = "Register `DMACR` reader"]
pub type R = crate::R<DmacrSpec>;
#[doc = "Register `DMACR` writer"]
pub type W = crate::W<DmacrSpec>;
#[doc = "Field `RX_EN` reader - Receive DMA enable"]
pub type RxEnR = crate::BitReader;
#[doc = "Field `RX_EN` writer - Receive DMA enable"]
pub type RxEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TX_EN` reader - Transmit DMA enable"]
pub type TxEnR = crate::BitReader;
#[doc = "Field `TX_EN` writer - Transmit DMA enable"]
pub type TxEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ON_ERR` reader - Stop DMA on error"]
pub type OnErrR = crate::BitReader;
#[doc = "Field `ON_ERR` writer - Stop DMA on error"]
pub type OnErrW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - Receive DMA enable"]
#[inline(always)]
pub fn rx_en(&self) -> RxEnR {
RxEnR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Transmit DMA enable"]
#[inline(always)]
pub fn tx_en(&self) -> TxEnR {
TxEnR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Stop DMA on error"]
#[inline(always)]
pub fn on_err(&self) -> OnErrR {
OnErrR::new(((self.bits >> 2) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Receive DMA enable"]
#[inline(always)]
pub fn rx_en(&mut self) -> RxEnW<DmacrSpec> {
RxEnW::new(self, 0)
}
#[doc = "Bit 1 - Transmit DMA enable"]
#[inline(always)]
pub fn tx_en(&mut self) -> TxEnW<DmacrSpec> {
TxEnW::new(self, 1)
}
#[doc = "Bit 2 - Stop DMA on error"]
#[inline(always)]
pub fn on_err(&mut self) -> OnErrW<DmacrSpec> {
OnErrW::new(self, 2)
}
}
#[doc = "DMA control register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmacr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmacr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DmacrSpec;
impl crate::RegisterSpec for DmacrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`dmacr::R`](R) reader structure"]
impl crate::Readable for DmacrSpec {}
#[doc = "`write(|w| ..)` method takes [`dmacr::W`](W) writer structure"]
impl crate::Writable for DmacrSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets DMACR to value 0"]
impl crate::Resettable for DmacrSpec {}
}
}
#[doc = "UART registers"]
pub type Uart1 = crate::Periph<uart0::RegisterBlock, 0x4002_6000>;
impl core::fmt::Debug for Uart1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Uart1").finish()
}
}
#[doc = "UART registers"]
pub use self::uart0 as uart1;
#[doc = "UART registers"]
pub type Uart2 = crate::Periph<uart0::RegisterBlock, 0x4002_7000>;
impl core::fmt::Debug for Uart2 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Uart2").finish()
}
}
#[doc = "UART registers"]
pub use self::uart0 as uart2;
#[doc = "UART registers"]
pub type Uart3 = crate::Periph<uart0::RegisterBlock, 0x4002_8000>;
impl core::fmt::Debug for Uart3 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Uart3").finish()
}
}
#[doc = "UART registers"]
pub use self::uart0 as uart3;
#[doc = "UART registers"]
pub type Uart4 = crate::Periph<uart0::RegisterBlock, 0x4002_9000>;
impl core::fmt::Debug for Uart4 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Uart4").finish()
}
}
#[doc = "UART registers"]
pub use self::uart0 as uart4;
#[doc = "CAN registers"]
pub type Can0 = crate::Periph<can0::RegisterBlock, 0x4002_a000>;
impl core::fmt::Debug for Can0 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Can0").finish()
}
}
#[doc = "CAN registers"]
pub mod can0 {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
mod_: Mod,
cmr: Cmr,
sr: Sr,
ir: Ir,
ier: Ier,
_reserved5: [u8; 0x04],
btr0: Btr0,
btr1: Btr1,
ocr: Ocr,
_reserved8: [u8; 0x08],
alc: Alc,
ecc: Ecc,
ewlr: Ewlr,
rxerr: Rxerr,
txerr: Txerr,
_reserved_13_acr0: [u8; 0x04],
_reserved_14_acr1: [u8; 0x04],
_reserved_15_acr2: [u8; 0x04],
_reserved_16_acr3: [u8; 0x04],
_reserved_17_amr0: [u8; 0x04],
_reserved_18_amr1: [u8; 0x04],
_reserved_19_amr2: [u8; 0x04],
_reserved_20_amr3: [u8; 0x04],
data7: Data7,
data8: Data8,
data9: Data9,
data10: Data10,
data11: Data11,
rmc: Rmc,
rbsa: Rbsa,
_reserved28: [u8; 0x0104],
tx_frame: TxFrame,
tx_data0: TxData0,
tx_data1: TxData1,
tx_data2: TxData2,
tx_data3: TxData3,
tx_data4: TxData4,
tx_data5: TxData5,
tx_data6: TxData6,
tx_data7: TxData7,
tx_data8: TxData8,
tx_data9: TxData9,
tx_data10: TxData10,
tx_data11: TxData11,
}
impl RegisterBlock {
#[doc = "0x00 - Mode register"]
#[inline(always)]
pub const fn mod_(&self) -> &Mod {
&self.mod_
}
#[doc = "0x04 - Command register"]
#[inline(always)]
pub const fn cmr(&self) -> &Cmr {
&self.cmr
}
#[doc = "0x08 - Status register"]
#[inline(always)]
pub const fn sr(&self) -> &Sr {
&self.sr
}
#[doc = "0x0c - Interrupt register"]
#[inline(always)]
pub const fn ir(&self) -> &Ir {
&self.ir
}
#[doc = "0x10 - Interrupt enable register"]
#[inline(always)]
pub const fn ier(&self) -> &Ier {
&self.ier
}
#[doc = "0x18 - Bus Timing 0"]
#[inline(always)]
pub const fn btr0(&self) -> &Btr0 {
&self.btr0
}
#[doc = "0x1c - Bus Timing 1"]
#[inline(always)]
pub const fn btr1(&self) -> &Btr1 {
&self.btr1
}
#[doc = "0x20 - Output Control Register"]
#[inline(always)]
pub const fn ocr(&self) -> &Ocr {
&self.ocr
}
#[doc = "0x2c - Arbitration Lost Capture"]
#[inline(always)]
pub const fn alc(&self) -> &Alc {
&self.alc
}
#[doc = "0x30 - Error Code Capture"]
#[inline(always)]
pub const fn ecc(&self) -> &Ecc {
&self.ecc
}
#[doc = "0x34 - Error Warning Limit"]
#[inline(always)]
pub const fn ewlr(&self) -> &Ewlr {
&self.ewlr
}
#[doc = "0x38 - Receive Error Counter"]
#[inline(always)]
pub const fn rxerr(&self) -> &Rxerr {
&self.rxerr
}
#[doc = "0x3c - Transmit Error Counter"]
#[inline(always)]
pub const fn txerr(&self) -> &Txerr {
&self.txerr
}
#[doc = "0x40 - Acceptance Code Register"]
#[inline(always)]
pub const fn acr0(&self) -> &Acr0 {
unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(64).cast() }
}
#[doc = "0x40 - Transfer Frame Information"]
#[inline(always)]
pub const fn frame(&self) -> &Frame {
unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(64).cast() }
}
#[doc = "0x44 - Transfer Data Information"]
#[inline(always)]
pub const fn data0(&self) -> &Data0 {
unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(68).cast() }
}
#[doc = "0x44 - Acceptance Code Register"]
#[inline(always)]
pub const fn acr1(&self) -> &Acr1 {
unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(68).cast() }
}
#[doc = "0x48 - Transfer Data Information"]
#[inline(always)]
pub const fn data1(&self) -> &Data1 {
unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(72).cast() }
}
#[doc = "0x48 - Acceptance Code Register"]
#[inline(always)]
pub const fn acr2(&self) -> &Acr2 {
unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(72).cast() }
}
#[doc = "0x4c - Transfer Data Information"]
#[inline(always)]
pub const fn data2(&self) -> &Data2 {
unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(76).cast() }
}
#[doc = "0x4c - Acceptance Code Register"]
#[inline(always)]
pub const fn acr3(&self) -> &Acr3 {
unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(76).cast() }
}
#[doc = "0x50 - Transfer Data Information"]
#[inline(always)]
pub const fn data3(&self) -> &Data3 {
unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(80).cast() }
}
#[doc = "0x50 - Acceptance Mask Register"]
#[inline(always)]
pub const fn amr0(&self) -> &Amr0 {
unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(80).cast() }
}
#[doc = "0x54 - Transfer Data Information"]
#[inline(always)]
pub const fn data4(&self) -> &Data4 {
unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(84).cast() }
}
#[doc = "0x54 - Acceptance Mask Register"]
#[inline(always)]
pub const fn amr1(&self) -> &Amr1 {
unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(84).cast() }
}
#[doc = "0x58 - Transfer Data Information"]
#[inline(always)]
pub const fn data5(&self) -> &Data5 {
unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(88).cast() }
}
#[doc = "0x58 - Acceptance Mask Register"]
#[inline(always)]
pub const fn amr2(&self) -> &Amr2 {
unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(88).cast() }
}
#[doc = "0x5c - Transfer Data Information"]
#[inline(always)]
pub const fn data6(&self) -> &Data6 {
unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(92).cast() }
}
#[doc = "0x5c - Acceptance Mask Register"]
#[inline(always)]
pub const fn amr3(&self) -> &Amr3 {
unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(92).cast() }
}
#[doc = "0x60 - Transfer Data Information"]
#[inline(always)]
pub const fn data7(&self) -> &Data7 {
&self.data7
}
#[doc = "0x64 - Transfer Data Information"]
#[inline(always)]
pub const fn data8(&self) -> &Data8 {
&self.data8
}
#[doc = "0x68 - Transfer Data Information"]
#[inline(always)]
pub const fn data9(&self) -> &Data9 {
&self.data9
}
#[doc = "0x6c - Transfer Data Information"]
#[inline(always)]
pub const fn data10(&self) -> &Data10 {
&self.data10
}
#[doc = "0x70 - Transfer Data Information"]
#[inline(always)]
pub const fn data11(&self) -> &Data11 {
&self.data11
}
#[doc = "0x74 - Receive Message Counter"]
#[inline(always)]
pub const fn rmc(&self) -> &Rmc {
&self.rmc
}
#[doc = "0x78 - Receive Buffer Start Address"]
#[inline(always)]
pub const fn rbsa(&self) -> &Rbsa {
&self.rbsa
}
#[doc = "0x180 - Transmit Frame Information"]
#[inline(always)]
pub const fn tx_frame(&self) -> &TxFrame {
&self.tx_frame
}
#[doc = "0x184 - Transmit Data Information"]
#[inline(always)]
pub const fn tx_data0(&self) -> &TxData0 {
&self.tx_data0
}
#[doc = "0x188 - Transmit Data Information"]
#[inline(always)]
pub const fn tx_data1(&self) -> &TxData1 {
&self.tx_data1
}
#[doc = "0x18c - Transmit Data Information"]
#[inline(always)]
pub const fn tx_data2(&self) -> &TxData2 {
&self.tx_data2
}
#[doc = "0x190 - Transmit Data Information"]
#[inline(always)]
pub const fn tx_data3(&self) -> &TxData3 {
&self.tx_data3
}
#[doc = "0x194 - Transmit Data Information"]
#[inline(always)]
pub const fn tx_data4(&self) -> &TxData4 {
&self.tx_data4
}
#[doc = "0x198 - Transmit Data Information"]
#[inline(always)]
pub const fn tx_data5(&self) -> &TxData5 {
&self.tx_data5
}
#[doc = "0x19c - Transmit Data Information"]
#[inline(always)]
pub const fn tx_data6(&self) -> &TxData6 {
&self.tx_data6
}
#[doc = "0x1a0 - Transmit Data Information"]
#[inline(always)]
pub const fn tx_data7(&self) -> &TxData7 {
&self.tx_data7
}
#[doc = "0x1a4 - Transmit Data Information"]
#[inline(always)]
pub const fn tx_data8(&self) -> &TxData8 {
&self.tx_data8
}
#[doc = "0x1a8 - Transmit Data Information"]
#[inline(always)]
pub const fn tx_data9(&self) -> &TxData9 {
&self.tx_data9
}
#[doc = "0x1ac - Transmit Data Information"]
#[inline(always)]
pub const fn tx_data10(&self) -> &TxData10 {
&self.tx_data10
}
#[doc = "0x1b0 - Transmit Data Information"]
#[inline(always)]
pub const fn tx_data11(&self) -> &TxData11 {
&self.tx_data11
}
}
#[doc = "MOD (rw) register accessor: Mode register\n\nYou can [`read`](crate::Reg::read) this register and get [`mod_::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mod_::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mod_`] module"]
#[doc(alias = "MOD")]
pub type Mod = crate::Reg<mod_::ModSpec>;
#[doc = "Mode register"]
pub mod mod_ {
#[doc = "Register `MOD` reader"]
pub type R = crate::R<ModSpec>;
#[doc = "Register `MOD` writer"]
pub type W = crate::W<ModSpec>;
#[doc = "Field `RM` reader - Reset Mode"]
pub type RmR = crate::BitReader;
#[doc = "Field `RM` writer - Reset Mode"]
pub type RmW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `LOM` reader - Listen Only Mode"]
pub type LomR = crate::BitReader;
#[doc = "Field `LOM` writer - Listen Only Mode"]
pub type LomW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `STM` reader - Self Test Mode"]
pub type StmR = crate::BitReader;
#[doc = "Field `STM` writer - Self Test Mode"]
pub type StmW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Acceptance Filter Mode\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Afm {
#[doc = "0: Dual"]
Dual = 0,
#[doc = "1: Single"]
Single = 1,
}
impl From<Afm> for bool {
#[inline(always)]
fn from(variant: Afm) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `AFM` reader - Acceptance Filter Mode"]
pub type AfmR = crate::BitReader<Afm>;
impl AfmR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Afm {
match self.bits {
false => Afm::Dual,
true => Afm::Single,
}
}
#[doc = "Dual"]
#[inline(always)]
pub fn is_dual(&self) -> bool {
*self == Afm::Dual
}
#[doc = "Single"]
#[inline(always)]
pub fn is_single(&self) -> bool {
*self == Afm::Single
}
}
#[doc = "Field `AFM` writer - Acceptance Filter Mode"]
pub type AfmW<'a, REG> = crate::BitWriter<'a, REG, Afm>;
impl<'a, REG> AfmW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Dual"]
#[inline(always)]
pub fn dual(self) -> &'a mut crate::W<REG> {
self.variant(Afm::Dual)
}
#[doc = "Single"]
#[inline(always)]
pub fn single(self) -> &'a mut crate::W<REG> {
self.variant(Afm::Single)
}
}
#[doc = "Field `SM` reader - Sleep Mode"]
pub type SmR = crate::BitReader;
#[doc = "Field `SM` writer - Sleep Mode"]
pub type SmW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - Reset Mode"]
#[inline(always)]
pub fn rm(&self) -> RmR {
RmR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Listen Only Mode"]
#[inline(always)]
pub fn lom(&self) -> LomR {
LomR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Self Test Mode"]
#[inline(always)]
pub fn stm(&self) -> StmR {
StmR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Acceptance Filter Mode"]
#[inline(always)]
pub fn afm(&self) -> AfmR {
AfmR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Sleep Mode"]
#[inline(always)]
pub fn sm(&self) -> SmR {
SmR::new(((self.bits >> 4) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Reset Mode"]
#[inline(always)]
pub fn rm(&mut self) -> RmW<ModSpec> {
RmW::new(self, 0)
}
#[doc = "Bit 1 - Listen Only Mode"]
#[inline(always)]
pub fn lom(&mut self) -> LomW<ModSpec> {
LomW::new(self, 1)
}
#[doc = "Bit 2 - Self Test Mode"]
#[inline(always)]
pub fn stm(&mut self) -> StmW<ModSpec> {
StmW::new(self, 2)
}
#[doc = "Bit 3 - Acceptance Filter Mode"]
#[inline(always)]
pub fn afm(&mut self) -> AfmW<ModSpec> {
AfmW::new(self, 3)
}
#[doc = "Bit 4 - Sleep Mode"]
#[inline(always)]
pub fn sm(&mut self) -> SmW<ModSpec> {
SmW::new(self, 4)
}
}
#[doc = "Mode register\n\nYou can [`read`](crate::Reg::read) this register and get [`mod_::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mod_::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ModSpec;
impl crate::RegisterSpec for ModSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`mod_::R`](R) reader structure"]
impl crate::Readable for ModSpec {}
#[doc = "`write(|w| ..)` method takes [`mod_::W`](W) writer structure"]
impl crate::Writable for ModSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets MOD to value 0"]
impl crate::Resettable for ModSpec {}
}
#[doc = "CMR (w) register accessor: Command register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmr`] module"]
#[doc(alias = "CMR")]
pub type Cmr = crate::Reg<cmr::CmrSpec>;
#[doc = "Command register"]
pub mod cmr {
#[doc = "Register `CMR` writer"]
pub type W = crate::W<CmrSpec>;
#[doc = "Field `TR` writer - Transmission Request"]
pub type TrW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `AT` writer - Abort Transmission"]
pub type AtW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RRB` writer - Release Receive Buffer"]
pub type RrbW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CDO` writer - Clear Data Overrun"]
pub type CdoW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SRR` writer - Self Reception Request"]
pub type SrrW<'a, REG> = crate::BitWriter<'a, REG>;
impl W {
#[doc = "Bit 0 - Transmission Request"]
#[inline(always)]
pub fn tr(&mut self) -> TrW<CmrSpec> {
TrW::new(self, 0)
}
#[doc = "Bit 1 - Abort Transmission"]
#[inline(always)]
pub fn at(&mut self) -> AtW<CmrSpec> {
AtW::new(self, 1)
}
#[doc = "Bit 2 - Release Receive Buffer"]
#[inline(always)]
pub fn rrb(&mut self) -> RrbW<CmrSpec> {
RrbW::new(self, 2)
}
#[doc = "Bit 3 - Clear Data Overrun"]
#[inline(always)]
pub fn cdo(&mut self) -> CdoW<CmrSpec> {
CdoW::new(self, 3)
}
#[doc = "Bit 4 - Self Reception Request"]
#[inline(always)]
pub fn srr(&mut self) -> SrrW<CmrSpec> {
SrrW::new(self, 4)
}
}
#[doc = "Command register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CmrSpec;
impl crate::RegisterSpec for CmrSpec {
type Ux = u32;
}
#[doc = "`write(|w| ..)` method takes [`cmr::W`](W) writer structure"]
impl crate::Writable for CmrSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets CMR to value 0"]
impl crate::Resettable for CmrSpec {}
}
#[doc = "SR (r) register accessor: Status register\n\nYou can [`read`](crate::Reg::read) this register and get [`sr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sr`] module"]
#[doc(alias = "SR")]
pub type Sr = crate::Reg<sr::SrSpec>;
#[doc = "Status register"]
pub mod sr {
#[doc = "Register `SR` reader"]
pub type R = crate::R<SrSpec>;
#[doc = "Field `RBS` reader - Receive Buffer Status"]
pub type RbsR = crate::BitReader;
#[doc = "Field `DOS` reader - Data Overrun Status"]
pub type DosR = crate::BitReader;
#[doc = "Field `TBS` reader - Transmit Buffer Status"]
pub type TbsR = crate::BitReader;
#[doc = "Field `TCS` reader - Transmission Complete Status"]
pub type TcsR = crate::BitReader;
#[doc = "Field `RS` reader - Receive Status"]
pub type RsR = crate::BitReader;
#[doc = "Field `TS` reader - Transmit Status"]
pub type TsR = crate::BitReader;
#[doc = "Field `ES` reader - Error Status"]
pub type EsR = crate::BitReader;
#[doc = "Field `BS` reader - Bus Status"]
pub type BsR = crate::BitReader;
impl R {
#[doc = "Bit 0 - Receive Buffer Status"]
#[inline(always)]
pub fn rbs(&self) -> RbsR {
RbsR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Data Overrun Status"]
#[inline(always)]
pub fn dos(&self) -> DosR {
DosR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Transmit Buffer Status"]
#[inline(always)]
pub fn tbs(&self) -> TbsR {
TbsR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Transmission Complete Status"]
#[inline(always)]
pub fn tcs(&self) -> TcsR {
TcsR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Receive Status"]
#[inline(always)]
pub fn rs(&self) -> RsR {
RsR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Transmit Status"]
#[inline(always)]
pub fn ts(&self) -> TsR {
TsR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Error Status"]
#[inline(always)]
pub fn es(&self) -> EsR {
EsR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Bus Status"]
#[inline(always)]
pub fn bs(&self) -> BsR {
BsR::new(((self.bits >> 7) & 1) != 0)
}
}
#[doc = "Status register\n\nYou can [`read`](crate::Reg::read) this register and get [`sr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SrSpec;
impl crate::RegisterSpec for SrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`sr::R`](R) reader structure"]
impl crate::Readable for SrSpec {}
#[doc = "`reset()` method sets SR to value 0"]
impl crate::Resettable for SrSpec {}
}
#[doc = "IR (r) register accessor: Interrupt register\n\nYou can [`read`](crate::Reg::read) this register and get [`ir::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ir`] module"]
#[doc(alias = "IR")]
pub type Ir = crate::Reg<ir::IrSpec>;
#[doc = "Interrupt register"]
pub mod ir {
#[doc = "Register `IR` reader"]
pub type R = crate::R<IrSpec>;
#[doc = "Field `RI` reader - Receive Interrupt"]
pub type RiR = crate::BitReader;
#[doc = "Field `TI` reader - Transmit Interrupt"]
pub type TiR = crate::BitReader;
#[doc = "Field `EI` reader - Error Warning Interrupt"]
pub type EiR = crate::BitReader;
#[doc = "Field `DOI` reader - Data Overrun Interrupt"]
pub type DoiR = crate::BitReader;
#[doc = "Field `WUI` reader - Wake-Up Interrupt"]
pub type WuiR = crate::BitReader;
#[doc = "Field `EPI` reader - Error Passive Interrupt"]
pub type EpiR = crate::BitReader;
#[doc = "Field `ALI` reader - Arbitration Lost Interrupt"]
pub type AliR = crate::BitReader;
#[doc = "Field `BEI` reader - Bus Error Interrupt"]
pub type BeiR = crate::BitReader;
impl R {
#[doc = "Bit 0 - Receive Interrupt"]
#[inline(always)]
pub fn ri(&self) -> RiR {
RiR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Transmit Interrupt"]
#[inline(always)]
pub fn ti(&self) -> TiR {
TiR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Error Warning Interrupt"]
#[inline(always)]
pub fn ei(&self) -> EiR {
EiR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Data Overrun Interrupt"]
#[inline(always)]
pub fn doi(&self) -> DoiR {
DoiR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Wake-Up Interrupt"]
#[inline(always)]
pub fn wui(&self) -> WuiR {
WuiR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Error Passive Interrupt"]
#[inline(always)]
pub fn epi(&self) -> EpiR {
EpiR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Arbitration Lost Interrupt"]
#[inline(always)]
pub fn ali(&self) -> AliR {
AliR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Bus Error Interrupt"]
#[inline(always)]
pub fn bei(&self) -> BeiR {
BeiR::new(((self.bits >> 7) & 1) != 0)
}
}
#[doc = "Interrupt register\n\nYou can [`read`](crate::Reg::read) this register and get [`ir::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IrSpec;
impl crate::RegisterSpec for IrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ir::R`](R) reader structure"]
impl crate::Readable for IrSpec {}
#[doc = "`reset()` method sets IR to value 0"]
impl crate::Resettable for IrSpec {}
}
#[doc = "IER (rw) register accessor: Interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`ier::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ier::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ier`] module"]
#[doc(alias = "IER")]
pub type Ier = crate::Reg<ier::IerSpec>;
#[doc = "Interrupt enable register"]
pub mod ier {
#[doc = "Register `IER` reader"]
pub type R = crate::R<IerSpec>;
#[doc = "Register `IER` writer"]
pub type W = crate::W<IerSpec>;
#[doc = "Field `RIE` reader - Receive Interrupt Enable"]
pub type RieR = crate::BitReader;
#[doc = "Field `RIE` writer - Receive Interrupt Enable"]
pub type RieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TIE` reader - Transmit Interrupt Enable"]
pub type TieR = crate::BitReader;
#[doc = "Field `TIE` writer - Transmit Interrupt Enable"]
pub type TieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EIE` reader - Error Warning Interrupt Enable"]
pub type EieR = crate::BitReader;
#[doc = "Field `EIE` writer - Error Warning Interrupt Enable"]
pub type EieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DOIE` reader - Data Overrun Interrupt Enable"]
pub type DoieR = crate::BitReader;
#[doc = "Field `DOIE` writer - Data Overrun Interrupt Enable"]
pub type DoieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `WUIE` reader - Wake-Up Interrupt Enable"]
pub type WuieR = crate::BitReader;
#[doc = "Field `WUIE` writer - Wake-Up Interrupt Enable"]
pub type WuieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EPIE` reader - Error Passive Interrupt Enable"]
pub type EpieR = crate::BitReader;
#[doc = "Field `EPIE` writer - Error Passive Interrupt Enable"]
pub type EpieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ALIE` reader - Arbitration Lost Interrupt Enable"]
pub type AlieR = crate::BitReader;
#[doc = "Field `ALIE` writer - Arbitration Lost Interrupt Enable"]
pub type AlieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `BEIE` reader - Bus Error Interrupt Enable"]
pub type BeieR = crate::BitReader;
#[doc = "Field `BEIE` writer - Bus Error Interrupt Enable"]
pub type BeieW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - Receive Interrupt Enable"]
#[inline(always)]
pub fn rie(&self) -> RieR {
RieR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Transmit Interrupt Enable"]
#[inline(always)]
pub fn tie(&self) -> TieR {
TieR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Error Warning Interrupt Enable"]
#[inline(always)]
pub fn eie(&self) -> EieR {
EieR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Data Overrun Interrupt Enable"]
#[inline(always)]
pub fn doie(&self) -> DoieR {
DoieR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Wake-Up Interrupt Enable"]
#[inline(always)]
pub fn wuie(&self) -> WuieR {
WuieR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Error Passive Interrupt Enable"]
#[inline(always)]
pub fn epie(&self) -> EpieR {
EpieR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Arbitration Lost Interrupt Enable"]
#[inline(always)]
pub fn alie(&self) -> AlieR {
AlieR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Bus Error Interrupt Enable"]
#[inline(always)]
pub fn beie(&self) -> BeieR {
BeieR::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Receive Interrupt Enable"]
#[inline(always)]
pub fn rie(&mut self) -> RieW<IerSpec> {
RieW::new(self, 0)
}
#[doc = "Bit 1 - Transmit Interrupt Enable"]
#[inline(always)]
pub fn tie(&mut self) -> TieW<IerSpec> {
TieW::new(self, 1)
}
#[doc = "Bit 2 - Error Warning Interrupt Enable"]
#[inline(always)]
pub fn eie(&mut self) -> EieW<IerSpec> {
EieW::new(self, 2)
}
#[doc = "Bit 3 - Data Overrun Interrupt Enable"]
#[inline(always)]
pub fn doie(&mut self) -> DoieW<IerSpec> {
DoieW::new(self, 3)
}
#[doc = "Bit 4 - Wake-Up Interrupt Enable"]
#[inline(always)]
pub fn wuie(&mut self) -> WuieW<IerSpec> {
WuieW::new(self, 4)
}
#[doc = "Bit 5 - Error Passive Interrupt Enable"]
#[inline(always)]
pub fn epie(&mut self) -> EpieW<IerSpec> {
EpieW::new(self, 5)
}
#[doc = "Bit 6 - Arbitration Lost Interrupt Enable"]
#[inline(always)]
pub fn alie(&mut self) -> AlieW<IerSpec> {
AlieW::new(self, 6)
}
#[doc = "Bit 7 - Bus Error Interrupt Enable"]
#[inline(always)]
pub fn beie(&mut self) -> BeieW<IerSpec> {
BeieW::new(self, 7)
}
}
#[doc = "Interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`ier::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ier::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IerSpec;
impl crate::RegisterSpec for IerSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ier::R`](R) reader structure"]
impl crate::Readable for IerSpec {}
#[doc = "`write(|w| ..)` method takes [`ier::W`](W) writer structure"]
impl crate::Writable for IerSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets IER to value 0"]
impl crate::Resettable for IerSpec {}
}
#[doc = "BTR0 (rw) register accessor: Bus Timing 0\n\nYou can [`read`](crate::Reg::read) this register and get [`btr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`btr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@btr0`] module"]
#[doc(alias = "BTR0")]
pub type Btr0 = crate::Reg<btr0::Btr0Spec>;
#[doc = "Bus Timing 0"]
pub mod btr0 {
#[doc = "Register `BTR0` reader"]
pub type R = crate::R<Btr0Spec>;
#[doc = "Register `BTR0` writer"]
pub type W = crate::W<Btr0Spec>;
#[doc = "Field `BRP` reader - Baud Rate Prescaler"]
pub type BrpR = crate::FieldReader;
#[doc = "Field `BRP` writer - Baud Rate Prescaler"]
pub type BrpW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `SJW` reader - Synchronization Jump Width"]
pub type SjwR = crate::FieldReader;
#[doc = "Field `SJW` writer - Synchronization Jump Width"]
pub type SjwW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
impl R {
#[doc = "Bits 0:5 - Baud Rate Prescaler"]
#[inline(always)]
pub fn brp(&self) -> BrpR {
BrpR::new((self.bits & 0x3f) as u8)
}
#[doc = "Bits 6:7 - Synchronization Jump Width"]
#[inline(always)]
pub fn sjw(&self) -> SjwR {
SjwR::new(((self.bits >> 6) & 3) as u8)
}
}
impl W {
#[doc = "Bits 0:5 - Baud Rate Prescaler"]
#[inline(always)]
pub fn brp(&mut self) -> BrpW<Btr0Spec> {
BrpW::new(self, 0)
}
#[doc = "Bits 6:7 - Synchronization Jump Width"]
#[inline(always)]
pub fn sjw(&mut self) -> SjwW<Btr0Spec> {
SjwW::new(self, 6)
}
}
#[doc = "Bus Timing 0\n\nYou can [`read`](crate::Reg::read) this register and get [`btr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`btr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Btr0Spec;
impl crate::RegisterSpec for Btr0Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`btr0::R`](R) reader structure"]
impl crate::Readable for Btr0Spec {}
#[doc = "`write(|w| ..)` method takes [`btr0::W`](W) writer structure"]
impl crate::Writable for Btr0Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets BTR0 to value 0"]
impl crate::Resettable for Btr0Spec {}
}
#[doc = "BTR1 (rw) register accessor: Bus Timing 1\n\nYou can [`read`](crate::Reg::read) this register and get [`btr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`btr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@btr1`] module"]
#[doc(alias = "BTR1")]
pub type Btr1 = crate::Reg<btr1::Btr1Spec>;
#[doc = "Bus Timing 1"]
pub mod btr1 {
#[doc = "Register `BTR1` reader"]
pub type R = crate::R<Btr1Spec>;
#[doc = "Register `BTR1` writer"]
pub type W = crate::W<Btr1Spec>;
#[doc = "Field `TSEG1` reader - Time Segment 1"]
pub type Tseg1R = crate::FieldReader;
#[doc = "Field `TSEG1` writer - Time Segment 1"]
pub type Tseg1W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `TSEG2` reader - Time Segment 2"]
pub type Tseg2R = crate::FieldReader;
#[doc = "Field `TSEG2` writer - Time Segment 2"]
pub type Tseg2W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `SAM` reader - Sampling"]
pub type SamR = crate::BitReader;
#[doc = "Field `SAM` writer - Sampling"]
pub type SamW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:3 - Time Segment 1"]
#[inline(always)]
pub fn tseg1(&self) -> Tseg1R {
Tseg1R::new((self.bits & 0x0f) as u8)
}
#[doc = "Bits 4:6 - Time Segment 2"]
#[inline(always)]
pub fn tseg2(&self) -> Tseg2R {
Tseg2R::new(((self.bits >> 4) & 7) as u8)
}
#[doc = "Bit 7 - Sampling"]
#[inline(always)]
pub fn sam(&self) -> SamR {
SamR::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:3 - Time Segment 1"]
#[inline(always)]
pub fn tseg1(&mut self) -> Tseg1W<Btr1Spec> {
Tseg1W::new(self, 0)
}
#[doc = "Bits 4:6 - Time Segment 2"]
#[inline(always)]
pub fn tseg2(&mut self) -> Tseg2W<Btr1Spec> {
Tseg2W::new(self, 4)
}
#[doc = "Bit 7 - Sampling"]
#[inline(always)]
pub fn sam(&mut self) -> SamW<Btr1Spec> {
SamW::new(self, 7)
}
}
#[doc = "Bus Timing 1\n\nYou can [`read`](crate::Reg::read) this register and get [`btr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`btr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Btr1Spec;
impl crate::RegisterSpec for Btr1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`btr1::R`](R) reader structure"]
impl crate::Readable for Btr1Spec {}
#[doc = "`write(|w| ..)` method takes [`btr1::W`](W) writer structure"]
impl crate::Writable for Btr1Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets BTR1 to value 0"]
impl crate::Resettable for Btr1Spec {}
}
#[doc = "OCR (rw) register accessor: Output Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ocr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ocr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ocr`] module"]
#[doc(alias = "OCR")]
pub type Ocr = crate::Reg<ocr::OcrSpec>;
#[doc = "Output Control Register"]
pub mod ocr {
#[doc = "Register `OCR` reader"]
pub type R = crate::R<OcrSpec>;
#[doc = "Register `OCR` writer"]
pub type W = crate::W<OcrSpec>;
#[doc = "Output Control Register\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Ocr {
#[doc = "2: Normal Output Mode"]
NormalOutputMode = 2,
}
impl From<Ocr> for u8 {
#[inline(always)]
fn from(variant: Ocr) -> Self {
variant as _
}
}
impl crate::FieldSpec for Ocr {
type Ux = u8;
}
impl crate::IsEnum for Ocr {}
#[doc = "Field `OCR` reader - Output Control Register"]
pub type OcrR = crate::FieldReader<Ocr>;
impl OcrR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<Ocr> {
match self.bits {
2 => Some(Ocr::NormalOutputMode),
_ => None,
}
}
#[doc = "Normal Output Mode"]
#[inline(always)]
pub fn is_normal_output_mode(&self) -> bool {
*self == Ocr::NormalOutputMode
}
}
#[doc = "Field `OCR` writer - Output Control Register"]
pub type OcrW<'a, REG> = crate::FieldWriter<'a, REG, 2, Ocr>;
impl<'a, REG> OcrW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Normal Output Mode"]
#[inline(always)]
pub fn normal_output_mode(self) -> &'a mut crate::W<REG> {
self.variant(Ocr::NormalOutputMode)
}
}
impl R {
#[doc = "Bits 0:1 - Output Control Register"]
#[inline(always)]
pub fn ocr(&self) -> OcrR {
OcrR::new((self.bits & 3) as u8)
}
}
impl W {
#[doc = "Bits 0:1 - Output Control Register"]
#[inline(always)]
pub fn ocr(&mut self) -> OcrW<OcrSpec> {
OcrW::new(self, 0)
}
}
#[doc = "Output Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ocr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ocr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OcrSpec;
impl crate::RegisterSpec for OcrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ocr::R`](R) reader structure"]
impl crate::Readable for OcrSpec {}
#[doc = "`write(|w| ..)` method takes [`ocr::W`](W) writer structure"]
impl crate::Writable for OcrSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets OCR to value 0"]
impl crate::Resettable for OcrSpec {}
}
#[doc = "ALC (r) register accessor: Arbitration Lost Capture\n\nYou can [`read`](crate::Reg::read) this register and get [`alc::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@alc`] module"]
#[doc(alias = "ALC")]
pub type Alc = crate::Reg<alc::AlcSpec>;
#[doc = "Arbitration Lost Capture"]
pub mod alc {
#[doc = "Register `ALC` reader"]
pub type R = crate::R<AlcSpec>;
#[doc = "Field `ALC` reader - Arbitration Lost Capture"]
pub type AlcR = crate::FieldReader;
impl R {
#[doc = "Bits 0:4 - Arbitration Lost Capture"]
#[inline(always)]
pub fn alc(&self) -> AlcR {
AlcR::new((self.bits & 0x1f) as u8)
}
}
#[doc = "Arbitration Lost Capture\n\nYou can [`read`](crate::Reg::read) this register and get [`alc::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AlcSpec;
impl crate::RegisterSpec for AlcSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`alc::R`](R) reader structure"]
impl crate::Readable for AlcSpec {}
#[doc = "`reset()` method sets ALC to value 0"]
impl crate::Resettable for AlcSpec {}
}
#[doc = "ECC (r) register accessor: Error Code Capture\n\nYou can [`read`](crate::Reg::read) this register and get [`ecc::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ecc`] module"]
#[doc(alias = "ECC")]
pub type Ecc = crate::Reg<ecc::EccSpec>;
#[doc = "Error Code Capture"]
pub mod ecc {
#[doc = "Register `ECC` reader"]
pub type R = crate::R<EccSpec>;
#[doc = "Field `Segment` reader - Segment code"]
pub type SegmentR = crate::FieldReader;
#[doc = "When is error occured\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Direction {
#[doc = "0: TX"]
Tx = 0,
#[doc = "1: RX"]
Rx = 1,
}
impl From<Direction> for bool {
#[inline(always)]
fn from(variant: Direction) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `Direction` reader - When is error occured"]
pub type DirectionR = crate::BitReader<Direction>;
impl DirectionR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Direction {
match self.bits {
false => Direction::Tx,
true => Direction::Rx,
}
}
#[doc = "TX"]
#[inline(always)]
pub fn is_tx(&self) -> bool {
*self == Direction::Tx
}
#[doc = "RX"]
#[inline(always)]
pub fn is_rx(&self) -> bool {
*self == Direction::Rx
}
}
#[doc = "Error code\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Code {
#[doc = "0: Bit error"]
Biterror = 0,
#[doc = "1: Form error"]
Formerror = 1,
#[doc = "2: Stuff error"]
Stufferror = 2,
#[doc = "3: Other error"]
Othererror = 3,
}
impl From<Code> for u8 {
#[inline(always)]
fn from(variant: Code) -> Self {
variant as _
}
}
impl crate::FieldSpec for Code {
type Ux = u8;
}
impl crate::IsEnum for Code {}
#[doc = "Field `Code` reader - Error code"]
pub type CodeR = crate::FieldReader<Code>;
impl CodeR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Code {
match self.bits {
0 => Code::Biterror,
1 => Code::Formerror,
2 => Code::Stufferror,
3 => Code::Othererror,
_ => unreachable!(),
}
}
#[doc = "Bit error"]
#[inline(always)]
pub fn is_biterror(&self) -> bool {
*self == Code::Biterror
}
#[doc = "Form error"]
#[inline(always)]
pub fn is_formerror(&self) -> bool {
*self == Code::Formerror
}
#[doc = "Stuff error"]
#[inline(always)]
pub fn is_stufferror(&self) -> bool {
*self == Code::Stufferror
}
#[doc = "Other error"]
#[inline(always)]
pub fn is_othererror(&self) -> bool {
*self == Code::Othererror
}
}
impl R {
#[doc = "Bits 0:4 - Segment code"]
#[inline(always)]
pub fn segment(&self) -> SegmentR {
SegmentR::new((self.bits & 0x1f) as u8)
}
#[doc = "Bit 5 - When is error occured"]
#[inline(always)]
pub fn direction(&self) -> DirectionR {
DirectionR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bits 6:7 - Error code"]
#[inline(always)]
pub fn code(&self) -> CodeR {
CodeR::new(((self.bits >> 6) & 3) as u8)
}
}
#[doc = "Error Code Capture\n\nYou can [`read`](crate::Reg::read) this register and get [`ecc::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EccSpec;
impl crate::RegisterSpec for EccSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ecc::R`](R) reader structure"]
impl crate::Readable for EccSpec {}
#[doc = "`reset()` method sets ECC to value 0"]
impl crate::Resettable for EccSpec {}
}
#[doc = "EWLR (rw) register accessor: Error Warning Limit\n\nYou can [`read`](crate::Reg::read) this register and get [`ewlr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ewlr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ewlr`] module"]
#[doc(alias = "EWLR")]
pub type Ewlr = crate::Reg<ewlr::EwlrSpec>;
#[doc = "Error Warning Limit"]
pub mod ewlr {
#[doc = "Register `EWLR` reader"]
pub type R = crate::R<EwlrSpec>;
#[doc = "Register `EWLR` writer"]
pub type W = crate::W<EwlrSpec>;
#[doc = "Field `EWLR` reader - Error Warning Limit"]
pub type EwlrR = crate::FieldReader;
#[doc = "Field `EWLR` writer - Error Warning Limit"]
pub type EwlrW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:7 - Error Warning Limit"]
#[inline(always)]
pub fn ewlr(&self) -> EwlrR {
EwlrR::new((self.bits & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:7 - Error Warning Limit"]
#[inline(always)]
pub fn ewlr(&mut self) -> EwlrW<EwlrSpec> {
EwlrW::new(self, 0)
}
}
#[doc = "Error Warning Limit\n\nYou can [`read`](crate::Reg::read) this register and get [`ewlr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ewlr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EwlrSpec;
impl crate::RegisterSpec for EwlrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ewlr::R`](R) reader structure"]
impl crate::Readable for EwlrSpec {}
#[doc = "`write(|w| ..)` method takes [`ewlr::W`](W) writer structure"]
impl crate::Writable for EwlrSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets EWLR to value 0"]
impl crate::Resettable for EwlrSpec {}
}
#[doc = "RXERR (rw) register accessor: Receive Error Counter\n\nYou can [`read`](crate::Reg::read) this register and get [`rxerr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxerr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxerr`] module"]
#[doc(alias = "RXERR")]
pub type Rxerr = crate::Reg<rxerr::RxerrSpec>;
#[doc = "Receive Error Counter"]
pub mod rxerr {
#[doc = "Register `RXERR` reader"]
pub type R = crate::R<RxerrSpec>;
#[doc = "Register `RXERR` writer"]
pub type W = crate::W<RxerrSpec>;
#[doc = "Field `RXERR` reader - Receive Error Counter"]
pub type RxerrR = crate::FieldReader;
#[doc = "Field `RXERR` writer - Receive Error Counter"]
pub type RxerrW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:7 - Receive Error Counter"]
#[inline(always)]
pub fn rxerr(&self) -> RxerrR {
RxerrR::new((self.bits & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:7 - Receive Error Counter"]
#[inline(always)]
pub fn rxerr(&mut self) -> RxerrW<RxerrSpec> {
RxerrW::new(self, 0)
}
}
#[doc = "Receive Error Counter\n\nYou can [`read`](crate::Reg::read) this register and get [`rxerr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxerr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RxerrSpec;
impl crate::RegisterSpec for RxerrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rxerr::R`](R) reader structure"]
impl crate::Readable for RxerrSpec {}
#[doc = "`write(|w| ..)` method takes [`rxerr::W`](W) writer structure"]
impl crate::Writable for RxerrSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets RXERR to value 0"]
impl crate::Resettable for RxerrSpec {}
}
#[doc = "TXERR (rw) register accessor: Transmit Error Counter\n\nYou can [`read`](crate::Reg::read) this register and get [`txerr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txerr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txerr`] module"]
#[doc(alias = "TXERR")]
pub type Txerr = crate::Reg<txerr::TxerrSpec>;
#[doc = "Transmit Error Counter"]
pub mod txerr {
#[doc = "Register `TXERR` reader"]
pub type R = crate::R<TxerrSpec>;
#[doc = "Register `TXERR` writer"]
pub type W = crate::W<TxerrSpec>;
#[doc = "Field `TXERR` reader - Transmit Error Counter"]
pub type TxerrR = crate::FieldReader;
#[doc = "Field `TXERR` writer - Transmit Error Counter"]
pub type TxerrW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:7 - Transmit Error Counter"]
#[inline(always)]
pub fn txerr(&self) -> TxerrR {
TxerrR::new((self.bits & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:7 - Transmit Error Counter"]
#[inline(always)]
pub fn txerr(&mut self) -> TxerrW<TxerrSpec> {
TxerrW::new(self, 0)
}
}
#[doc = "Transmit Error Counter\n\nYou can [`read`](crate::Reg::read) this register and get [`txerr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txerr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TxerrSpec;
impl crate::RegisterSpec for TxerrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`txerr::R`](R) reader structure"]
impl crate::Readable for TxerrSpec {}
#[doc = "`write(|w| ..)` method takes [`txerr::W`](W) writer structure"]
impl crate::Writable for TxerrSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets TXERR to value 0"]
impl crate::Resettable for TxerrSpec {}
}
#[doc = "FRAME (rw) register accessor: Transfer Frame Information\n\nYou can [`read`](crate::Reg::read) this register and get [`frame::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`frame::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@frame`] module"]
#[doc(alias = "FRAME")]
pub type Frame = crate::Reg<frame::FrameSpec>;
#[doc = "Transfer Frame Information"]
pub mod frame {
#[doc = "Register `FRAME` reader"]
pub type R = crate::R<FrameSpec>;
#[doc = "Register `FRAME` writer"]
pub type W = crate::W<FrameSpec>;
#[doc = "Field `FRAME` reader - Transfer Frame Information"]
pub type FrameR = crate::FieldReader;
#[doc = "Field `FRAME` writer - Transfer Frame Information"]
pub type FrameW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:7 - Transfer Frame Information"]
#[inline(always)]
pub fn frame(&self) -> FrameR {
FrameR::new((self.bits & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:7 - Transfer Frame Information"]
#[inline(always)]
pub fn frame(&mut self) -> FrameW<FrameSpec> {
FrameW::new(self, 0)
}
}
#[doc = "Transfer Frame Information\n\nYou can [`read`](crate::Reg::read) this register and get [`frame::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`frame::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FrameSpec;
impl crate::RegisterSpec for FrameSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`frame::R`](R) reader structure"]
impl crate::Readable for FrameSpec {}
#[doc = "`write(|w| ..)` method takes [`frame::W`](W) writer structure"]
impl crate::Writable for FrameSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets FRAME to value 0"]
impl crate::Resettable for FrameSpec {}
}
#[doc = "ACR[0] (rw) register accessor: Acceptance Code Register\n\nYou can [`read`](crate::Reg::read) this register and get [`acr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`acr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@acr0`] module"]
#[doc(alias = "ACR[0]")]
pub type Acr0 = crate::Reg<acr0::Acr0Spec>;
#[doc = "Acceptance Code Register"]
pub mod acr0 {
#[doc = "Register `ACR[0]` reader"]
pub type R = crate::R<Acr0Spec>;
#[doc = "Register `ACR[0]` writer"]
pub type W = crate::W<Acr0Spec>;
#[doc = "Field `ACR[0]` reader - Acceptance Code Register 0"]
pub type Acr0R = crate::FieldReader;
#[doc = "Field `ACR[0]` writer - Acceptance Code Register 0"]
pub type Acr0W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:7 - Acceptance Code Register 0"]
#[inline(always)]
pub fn acr0(&self) -> Acr0R {
Acr0R::new((self.bits & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:7 - Acceptance Code Register 0"]
#[inline(always)]
pub fn acr0(&mut self) -> Acr0W<Acr0Spec> {
Acr0W::new(self, 0)
}
}
#[doc = "Acceptance Code Register\n\nYou can [`read`](crate::Reg::read) this register and get [`acr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`acr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Acr0Spec;
impl crate::RegisterSpec for Acr0Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`acr0::R`](R) reader structure"]
impl crate::Readable for Acr0Spec {}
#[doc = "`write(|w| ..)` method takes [`acr0::W`](W) writer structure"]
impl crate::Writable for Acr0Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ACR[0] to value 0"]
impl crate::Resettable for Acr0Spec {}
}
#[doc = "ACR[1] (rw) register accessor: Acceptance Code Register\n\nYou can [`read`](crate::Reg::read) this register and get [`acr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`acr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@acr1`] module"]
#[doc(alias = "ACR[1]")]
pub type Acr1 = crate::Reg<acr1::Acr1Spec>;
#[doc = "Acceptance Code Register"]
pub mod acr1 {
#[doc = "Register `ACR[1]` reader"]
pub type R = crate::R<Acr1Spec>;
#[doc = "Register `ACR[1]` writer"]
pub type W = crate::W<Acr1Spec>;
#[doc = "Field `ACR[1]` reader - Acceptance Code Register 1"]
pub type Acr1R = crate::FieldReader;
#[doc = "Field `ACR[1]` writer - Acceptance Code Register 1"]
pub type Acr1W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:7 - Acceptance Code Register 1"]
#[inline(always)]
pub fn acr1(&self) -> Acr1R {
Acr1R::new((self.bits & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:7 - Acceptance Code Register 1"]
#[inline(always)]
pub fn acr1(&mut self) -> Acr1W<Acr1Spec> {
Acr1W::new(self, 0)
}
}
#[doc = "Acceptance Code Register\n\nYou can [`read`](crate::Reg::read) this register and get [`acr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`acr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Acr1Spec;
impl crate::RegisterSpec for Acr1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`acr1::R`](R) reader structure"]
impl crate::Readable for Acr1Spec {}
#[doc = "`write(|w| ..)` method takes [`acr1::W`](W) writer structure"]
impl crate::Writable for Acr1Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ACR[1] to value 0"]
impl crate::Resettable for Acr1Spec {}
}
#[doc = "DATA[0] (rw) register accessor: Transfer Data Information\n\nYou can [`read`](crate::Reg::read) this register and get [`data0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data0`] module"]
#[doc(alias = "DATA[0]")]
pub type Data0 = crate::Reg<data0::Data0Spec>;
#[doc = "Transfer Data Information"]
pub mod data0 {
#[doc = "Register `DATA[0]` reader"]
pub type R = crate::R<Data0Spec>;
#[doc = "Register `DATA[0]` writer"]
pub type W = crate::W<Data0Spec>;
#[doc = "Field `DATA[0]` reader - Transfer Data Information 0"]
pub type Data0R = crate::FieldReader;
#[doc = "Field `DATA[0]` writer - Transfer Data Information 0"]
pub type Data0W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:7 - Transfer Data Information 0"]
#[inline(always)]
pub fn data0(&self) -> Data0R {
Data0R::new((self.bits & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:7 - Transfer Data Information 0"]
#[inline(always)]
pub fn data0(&mut self) -> Data0W<Data0Spec> {
Data0W::new(self, 0)
}
}
#[doc = "Transfer Data Information\n\nYou can [`read`](crate::Reg::read) this register and get [`data0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Data0Spec;
impl crate::RegisterSpec for Data0Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`data0::R`](R) reader structure"]
impl crate::Readable for Data0Spec {}
#[doc = "`write(|w| ..)` method takes [`data0::W`](W) writer structure"]
impl crate::Writable for Data0Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets DATA[0] to value 0"]
impl crate::Resettable for Data0Spec {}
}
#[doc = "ACR[2] (rw) register accessor: Acceptance Code Register\n\nYou can [`read`](crate::Reg::read) this register and get [`acr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`acr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@acr2`] module"]
#[doc(alias = "ACR[2]")]
pub type Acr2 = crate::Reg<acr2::Acr2Spec>;
#[doc = "Acceptance Code Register"]
pub mod acr2 {
#[doc = "Register `ACR[2]` reader"]
pub type R = crate::R<Acr2Spec>;
#[doc = "Register `ACR[2]` writer"]
pub type W = crate::W<Acr2Spec>;
#[doc = "Field `ACR[2]` reader - Acceptance Code Register 2"]
pub type Acr2R = crate::FieldReader;
#[doc = "Field `ACR[2]` writer - Acceptance Code Register 2"]
pub type Acr2W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:7 - Acceptance Code Register 2"]
#[inline(always)]
pub fn acr2(&self) -> Acr2R {
Acr2R::new((self.bits & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:7 - Acceptance Code Register 2"]
#[inline(always)]
pub fn acr2(&mut self) -> Acr2W<Acr2Spec> {
Acr2W::new(self, 0)
}
}
#[doc = "Acceptance Code Register\n\nYou can [`read`](crate::Reg::read) this register and get [`acr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`acr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Acr2Spec;
impl crate::RegisterSpec for Acr2Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`acr2::R`](R) reader structure"]
impl crate::Readable for Acr2Spec {}
#[doc = "`write(|w| ..)` method takes [`acr2::W`](W) writer structure"]
impl crate::Writable for Acr2Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ACR[2] to value 0"]
impl crate::Resettable for Acr2Spec {}
}
#[doc = "DATA[1] (rw) register accessor: Transfer Data Information\n\nYou can [`read`](crate::Reg::read) this register and get [`data1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data1`] module"]
#[doc(alias = "DATA[1]")]
pub type Data1 = crate::Reg<data1::Data1Spec>;
#[doc = "Transfer Data Information"]
pub mod data1 {
#[doc = "Register `DATA[1]` reader"]
pub type R = crate::R<Data1Spec>;
#[doc = "Register `DATA[1]` writer"]
pub type W = crate::W<Data1Spec>;
#[doc = "Field `DATA[1]` reader - Transfer Data Information 1"]
pub type Data1R = crate::FieldReader;
#[doc = "Field `DATA[1]` writer - Transfer Data Information 1"]
pub type Data1W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:7 - Transfer Data Information 1"]
#[inline(always)]
pub fn data1(&self) -> Data1R {
Data1R::new((self.bits & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:7 - Transfer Data Information 1"]
#[inline(always)]
pub fn data1(&mut self) -> Data1W<Data1Spec> {
Data1W::new(self, 0)
}
}
#[doc = "Transfer Data Information\n\nYou can [`read`](crate::Reg::read) this register and get [`data1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Data1Spec;
impl crate::RegisterSpec for Data1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`data1::R`](R) reader structure"]
impl crate::Readable for Data1Spec {}
#[doc = "`write(|w| ..)` method takes [`data1::W`](W) writer structure"]
impl crate::Writable for Data1Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets DATA[1] to value 0"]
impl crate::Resettable for Data1Spec {}
}
#[doc = "ACR[3] (rw) register accessor: Acceptance Code Register\n\nYou can [`read`](crate::Reg::read) this register and get [`acr3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`acr3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@acr3`] module"]
#[doc(alias = "ACR[3]")]
pub type Acr3 = crate::Reg<acr3::Acr3Spec>;
#[doc = "Acceptance Code Register"]
pub mod acr3 {
#[doc = "Register `ACR[3]` reader"]
pub type R = crate::R<Acr3Spec>;
#[doc = "Register `ACR[3]` writer"]
pub type W = crate::W<Acr3Spec>;
#[doc = "Field `ACR[3]` reader - Acceptance Code Register 3"]
pub type Acr3R = crate::FieldReader;
#[doc = "Field `ACR[3]` writer - Acceptance Code Register 3"]
pub type Acr3W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:7 - Acceptance Code Register 3"]
#[inline(always)]
pub fn acr3(&self) -> Acr3R {
Acr3R::new((self.bits & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:7 - Acceptance Code Register 3"]
#[inline(always)]
pub fn acr3(&mut self) -> Acr3W<Acr3Spec> {
Acr3W::new(self, 0)
}
}
#[doc = "Acceptance Code Register\n\nYou can [`read`](crate::Reg::read) this register and get [`acr3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`acr3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Acr3Spec;
impl crate::RegisterSpec for Acr3Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`acr3::R`](R) reader structure"]
impl crate::Readable for Acr3Spec {}
#[doc = "`write(|w| ..)` method takes [`acr3::W`](W) writer structure"]
impl crate::Writable for Acr3Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ACR[3] to value 0"]
impl crate::Resettable for Acr3Spec {}
}
#[doc = "DATA[2] (rw) register accessor: Transfer Data Information\n\nYou can [`read`](crate::Reg::read) this register and get [`data2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data2`] module"]
#[doc(alias = "DATA[2]")]
pub type Data2 = crate::Reg<data2::Data2Spec>;
#[doc = "Transfer Data Information"]
pub mod data2 {
#[doc = "Register `DATA[2]` reader"]
pub type R = crate::R<Data2Spec>;
#[doc = "Register `DATA[2]` writer"]
pub type W = crate::W<Data2Spec>;
#[doc = "Field `DATA[2]` reader - Transfer Data Information 2"]
pub type Data2R = crate::FieldReader;
#[doc = "Field `DATA[2]` writer - Transfer Data Information 2"]
pub type Data2W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:7 - Transfer Data Information 2"]
#[inline(always)]
pub fn data2(&self) -> Data2R {
Data2R::new((self.bits & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:7 - Transfer Data Information 2"]
#[inline(always)]
pub fn data2(&mut self) -> Data2W<Data2Spec> {
Data2W::new(self, 0)
}
}
#[doc = "Transfer Data Information\n\nYou can [`read`](crate::Reg::read) this register and get [`data2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Data2Spec;
impl crate::RegisterSpec for Data2Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`data2::R`](R) reader structure"]
impl crate::Readable for Data2Spec {}
#[doc = "`write(|w| ..)` method takes [`data2::W`](W) writer structure"]
impl crate::Writable for Data2Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets DATA[2] to value 0"]
impl crate::Resettable for Data2Spec {}
}
#[doc = "AMR[0] (rw) register accessor: Acceptance Mask Register\n\nYou can [`read`](crate::Reg::read) this register and get [`amr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`amr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@amr0`] module"]
#[doc(alias = "AMR[0]")]
pub type Amr0 = crate::Reg<amr0::Amr0Spec>;
#[doc = "Acceptance Mask Register"]
pub mod amr0 {
#[doc = "Register `AMR[0]` reader"]
pub type R = crate::R<Amr0Spec>;
#[doc = "Register `AMR[0]` writer"]
pub type W = crate::W<Amr0Spec>;
#[doc = "Field `AMR[0]` reader - Acceptance Mask Register 0"]
pub type Amr0R = crate::FieldReader;
#[doc = "Field `AMR[0]` writer - Acceptance Mask Register 0"]
pub type Amr0W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:7 - Acceptance Mask Register 0"]
#[inline(always)]
pub fn amr0(&self) -> Amr0R {
Amr0R::new((self.bits & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:7 - Acceptance Mask Register 0"]
#[inline(always)]
pub fn amr0(&mut self) -> Amr0W<Amr0Spec> {
Amr0W::new(self, 0)
}
}
#[doc = "Acceptance Mask Register\n\nYou can [`read`](crate::Reg::read) this register and get [`amr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`amr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Amr0Spec;
impl crate::RegisterSpec for Amr0Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`amr0::R`](R) reader structure"]
impl crate::Readable for Amr0Spec {}
#[doc = "`write(|w| ..)` method takes [`amr0::W`](W) writer structure"]
impl crate::Writable for Amr0Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets AMR[0] to value 0"]
impl crate::Resettable for Amr0Spec {}
}
#[doc = "DATA[3] (rw) register accessor: Transfer Data Information\n\nYou can [`read`](crate::Reg::read) this register and get [`data3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data3`] module"]
#[doc(alias = "DATA[3]")]
pub type Data3 = crate::Reg<data3::Data3Spec>;
#[doc = "Transfer Data Information"]
pub mod data3 {
#[doc = "Register `DATA[3]` reader"]
pub type R = crate::R<Data3Spec>;
#[doc = "Register `DATA[3]` writer"]
pub type W = crate::W<Data3Spec>;
#[doc = "Field `DATA[3]` reader - Transfer Data Information 3"]
pub type Data3R = crate::FieldReader;
#[doc = "Field `DATA[3]` writer - Transfer Data Information 3"]
pub type Data3W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:7 - Transfer Data Information 3"]
#[inline(always)]
pub fn data3(&self) -> Data3R {
Data3R::new((self.bits & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:7 - Transfer Data Information 3"]
#[inline(always)]
pub fn data3(&mut self) -> Data3W<Data3Spec> {
Data3W::new(self, 0)
}
}
#[doc = "Transfer Data Information\n\nYou can [`read`](crate::Reg::read) this register and get [`data3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Data3Spec;
impl crate::RegisterSpec for Data3Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`data3::R`](R) reader structure"]
impl crate::Readable for Data3Spec {}
#[doc = "`write(|w| ..)` method takes [`data3::W`](W) writer structure"]
impl crate::Writable for Data3Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets DATA[3] to value 0"]
impl crate::Resettable for Data3Spec {}
}
#[doc = "AMR[1] (rw) register accessor: Acceptance Mask Register\n\nYou can [`read`](crate::Reg::read) this register and get [`amr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`amr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@amr1`] module"]
#[doc(alias = "AMR[1]")]
pub type Amr1 = crate::Reg<amr1::Amr1Spec>;
#[doc = "Acceptance Mask Register"]
pub mod amr1 {
#[doc = "Register `AMR[1]` reader"]
pub type R = crate::R<Amr1Spec>;
#[doc = "Register `AMR[1]` writer"]
pub type W = crate::W<Amr1Spec>;
#[doc = "Field `AMR[1]` reader - Acceptance Mask Register 1"]
pub type Amr1R = crate::FieldReader;
#[doc = "Field `AMR[1]` writer - Acceptance Mask Register 1"]
pub type Amr1W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:7 - Acceptance Mask Register 1"]
#[inline(always)]
pub fn amr1(&self) -> Amr1R {
Amr1R::new((self.bits & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:7 - Acceptance Mask Register 1"]
#[inline(always)]
pub fn amr1(&mut self) -> Amr1W<Amr1Spec> {
Amr1W::new(self, 0)
}
}
#[doc = "Acceptance Mask Register\n\nYou can [`read`](crate::Reg::read) this register and get [`amr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`amr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Amr1Spec;
impl crate::RegisterSpec for Amr1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`amr1::R`](R) reader structure"]
impl crate::Readable for Amr1Spec {}
#[doc = "`write(|w| ..)` method takes [`amr1::W`](W) writer structure"]
impl crate::Writable for Amr1Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets AMR[1] to value 0"]
impl crate::Resettable for Amr1Spec {}
}
#[doc = "DATA[4] (rw) register accessor: Transfer Data Information\n\nYou can [`read`](crate::Reg::read) this register and get [`data4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data4`] module"]
#[doc(alias = "DATA[4]")]
pub type Data4 = crate::Reg<data4::Data4Spec>;
#[doc = "Transfer Data Information"]
pub mod data4 {
#[doc = "Register `DATA[4]` reader"]
pub type R = crate::R<Data4Spec>;
#[doc = "Register `DATA[4]` writer"]
pub type W = crate::W<Data4Spec>;
#[doc = "Field `DATA[4]` reader - Transfer Data Information 4"]
pub type Data4R = crate::FieldReader;
#[doc = "Field `DATA[4]` writer - Transfer Data Information 4"]
pub type Data4W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:7 - Transfer Data Information 4"]
#[inline(always)]
pub fn data4(&self) -> Data4R {
Data4R::new((self.bits & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:7 - Transfer Data Information 4"]
#[inline(always)]
pub fn data4(&mut self) -> Data4W<Data4Spec> {
Data4W::new(self, 0)
}
}
#[doc = "Transfer Data Information\n\nYou can [`read`](crate::Reg::read) this register and get [`data4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Data4Spec;
impl crate::RegisterSpec for Data4Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`data4::R`](R) reader structure"]
impl crate::Readable for Data4Spec {}
#[doc = "`write(|w| ..)` method takes [`data4::W`](W) writer structure"]
impl crate::Writable for Data4Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets DATA[4] to value 0"]
impl crate::Resettable for Data4Spec {}
}
#[doc = "AMR[2] (rw) register accessor: Acceptance Mask Register\n\nYou can [`read`](crate::Reg::read) this register and get [`amr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`amr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@amr2`] module"]
#[doc(alias = "AMR[2]")]
pub type Amr2 = crate::Reg<amr2::Amr2Spec>;
#[doc = "Acceptance Mask Register"]
pub mod amr2 {
#[doc = "Register `AMR[2]` reader"]
pub type R = crate::R<Amr2Spec>;
#[doc = "Register `AMR[2]` writer"]
pub type W = crate::W<Amr2Spec>;
#[doc = "Field `AMR[2]` reader - Acceptance Mask Register 2"]
pub type Amr2R = crate::FieldReader;
#[doc = "Field `AMR[2]` writer - Acceptance Mask Register 2"]
pub type Amr2W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:7 - Acceptance Mask Register 2"]
#[inline(always)]
pub fn amr2(&self) -> Amr2R {
Amr2R::new((self.bits & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:7 - Acceptance Mask Register 2"]
#[inline(always)]
pub fn amr2(&mut self) -> Amr2W<Amr2Spec> {
Amr2W::new(self, 0)
}
}
#[doc = "Acceptance Mask Register\n\nYou can [`read`](crate::Reg::read) this register and get [`amr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`amr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Amr2Spec;
impl crate::RegisterSpec for Amr2Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`amr2::R`](R) reader structure"]
impl crate::Readable for Amr2Spec {}
#[doc = "`write(|w| ..)` method takes [`amr2::W`](W) writer structure"]
impl crate::Writable for Amr2Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets AMR[2] to value 0"]
impl crate::Resettable for Amr2Spec {}
}
#[doc = "DATA[5] (rw) register accessor: Transfer Data Information\n\nYou can [`read`](crate::Reg::read) this register and get [`data5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data5`] module"]
#[doc(alias = "DATA[5]")]
pub type Data5 = crate::Reg<data5::Data5Spec>;
#[doc = "Transfer Data Information"]
pub mod data5 {
#[doc = "Register `DATA[5]` reader"]
pub type R = crate::R<Data5Spec>;
#[doc = "Register `DATA[5]` writer"]
pub type W = crate::W<Data5Spec>;
#[doc = "Field `DATA[5]` reader - Transfer Data Information 5"]
pub type Data5R = crate::FieldReader;
#[doc = "Field `DATA[5]` writer - Transfer Data Information 5"]
pub type Data5W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:7 - Transfer Data Information 5"]
#[inline(always)]
pub fn data5(&self) -> Data5R {
Data5R::new((self.bits & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:7 - Transfer Data Information 5"]
#[inline(always)]
pub fn data5(&mut self) -> Data5W<Data5Spec> {
Data5W::new(self, 0)
}
}
#[doc = "Transfer Data Information\n\nYou can [`read`](crate::Reg::read) this register and get [`data5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Data5Spec;
impl crate::RegisterSpec for Data5Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`data5::R`](R) reader structure"]
impl crate::Readable for Data5Spec {}
#[doc = "`write(|w| ..)` method takes [`data5::W`](W) writer structure"]
impl crate::Writable for Data5Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets DATA[5] to value 0"]
impl crate::Resettable for Data5Spec {}
}
#[doc = "AMR[3] (rw) register accessor: Acceptance Mask Register\n\nYou can [`read`](crate::Reg::read) this register and get [`amr3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`amr3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@amr3`] module"]
#[doc(alias = "AMR[3]")]
pub type Amr3 = crate::Reg<amr3::Amr3Spec>;
#[doc = "Acceptance Mask Register"]
pub mod amr3 {
#[doc = "Register `AMR[3]` reader"]
pub type R = crate::R<Amr3Spec>;
#[doc = "Register `AMR[3]` writer"]
pub type W = crate::W<Amr3Spec>;
#[doc = "Field `AMR[3]` reader - Acceptance Mask Register 3"]
pub type Amr3R = crate::FieldReader;
#[doc = "Field `AMR[3]` writer - Acceptance Mask Register 3"]
pub type Amr3W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:7 - Acceptance Mask Register 3"]
#[inline(always)]
pub fn amr3(&self) -> Amr3R {
Amr3R::new((self.bits & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:7 - Acceptance Mask Register 3"]
#[inline(always)]
pub fn amr3(&mut self) -> Amr3W<Amr3Spec> {
Amr3W::new(self, 0)
}
}
#[doc = "Acceptance Mask Register\n\nYou can [`read`](crate::Reg::read) this register and get [`amr3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`amr3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Amr3Spec;
impl crate::RegisterSpec for Amr3Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`amr3::R`](R) reader structure"]
impl crate::Readable for Amr3Spec {}
#[doc = "`write(|w| ..)` method takes [`amr3::W`](W) writer structure"]
impl crate::Writable for Amr3Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets AMR[3] to value 0"]
impl crate::Resettable for Amr3Spec {}
}
#[doc = "DATA[6] (rw) register accessor: Transfer Data Information\n\nYou can [`read`](crate::Reg::read) this register and get [`data6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data6`] module"]
#[doc(alias = "DATA[6]")]
pub type Data6 = crate::Reg<data6::Data6Spec>;
#[doc = "Transfer Data Information"]
pub mod data6 {
#[doc = "Register `DATA[6]` reader"]
pub type R = crate::R<Data6Spec>;
#[doc = "Register `DATA[6]` writer"]
pub type W = crate::W<Data6Spec>;
#[doc = "Field `DATA[6]` reader - Transfer Data Information 6"]
pub type Data6R = crate::FieldReader;
#[doc = "Field `DATA[6]` writer - Transfer Data Information 6"]
pub type Data6W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:7 - Transfer Data Information 6"]
#[inline(always)]
pub fn data6(&self) -> Data6R {
Data6R::new((self.bits & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:7 - Transfer Data Information 6"]
#[inline(always)]
pub fn data6(&mut self) -> Data6W<Data6Spec> {
Data6W::new(self, 0)
}
}
#[doc = "Transfer Data Information\n\nYou can [`read`](crate::Reg::read) this register and get [`data6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Data6Spec;
impl crate::RegisterSpec for Data6Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`data6::R`](R) reader structure"]
impl crate::Readable for Data6Spec {}
#[doc = "`write(|w| ..)` method takes [`data6::W`](W) writer structure"]
impl crate::Writable for Data6Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets DATA[6] to value 0"]
impl crate::Resettable for Data6Spec {}
}
#[doc = "DATA[7] (rw) register accessor: Transfer Data Information\n\nYou can [`read`](crate::Reg::read) this register and get [`data7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data7`] module"]
#[doc(alias = "DATA[7]")]
pub type Data7 = crate::Reg<data7::Data7Spec>;
#[doc = "Transfer Data Information"]
pub mod data7 {
#[doc = "Register `DATA[7]` reader"]
pub type R = crate::R<Data7Spec>;
#[doc = "Register `DATA[7]` writer"]
pub type W = crate::W<Data7Spec>;
#[doc = "Field `DATA[7]` reader - Transfer Data Information 7"]
pub type Data7R = crate::FieldReader;
#[doc = "Field `DATA[7]` writer - Transfer Data Information 7"]
pub type Data7W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:7 - Transfer Data Information 7"]
#[inline(always)]
pub fn data7(&self) -> Data7R {
Data7R::new((self.bits & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:7 - Transfer Data Information 7"]
#[inline(always)]
pub fn data7(&mut self) -> Data7W<Data7Spec> {
Data7W::new(self, 0)
}
}
#[doc = "Transfer Data Information\n\nYou can [`read`](crate::Reg::read) this register and get [`data7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Data7Spec;
impl crate::RegisterSpec for Data7Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`data7::R`](R) reader structure"]
impl crate::Readable for Data7Spec {}
#[doc = "`write(|w| ..)` method takes [`data7::W`](W) writer structure"]
impl crate::Writable for Data7Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets DATA[7] to value 0"]
impl crate::Resettable for Data7Spec {}
}
#[doc = "DATA[8] (rw) register accessor: Transfer Data Information\n\nYou can [`read`](crate::Reg::read) this register and get [`data8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data8`] module"]
#[doc(alias = "DATA[8]")]
pub type Data8 = crate::Reg<data8::Data8Spec>;
#[doc = "Transfer Data Information"]
pub mod data8 {
#[doc = "Register `DATA[8]` reader"]
pub type R = crate::R<Data8Spec>;
#[doc = "Register `DATA[8]` writer"]
pub type W = crate::W<Data8Spec>;
#[doc = "Field `DATA[8]` reader - Transfer Data Information 8"]
pub type Data8R = crate::FieldReader;
#[doc = "Field `DATA[8]` writer - Transfer Data Information 8"]
pub type Data8W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:7 - Transfer Data Information 8"]
#[inline(always)]
pub fn data8(&self) -> Data8R {
Data8R::new((self.bits & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:7 - Transfer Data Information 8"]
#[inline(always)]
pub fn data8(&mut self) -> Data8W<Data8Spec> {
Data8W::new(self, 0)
}
}
#[doc = "Transfer Data Information\n\nYou can [`read`](crate::Reg::read) this register and get [`data8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Data8Spec;
impl crate::RegisterSpec for Data8Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`data8::R`](R) reader structure"]
impl crate::Readable for Data8Spec {}
#[doc = "`write(|w| ..)` method takes [`data8::W`](W) writer structure"]
impl crate::Writable for Data8Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets DATA[8] to value 0"]
impl crate::Resettable for Data8Spec {}
}
#[doc = "DATA[9] (rw) register accessor: Transfer Data Information\n\nYou can [`read`](crate::Reg::read) this register and get [`data9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data9`] module"]
#[doc(alias = "DATA[9]")]
pub type Data9 = crate::Reg<data9::Data9Spec>;
#[doc = "Transfer Data Information"]
pub mod data9 {
#[doc = "Register `DATA[9]` reader"]
pub type R = crate::R<Data9Spec>;
#[doc = "Register `DATA[9]` writer"]
pub type W = crate::W<Data9Spec>;
#[doc = "Field `DATA[9]` reader - Transfer Data Information 9"]
pub type Data9R = crate::FieldReader;
#[doc = "Field `DATA[9]` writer - Transfer Data Information 9"]
pub type Data9W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:7 - Transfer Data Information 9"]
#[inline(always)]
pub fn data9(&self) -> Data9R {
Data9R::new((self.bits & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:7 - Transfer Data Information 9"]
#[inline(always)]
pub fn data9(&mut self) -> Data9W<Data9Spec> {
Data9W::new(self, 0)
}
}
#[doc = "Transfer Data Information\n\nYou can [`read`](crate::Reg::read) this register and get [`data9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Data9Spec;
impl crate::RegisterSpec for Data9Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`data9::R`](R) reader structure"]
impl crate::Readable for Data9Spec {}
#[doc = "`write(|w| ..)` method takes [`data9::W`](W) writer structure"]
impl crate::Writable for Data9Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets DATA[9] to value 0"]
impl crate::Resettable for Data9Spec {}
}
#[doc = "DATA[10] (rw) register accessor: Transfer Data Information\n\nYou can [`read`](crate::Reg::read) this register and get [`data10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data10`] module"]
#[doc(alias = "DATA[10]")]
pub type Data10 = crate::Reg<data10::Data10Spec>;
#[doc = "Transfer Data Information"]
pub mod data10 {
#[doc = "Register `DATA[10]` reader"]
pub type R = crate::R<Data10Spec>;
#[doc = "Register `DATA[10]` writer"]
pub type W = crate::W<Data10Spec>;
#[doc = "Field `DATA[10]` reader - Transfer Data Information 10"]
pub type Data10R = crate::FieldReader;
#[doc = "Field `DATA[10]` writer - Transfer Data Information 10"]
pub type Data10W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:7 - Transfer Data Information 10"]
#[inline(always)]
pub fn data10(&self) -> Data10R {
Data10R::new((self.bits & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:7 - Transfer Data Information 10"]
#[inline(always)]
pub fn data10(&mut self) -> Data10W<Data10Spec> {
Data10W::new(self, 0)
}
}
#[doc = "Transfer Data Information\n\nYou can [`read`](crate::Reg::read) this register and get [`data10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Data10Spec;
impl crate::RegisterSpec for Data10Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`data10::R`](R) reader structure"]
impl crate::Readable for Data10Spec {}
#[doc = "`write(|w| ..)` method takes [`data10::W`](W) writer structure"]
impl crate::Writable for Data10Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets DATA[10] to value 0"]
impl crate::Resettable for Data10Spec {}
}
#[doc = "DATA[11] (rw) register accessor: Transfer Data Information\n\nYou can [`read`](crate::Reg::read) this register and get [`data11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data11`] module"]
#[doc(alias = "DATA[11]")]
pub type Data11 = crate::Reg<data11::Data11Spec>;
#[doc = "Transfer Data Information"]
pub mod data11 {
#[doc = "Register `DATA[11]` reader"]
pub type R = crate::R<Data11Spec>;
#[doc = "Register `DATA[11]` writer"]
pub type W = crate::W<Data11Spec>;
#[doc = "Field `DATA[11]` reader - Transfer Data Information 11"]
pub type Data11R = crate::FieldReader;
#[doc = "Field `DATA[11]` writer - Transfer Data Information 11"]
pub type Data11W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:7 - Transfer Data Information 11"]
#[inline(always)]
pub fn data11(&self) -> Data11R {
Data11R::new((self.bits & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:7 - Transfer Data Information 11"]
#[inline(always)]
pub fn data11(&mut self) -> Data11W<Data11Spec> {
Data11W::new(self, 0)
}
}
#[doc = "Transfer Data Information\n\nYou can [`read`](crate::Reg::read) this register and get [`data11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Data11Spec;
impl crate::RegisterSpec for Data11Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`data11::R`](R) reader structure"]
impl crate::Readable for Data11Spec {}
#[doc = "`write(|w| ..)` method takes [`data11::W`](W) writer structure"]
impl crate::Writable for Data11Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets DATA[11] to value 0"]
impl crate::Resettable for Data11Spec {}
}
#[doc = "RMC (r) register accessor: Receive Message Counter\n\nYou can [`read`](crate::Reg::read) this register and get [`rmc::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rmc`] module"]
#[doc(alias = "RMC")]
pub type Rmc = crate::Reg<rmc::RmcSpec>;
#[doc = "Receive Message Counter"]
pub mod rmc {
#[doc = "Register `RMC` reader"]
pub type R = crate::R<RmcSpec>;
#[doc = "Field `RMC` reader - Receive Message Counter"]
pub type RmcR = crate::FieldReader;
impl R {
#[doc = "Bits 0:4 - Receive Message Counter"]
#[inline(always)]
pub fn rmc(&self) -> RmcR {
RmcR::new((self.bits & 0x1f) as u8)
}
}
#[doc = "Receive Message Counter\n\nYou can [`read`](crate::Reg::read) this register and get [`rmc::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RmcSpec;
impl crate::RegisterSpec for RmcSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rmc::R`](R) reader structure"]
impl crate::Readable for RmcSpec {}
#[doc = "`reset()` method sets RMC to value 0"]
impl crate::Resettable for RmcSpec {}
}
#[doc = "RBSA (rw) register accessor: Receive Buffer Start Address\n\nYou can [`read`](crate::Reg::read) this register and get [`rbsa::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rbsa::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rbsa`] module"]
#[doc(alias = "RBSA")]
pub type Rbsa = crate::Reg<rbsa::RbsaSpec>;
#[doc = "Receive Buffer Start Address"]
pub mod rbsa {
#[doc = "Register `RBSA` reader"]
pub type R = crate::R<RbsaSpec>;
#[doc = "Register `RBSA` writer"]
pub type W = crate::W<RbsaSpec>;
#[doc = "Field `RBSA` reader - Receive Buffer Start Address"]
pub type RbsaR = crate::FieldReader;
#[doc = "Field `RBSA` writer - Receive Buffer Start Address"]
pub type RbsaW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
impl R {
#[doc = "Bits 0:5 - Receive Buffer Start Address"]
#[inline(always)]
pub fn rbsa(&self) -> RbsaR {
RbsaR::new((self.bits & 0x3f) as u8)
}
}
impl W {
#[doc = "Bits 0:5 - Receive Buffer Start Address"]
#[inline(always)]
pub fn rbsa(&mut self) -> RbsaW<RbsaSpec> {
RbsaW::new(self, 0)
}
}
#[doc = "Receive Buffer Start Address\n\nYou can [`read`](crate::Reg::read) this register and get [`rbsa::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rbsa::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RbsaSpec;
impl crate::RegisterSpec for RbsaSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rbsa::R`](R) reader structure"]
impl crate::Readable for RbsaSpec {}
#[doc = "`write(|w| ..)` method takes [`rbsa::W`](W) writer structure"]
impl crate::Writable for RbsaSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets RBSA to value 0"]
impl crate::Resettable for RbsaSpec {}
}
#[doc = "TX_FRAME (r) register accessor: Transmit Frame Information\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_frame::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_frame`] module"]
#[doc(alias = "TX_FRAME")]
pub type TxFrame = crate::Reg<tx_frame::TxFrameSpec>;
#[doc = "Transmit Frame Information"]
pub mod tx_frame {
#[doc = "Register `TX_FRAME` reader"]
pub type R = crate::R<TxFrameSpec>;
#[doc = "Field `TX_FRAME` reader - Transmit Frame Information"]
pub type TxFrameR = crate::FieldReader;
impl R {
#[doc = "Bits 0:7 - Transmit Frame Information"]
#[inline(always)]
pub fn tx_frame(&self) -> TxFrameR {
TxFrameR::new((self.bits & 0xff) as u8)
}
}
#[doc = "Transmit Frame Information\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_frame::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TxFrameSpec;
impl crate::RegisterSpec for TxFrameSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`tx_frame::R`](R) reader structure"]
impl crate::Readable for TxFrameSpec {}
#[doc = "`reset()` method sets TX_FRAME to value 0"]
impl crate::Resettable for TxFrameSpec {}
}
#[doc = "TX_DATA[0] (r) register accessor: Transmit Data Information\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_data0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_data0`] module"]
#[doc(alias = "TX_DATA[0]")]
pub type TxData0 = crate::Reg<tx_data0::TxData0Spec>;
#[doc = "Transmit Data Information"]
pub mod tx_data0 {
#[doc = "Register `TX_DATA[0]` reader"]
pub type R = crate::R<TxData0Spec>;
#[doc = "Field `TX_DATA[0]` reader - Transmit Data Information 0"]
pub type TxData0R = crate::FieldReader;
impl R {
#[doc = "Bits 0:7 - Transmit Data Information 0"]
#[inline(always)]
pub fn tx_data0(&self) -> TxData0R {
TxData0R::new((self.bits & 0xff) as u8)
}
}
#[doc = "Transmit Data Information\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_data0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TxData0Spec;
impl crate::RegisterSpec for TxData0Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`tx_data0::R`](R) reader structure"]
impl crate::Readable for TxData0Spec {}
#[doc = "`reset()` method sets TX_DATA[0] to value 0"]
impl crate::Resettable for TxData0Spec {}
}
#[doc = "TX_DATA[1] (r) register accessor: Transmit Data Information\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_data1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_data1`] module"]
#[doc(alias = "TX_DATA[1]")]
pub type TxData1 = crate::Reg<tx_data1::TxData1Spec>;
#[doc = "Transmit Data Information"]
pub mod tx_data1 {
#[doc = "Register `TX_DATA[1]` reader"]
pub type R = crate::R<TxData1Spec>;
#[doc = "Field `TX_DATA[1]` reader - Transmit Data Information 1"]
pub type TxData1R = crate::FieldReader;
impl R {
#[doc = "Bits 0:7 - Transmit Data Information 1"]
#[inline(always)]
pub fn tx_data1(&self) -> TxData1R {
TxData1R::new((self.bits & 0xff) as u8)
}
}
#[doc = "Transmit Data Information\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_data1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TxData1Spec;
impl crate::RegisterSpec for TxData1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`tx_data1::R`](R) reader structure"]
impl crate::Readable for TxData1Spec {}
#[doc = "`reset()` method sets TX_DATA[1] to value 0"]
impl crate::Resettable for TxData1Spec {}
}
#[doc = "TX_DATA[2] (r) register accessor: Transmit Data Information\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_data2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_data2`] module"]
#[doc(alias = "TX_DATA[2]")]
pub type TxData2 = crate::Reg<tx_data2::TxData2Spec>;
#[doc = "Transmit Data Information"]
pub mod tx_data2 {
#[doc = "Register `TX_DATA[2]` reader"]
pub type R = crate::R<TxData2Spec>;
#[doc = "Field `TX_DATA[2]` reader - Transmit Data Information 2"]
pub type TxData2R = crate::FieldReader;
impl R {
#[doc = "Bits 0:7 - Transmit Data Information 2"]
#[inline(always)]
pub fn tx_data2(&self) -> TxData2R {
TxData2R::new((self.bits & 0xff) as u8)
}
}
#[doc = "Transmit Data Information\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_data2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TxData2Spec;
impl crate::RegisterSpec for TxData2Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`tx_data2::R`](R) reader structure"]
impl crate::Readable for TxData2Spec {}
#[doc = "`reset()` method sets TX_DATA[2] to value 0"]
impl crate::Resettable for TxData2Spec {}
}
#[doc = "TX_DATA[3] (r) register accessor: Transmit Data Information\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_data3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_data3`] module"]
#[doc(alias = "TX_DATA[3]")]
pub type TxData3 = crate::Reg<tx_data3::TxData3Spec>;
#[doc = "Transmit Data Information"]
pub mod tx_data3 {
#[doc = "Register `TX_DATA[3]` reader"]
pub type R = crate::R<TxData3Spec>;
#[doc = "Field `TX_DATA[3]` reader - Transmit Data Information 3"]
pub type TxData3R = crate::FieldReader;
impl R {
#[doc = "Bits 0:7 - Transmit Data Information 3"]
#[inline(always)]
pub fn tx_data3(&self) -> TxData3R {
TxData3R::new((self.bits & 0xff) as u8)
}
}
#[doc = "Transmit Data Information\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_data3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TxData3Spec;
impl crate::RegisterSpec for TxData3Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`tx_data3::R`](R) reader structure"]
impl crate::Readable for TxData3Spec {}
#[doc = "`reset()` method sets TX_DATA[3] to value 0"]
impl crate::Resettable for TxData3Spec {}
}
#[doc = "TX_DATA[4] (r) register accessor: Transmit Data Information\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_data4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_data4`] module"]
#[doc(alias = "TX_DATA[4]")]
pub type TxData4 = crate::Reg<tx_data4::TxData4Spec>;
#[doc = "Transmit Data Information"]
pub mod tx_data4 {
#[doc = "Register `TX_DATA[4]` reader"]
pub type R = crate::R<TxData4Spec>;
#[doc = "Field `TX_DATA[4]` reader - Transmit Data Information 4"]
pub type TxData4R = crate::FieldReader;
impl R {
#[doc = "Bits 0:7 - Transmit Data Information 4"]
#[inline(always)]
pub fn tx_data4(&self) -> TxData4R {
TxData4R::new((self.bits & 0xff) as u8)
}
}
#[doc = "Transmit Data Information\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_data4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TxData4Spec;
impl crate::RegisterSpec for TxData4Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`tx_data4::R`](R) reader structure"]
impl crate::Readable for TxData4Spec {}
#[doc = "`reset()` method sets TX_DATA[4] to value 0"]
impl crate::Resettable for TxData4Spec {}
}
#[doc = "TX_DATA[5] (r) register accessor: Transmit Data Information\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_data5::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_data5`] module"]
#[doc(alias = "TX_DATA[5]")]
pub type TxData5 = crate::Reg<tx_data5::TxData5Spec>;
#[doc = "Transmit Data Information"]
pub mod tx_data5 {
#[doc = "Register `TX_DATA[5]` reader"]
pub type R = crate::R<TxData5Spec>;
#[doc = "Field `TX_DATA[5]` reader - Transmit Data Information 5"]
pub type TxData5R = crate::FieldReader;
impl R {
#[doc = "Bits 0:7 - Transmit Data Information 5"]
#[inline(always)]
pub fn tx_data5(&self) -> TxData5R {
TxData5R::new((self.bits & 0xff) as u8)
}
}
#[doc = "Transmit Data Information\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_data5::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TxData5Spec;
impl crate::RegisterSpec for TxData5Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`tx_data5::R`](R) reader structure"]
impl crate::Readable for TxData5Spec {}
#[doc = "`reset()` method sets TX_DATA[5] to value 0"]
impl crate::Resettable for TxData5Spec {}
}
#[doc = "TX_DATA[6] (r) register accessor: Transmit Data Information\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_data6::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_data6`] module"]
#[doc(alias = "TX_DATA[6]")]
pub type TxData6 = crate::Reg<tx_data6::TxData6Spec>;
#[doc = "Transmit Data Information"]
pub mod tx_data6 {
#[doc = "Register `TX_DATA[6]` reader"]
pub type R = crate::R<TxData6Spec>;
#[doc = "Field `TX_DATA[6]` reader - Transmit Data Information 6"]
pub type TxData6R = crate::FieldReader;
impl R {
#[doc = "Bits 0:7 - Transmit Data Information 6"]
#[inline(always)]
pub fn tx_data6(&self) -> TxData6R {
TxData6R::new((self.bits & 0xff) as u8)
}
}
#[doc = "Transmit Data Information\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_data6::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TxData6Spec;
impl crate::RegisterSpec for TxData6Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`tx_data6::R`](R) reader structure"]
impl crate::Readable for TxData6Spec {}
#[doc = "`reset()` method sets TX_DATA[6] to value 0"]
impl crate::Resettable for TxData6Spec {}
}
#[doc = "TX_DATA[7] (r) register accessor: Transmit Data Information\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_data7::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_data7`] module"]
#[doc(alias = "TX_DATA[7]")]
pub type TxData7 = crate::Reg<tx_data7::TxData7Spec>;
#[doc = "Transmit Data Information"]
pub mod tx_data7 {
#[doc = "Register `TX_DATA[7]` reader"]
pub type R = crate::R<TxData7Spec>;
#[doc = "Field `TX_DATA[7]` reader - Transmit Data Information 7"]
pub type TxData7R = crate::FieldReader;
impl R {
#[doc = "Bits 0:7 - Transmit Data Information 7"]
#[inline(always)]
pub fn tx_data7(&self) -> TxData7R {
TxData7R::new((self.bits & 0xff) as u8)
}
}
#[doc = "Transmit Data Information\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_data7::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TxData7Spec;
impl crate::RegisterSpec for TxData7Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`tx_data7::R`](R) reader structure"]
impl crate::Readable for TxData7Spec {}
#[doc = "`reset()` method sets TX_DATA[7] to value 0"]
impl crate::Resettable for TxData7Spec {}
}
#[doc = "TX_DATA[8] (r) register accessor: Transmit Data Information\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_data8::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_data8`] module"]
#[doc(alias = "TX_DATA[8]")]
pub type TxData8 = crate::Reg<tx_data8::TxData8Spec>;
#[doc = "Transmit Data Information"]
pub mod tx_data8 {
#[doc = "Register `TX_DATA[8]` reader"]
pub type R = crate::R<TxData8Spec>;
#[doc = "Field `TX_DATA[8]` reader - Transmit Data Information 8"]
pub type TxData8R = crate::FieldReader;
impl R {
#[doc = "Bits 0:7 - Transmit Data Information 8"]
#[inline(always)]
pub fn tx_data8(&self) -> TxData8R {
TxData8R::new((self.bits & 0xff) as u8)
}
}
#[doc = "Transmit Data Information\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_data8::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TxData8Spec;
impl crate::RegisterSpec for TxData8Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`tx_data8::R`](R) reader structure"]
impl crate::Readable for TxData8Spec {}
#[doc = "`reset()` method sets TX_DATA[8] to value 0"]
impl crate::Resettable for TxData8Spec {}
}
#[doc = "TX_DATA[9] (r) register accessor: Transmit Data Information\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_data9::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_data9`] module"]
#[doc(alias = "TX_DATA[9]")]
pub type TxData9 = crate::Reg<tx_data9::TxData9Spec>;
#[doc = "Transmit Data Information"]
pub mod tx_data9 {
#[doc = "Register `TX_DATA[9]` reader"]
pub type R = crate::R<TxData9Spec>;
#[doc = "Field `TX_DATA[9]` reader - Transmit Data Information 9"]
pub type TxData9R = crate::FieldReader;
impl R {
#[doc = "Bits 0:7 - Transmit Data Information 9"]
#[inline(always)]
pub fn tx_data9(&self) -> TxData9R {
TxData9R::new((self.bits & 0xff) as u8)
}
}
#[doc = "Transmit Data Information\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_data9::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TxData9Spec;
impl crate::RegisterSpec for TxData9Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`tx_data9::R`](R) reader structure"]
impl crate::Readable for TxData9Spec {}
#[doc = "`reset()` method sets TX_DATA[9] to value 0"]
impl crate::Resettable for TxData9Spec {}
}
#[doc = "TX_DATA[10] (r) register accessor: Transmit Data Information\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_data10::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_data10`] module"]
#[doc(alias = "TX_DATA[10]")]
pub type TxData10 = crate::Reg<tx_data10::TxData10Spec>;
#[doc = "Transmit Data Information"]
pub mod tx_data10 {
#[doc = "Register `TX_DATA[10]` reader"]
pub type R = crate::R<TxData10Spec>;
#[doc = "Field `TX_DATA[10]` reader - Transmit Data Information 10"]
pub type TxData10R = crate::FieldReader;
impl R {
#[doc = "Bits 0:7 - Transmit Data Information 10"]
#[inline(always)]
pub fn tx_data10(&self) -> TxData10R {
TxData10R::new((self.bits & 0xff) as u8)
}
}
#[doc = "Transmit Data Information\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_data10::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TxData10Spec;
impl crate::RegisterSpec for TxData10Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`tx_data10::R`](R) reader structure"]
impl crate::Readable for TxData10Spec {}
#[doc = "`reset()` method sets TX_DATA[10] to value 0"]
impl crate::Resettable for TxData10Spec {}
}
#[doc = "TX_DATA[11] (r) register accessor: Transmit Data Information\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_data11::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_data11`] module"]
#[doc(alias = "TX_DATA[11]")]
pub type TxData11 = crate::Reg<tx_data11::TxData11Spec>;
#[doc = "Transmit Data Information"]
pub mod tx_data11 {
#[doc = "Register `TX_DATA[11]` reader"]
pub type R = crate::R<TxData11Spec>;
#[doc = "Field `TX_DATA[11]` reader - Transmit Data Information 11"]
pub type TxData11R = crate::FieldReader;
impl R {
#[doc = "Bits 0:7 - Transmit Data Information 11"]
#[inline(always)]
pub fn tx_data11(&self) -> TxData11R {
TxData11R::new((self.bits & 0xff) as u8)
}
}
#[doc = "Transmit Data Information\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_data11::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TxData11Spec;
impl crate::RegisterSpec for TxData11Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`tx_data11::R`](R) reader structure"]
impl crate::Readable for TxData11Spec {}
#[doc = "`reset()` method sets TX_DATA[11] to value 0"]
impl crate::Resettable for TxData11Spec {}
}
}
#[doc = "I2C registers"]
pub type I2c0 = crate::Periph<i2c0::RegisterBlock, 0x4002_b000>;
impl core::fmt::Debug for I2c0 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("I2c0").finish()
}
}
#[doc = "I2C registers"]
pub mod i2c0 {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
prerlo: Prerlo,
prerhi: Prerhi,
ctr: Ctr,
_reserved_3_rxr: [u8; 0x04],
_reserved_4_cr: [u8; 0x04],
}
impl RegisterBlock {
#[doc = "0x00 - Prescaler register lo-byte"]
#[inline(always)]
pub const fn prerlo(&self) -> &Prerlo {
&self.prerlo
}
#[doc = "0x04 - Prescaler register hi-byte"]
#[inline(always)]
pub const fn prerhi(&self) -> &Prerhi {
&self.prerhi
}
#[doc = "0x08 - Control register"]
#[inline(always)]
pub const fn ctr(&self) -> &Ctr {
&self.ctr
}
#[doc = "0x0c - Transmit register"]
#[inline(always)]
pub const fn txr(&self) -> &Txr {
unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(12).cast() }
}
#[doc = "0x0c - Receive register"]
#[inline(always)]
pub const fn rxr(&self) -> &Rxr {
unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(12).cast() }
}
#[doc = "0x10 - Status register"]
#[inline(always)]
pub const fn sr(&self) -> &Sr {
unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(16).cast() }
}
#[doc = "0x10 - Command register"]
#[inline(always)]
pub const fn cr(&self) -> &Cr {
unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(16).cast() }
}
}
#[doc = "PRERLO (rw) register accessor: Prescaler register lo-byte\n\nYou can [`read`](crate::Reg::read) this register and get [`prerlo::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`prerlo::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@prerlo`] module"]
#[doc(alias = "PRERLO")]
pub type Prerlo = crate::Reg<prerlo::PrerloSpec>;
#[doc = "Prescaler register lo-byte"]
pub mod prerlo {
#[doc = "Register `PRERLO` reader"]
pub type R = crate::R<PrerloSpec>;
#[doc = "Register `PRERLO` writer"]
pub type W = crate::W<PrerloSpec>;
#[doc = "Field `PRERLO` reader - Prescaler register lo-byte"]
pub type PrerloR = crate::FieldReader;
#[doc = "Field `PRERLO` writer - Prescaler register lo-byte"]
pub type PrerloW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:7 - Prescaler register lo-byte"]
#[inline(always)]
pub fn prerlo(&self) -> PrerloR {
PrerloR::new((self.bits & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:7 - Prescaler register lo-byte"]
#[inline(always)]
pub fn prerlo(&mut self) -> PrerloW<PrerloSpec> {
PrerloW::new(self, 0)
}
}
#[doc = "Prescaler register lo-byte\n\nYou can [`read`](crate::Reg::read) this register and get [`prerlo::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`prerlo::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PrerloSpec;
impl crate::RegisterSpec for PrerloSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`prerlo::R`](R) reader structure"]
impl crate::Readable for PrerloSpec {}
#[doc = "`write(|w| ..)` method takes [`prerlo::W`](W) writer structure"]
impl crate::Writable for PrerloSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets PRERLO to value 0"]
impl crate::Resettable for PrerloSpec {}
}
#[doc = "PRERHI (rw) register accessor: Prescaler register hi-byte\n\nYou can [`read`](crate::Reg::read) this register and get [`prerhi::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`prerhi::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@prerhi`] module"]
#[doc(alias = "PRERHI")]
pub type Prerhi = crate::Reg<prerhi::PrerhiSpec>;
#[doc = "Prescaler register hi-byte"]
pub mod prerhi {
#[doc = "Register `PRERHI` reader"]
pub type R = crate::R<PrerhiSpec>;
#[doc = "Register `PRERHI` writer"]
pub type W = crate::W<PrerhiSpec>;
#[doc = "Field `PRERHI` reader - Prescaler register hi-byte"]
pub type PrerhiR = crate::FieldReader;
#[doc = "Field `PRERHI` writer - Prescaler register hi-byte"]
pub type PrerhiW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:7 - Prescaler register hi-byte"]
#[inline(always)]
pub fn prerhi(&self) -> PrerhiR {
PrerhiR::new((self.bits & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:7 - Prescaler register hi-byte"]
#[inline(always)]
pub fn prerhi(&mut self) -> PrerhiW<PrerhiSpec> {
PrerhiW::new(self, 0)
}
}
#[doc = "Prescaler register hi-byte\n\nYou can [`read`](crate::Reg::read) this register and get [`prerhi::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`prerhi::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PrerhiSpec;
impl crate::RegisterSpec for PrerhiSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`prerhi::R`](R) reader structure"]
impl crate::Readable for PrerhiSpec {}
#[doc = "`write(|w| ..)` method takes [`prerhi::W`](W) writer structure"]
impl crate::Writable for PrerhiSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets PRERHI to value 0"]
impl crate::Resettable for PrerhiSpec {}
}
#[doc = "CTR (rw) register accessor: Control register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctr`] module"]
#[doc(alias = "CTR")]
pub type Ctr = crate::Reg<ctr::CtrSpec>;
#[doc = "Control register"]
pub mod ctr {
#[doc = "Register `CTR` reader"]
pub type R = crate::R<CtrSpec>;
#[doc = "Register `CTR` writer"]
pub type W = crate::W<CtrSpec>;
#[doc = "Field `IEN` reader - Interrupt enable"]
pub type IenR = crate::BitReader;
#[doc = "Field `IEN` writer - Interrupt enable"]
pub type IenW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EN` reader - Core enable"]
pub type EnR = crate::BitReader;
#[doc = "Field `EN` writer - Core enable"]
pub type EnW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 6 - Interrupt enable"]
#[inline(always)]
pub fn ien(&self) -> IenR {
IenR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Core enable"]
#[inline(always)]
pub fn en(&self) -> EnR {
EnR::new(((self.bits >> 7) & 1) != 0)
}
}
impl W {
#[doc = "Bit 6 - Interrupt enable"]
#[inline(always)]
pub fn ien(&mut self) -> IenW<CtrSpec> {
IenW::new(self, 6)
}
#[doc = "Bit 7 - Core enable"]
#[inline(always)]
pub fn en(&mut self) -> EnW<CtrSpec> {
EnW::new(self, 7)
}
}
#[doc = "Control register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CtrSpec;
impl crate::RegisterSpec for CtrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ctr::R`](R) reader structure"]
impl crate::Readable for CtrSpec {}
#[doc = "`write(|w| ..)` method takes [`ctr::W`](W) writer structure"]
impl crate::Writable for CtrSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets CTR to value 0"]
impl crate::Resettable for CtrSpec {}
}
#[doc = "RXR (r) register accessor: Receive register\n\nYou can [`read`](crate::Reg::read) this register and get [`rxr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxr`] module"]
#[doc(alias = "RXR")]
pub type Rxr = crate::Reg<rxr::RxrSpec>;
#[doc = "Receive register"]
pub mod rxr {
#[doc = "Register `RXR` reader"]
pub type R = crate::R<RxrSpec>;
#[doc = "Field `RXR` reader - Receive register"]
pub type RxrR = crate::FieldReader;
impl R {
#[doc = "Bits 0:7 - Receive register"]
#[inline(always)]
pub fn rxr(&self) -> RxrR {
RxrR::new((self.bits & 0xff) as u8)
}
}
#[doc = "Receive register\n\nYou can [`read`](crate::Reg::read) this register and get [`rxr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RxrSpec;
impl crate::RegisterSpec for RxrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rxr::R`](R) reader structure"]
impl crate::Readable for RxrSpec {}
#[doc = "`reset()` method sets RXR to value 0"]
impl crate::Resettable for RxrSpec {}
}
#[doc = "TXR (w) register accessor: Transmit register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txr`] module"]
#[doc(alias = "TXR")]
pub type Txr = crate::Reg<txr::TxrSpec>;
#[doc = "Transmit register"]
pub mod txr {
#[doc = "Register `TXR` writer"]
pub type W = crate::W<TxrSpec>;
#[doc = "Field `TXR` writer - Transmit register"]
pub type TxrW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl W {
#[doc = "Bits 0:7 - Transmit register"]
#[inline(always)]
pub fn txr(&mut self) -> TxrW<TxrSpec> {
TxrW::new(self, 0)
}
}
#[doc = "Transmit register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TxrSpec;
impl crate::RegisterSpec for TxrSpec {
type Ux = u32;
}
#[doc = "`write(|w| ..)` method takes [`txr::W`](W) writer structure"]
impl crate::Writable for TxrSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets TXR to value 0"]
impl crate::Resettable for TxrSpec {}
}
#[doc = "CR (w) register accessor: Command register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr`] module"]
#[doc(alias = "CR")]
pub type Cr = crate::Reg<cr::CrSpec>;
#[doc = "Command register"]
pub mod cr {
#[doc = "Register `CR` writer"]
pub type W = crate::W<CrSpec>;
#[doc = "Field `IACK` writer - Interrupt acknowledge"]
pub type IackW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `NACK` writer - When a receiver, send ACK(0) or NACK(1)"]
pub type NackW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `WR` writer - Write to slave"]
pub type WrW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RD` writer - Read from slave"]
pub type RdW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `STO` writer - Generate stop condition"]
pub type StoW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `STA` writer - Generate (repeated) start condition"]
pub type StaW<'a, REG> = crate::BitWriter<'a, REG>;
impl W {
#[doc = "Bit 0 - Interrupt acknowledge"]
#[inline(always)]
pub fn iack(&mut self) -> IackW<CrSpec> {
IackW::new(self, 0)
}
#[doc = "Bit 3 - When a receiver, send ACK(0) or NACK(1)"]
#[inline(always)]
pub fn nack(&mut self) -> NackW<CrSpec> {
NackW::new(self, 3)
}
#[doc = "Bit 4 - Write to slave"]
#[inline(always)]
pub fn wr(&mut self) -> WrW<CrSpec> {
WrW::new(self, 4)
}
#[doc = "Bit 5 - Read from slave"]
#[inline(always)]
pub fn rd(&mut self) -> RdW<CrSpec> {
RdW::new(self, 5)
}
#[doc = "Bit 6 - Generate stop condition"]
#[inline(always)]
pub fn sto(&mut self) -> StoW<CrSpec> {
StoW::new(self, 6)
}
#[doc = "Bit 7 - Generate (repeated) start condition"]
#[inline(always)]
pub fn sta(&mut self) -> StaW<CrSpec> {
StaW::new(self, 7)
}
}
#[doc = "Command register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CrSpec;
impl crate::RegisterSpec for CrSpec {
type Ux = u32;
}
#[doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"]
impl crate::Writable for CrSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets CR to value 0"]
impl crate::Resettable for CrSpec {}
}
#[doc = "SR (r) register accessor: Status register\n\nYou can [`read`](crate::Reg::read) this register and get [`sr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sr`] module"]
#[doc(alias = "SR")]
pub type Sr = crate::Reg<sr::SrSpec>;
#[doc = "Status register"]
pub mod sr {
#[doc = "Register `SR` reader"]
pub type R = crate::R<SrSpec>;
#[doc = "Field `IF` reader - Interrupt flag. Set when one byte transfer is done or arbitration lost"]
pub type IfR = crate::BitReader;
#[doc = "Field `TIP` reader - Transfer in progress"]
pub type TipR = crate::BitReader;
#[doc = "Field `AL` reader - Arbitration lost"]
pub type AlR = crate::BitReader;
#[doc = "Field `BUSY` reader - I2C bus busy"]
pub type BusyR = crate::BitReader;
#[doc = "Received acknowledge from slave\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum RxAck {
#[doc = "0: ACK"]
Ack = 0,
#[doc = "1: NACK"]
Nack = 1,
}
impl From<RxAck> for bool {
#[inline(always)]
fn from(variant: RxAck) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `RxACK` reader - Received acknowledge from slave"]
pub type RxAckR = crate::BitReader<RxAck>;
impl RxAckR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> RxAck {
match self.bits {
false => RxAck::Ack,
true => RxAck::Nack,
}
}
#[doc = "ACK"]
#[inline(always)]
pub fn is_ack(&self) -> bool {
*self == RxAck::Ack
}
#[doc = "NACK"]
#[inline(always)]
pub fn is_nack(&self) -> bool {
*self == RxAck::Nack
}
}
impl R {
#[doc = "Bit 0 - Interrupt flag. Set when one byte transfer is done or arbitration lost"]
#[inline(always)]
pub fn if_(&self) -> IfR {
IfR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Transfer in progress"]
#[inline(always)]
pub fn tip(&self) -> TipR {
TipR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 5 - Arbitration lost"]
#[inline(always)]
pub fn al(&self) -> AlR {
AlR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - I2C bus busy"]
#[inline(always)]
pub fn busy(&self) -> BusyR {
BusyR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Received acknowledge from slave"]
#[inline(always)]
pub fn rx_ack(&self) -> RxAckR {
RxAckR::new(((self.bits >> 7) & 1) != 0)
}
}
#[doc = "Status register\n\nYou can [`read`](crate::Reg::read) this register and get [`sr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SrSpec;
impl crate::RegisterSpec for SrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`sr::R`](R) reader structure"]
impl crate::Readable for SrSpec {}
#[doc = "`reset()` method sets SR to value 0"]
impl crate::Resettable for SrSpec {}
}
}
#[doc = "I2C registers"]
pub type I2c1 = crate::Periph<i2c0::RegisterBlock, 0x4002_c000>;
impl core::fmt::Debug for I2c1 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("I2c1").finish()
}
}
#[doc = "I2C registers"]
pub use self::i2c0 as i2c1;
#[doc = "DMAC registers"]
pub type Dmac0 = crate::Periph<dmac0::RegisterBlock, 0x4100_0000>;
impl core::fmt::Debug for Dmac0 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Dmac0").finish()
}
}
#[doc = "DMAC registers"]
pub mod dmac0 {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
int_status: IntStatus,
int_tcstatus: IntTcstatus,
int_tcclear: IntTcclear,
int_error_status: IntErrorStatus,
int_error_clear: IntErrorClear,
raw_int_tcstatus: RawIntTcstatus,
raw_int_error_status: RawIntErrorStatus,
enabled_channels: EnabledChannels,
soft_breq: SoftBreq,
soft_sreq: SoftSreq,
soft_lbreq: SoftLbreq,
soft_sbreq: SoftSbreq,
dmac_configuration: DmacConfiguration,
sync: Sync,
_reserved14: [u8; 0xc8],
channel: (),
}
impl RegisterBlock {
#[doc = "0x00 - Interrupt Status Register"]
#[inline(always)]
pub const fn int_status(&self) -> &IntStatus {
&self.int_status
}
#[doc = "0x04 - Interrupt Terminal Count Status Register"]
#[inline(always)]
pub const fn int_tcstatus(&self) -> &IntTcstatus {
&self.int_tcstatus
}
#[doc = "0x08 - Interrupt Terminal Count Clear Register"]
#[inline(always)]
pub const fn int_tcclear(&self) -> &IntTcclear {
&self.int_tcclear
}
#[doc = "0x0c - Interrupt Error Status Register"]
#[inline(always)]
pub const fn int_error_status(&self) -> &IntErrorStatus {
&self.int_error_status
}
#[doc = "0x10 - Interrupt Error Clear Register"]
#[inline(always)]
pub const fn int_error_clear(&self) -> &IntErrorClear {
&self.int_error_clear
}
#[doc = "0x14 - Raw Interrupt Terminal Count Status Register"]
#[inline(always)]
pub const fn raw_int_tcstatus(&self) -> &RawIntTcstatus {
&self.raw_int_tcstatus
}
#[doc = "0x18 - Raw Error Interrupt Status Register"]
#[inline(always)]
pub const fn raw_int_error_status(&self) -> &RawIntErrorStatus {
&self.raw_int_error_status
}
#[doc = "0x1c - Enabled Channel Register"]
#[inline(always)]
pub const fn enabled_channels(&self) -> &EnabledChannels {
&self.enabled_channels
}
#[doc = "0x20 - Software Burst Request Register"]
#[inline(always)]
pub const fn soft_breq(&self) -> &SoftBreq {
&self.soft_breq
}
#[doc = "0x24 - Software Single Request Register"]
#[inline(always)]
pub const fn soft_sreq(&self) -> &SoftSreq {
&self.soft_sreq
}
#[doc = "0x28 - Software Last Burst Request Register"]
#[inline(always)]
pub const fn soft_lbreq(&self) -> &SoftLbreq {
&self.soft_lbreq
}
#[doc = "0x2c - Software Last Single Request Register"]
#[inline(always)]
pub const fn soft_sbreq(&self) -> &SoftSbreq {
&self.soft_sbreq
}
#[doc = "0x30 - Configuration Register"]
#[inline(always)]
pub const fn dmac_configuration(&self) -> &DmacConfiguration {
&self.dmac_configuration
}
#[doc = "0x34 - Synchronization Register"]
#[inline(always)]
pub const fn sync(&self) -> &Sync {
&self.sync
}
#[doc = "0x100..0x1a0 - Channel Registers"]
#[inline(always)]
pub const fn channel(&self, n: usize) -> &Channel {
#[allow(clippy::no_effect)]
[(); 8][n];
unsafe {
&*core::ptr::from_ref(self)
.cast::<u8>()
.add(256)
.add(32 * n)
.cast()
}
}
#[doc = "Iterator for array of:"]
#[doc = "0x100..0x1a0 - Channel Registers"]
#[inline(always)]
pub fn channel_iter(&self) -> impl Iterator<Item = &Channel> {
(0..8).map(move |n| unsafe {
&*core::ptr::from_ref(self)
.cast::<u8>()
.add(256)
.add(32 * n)
.cast()
})
}
}
#[doc = "Channel Registers"]
pub use self::channel::Channel;
#[doc = r"Cluster"]
#[doc = "Channel Registers"]
pub mod channel {
#[repr(C)]
#[doc = "Channel Registers"]
pub struct Channel {
src_addr: SrcAddr,
dst_addr: DstAddr,
lli: Lli,
control: Control,
configuration: Configuration,
}
impl Channel {
#[doc = "0x00 - Channel Source Address Register"]
#[inline(always)]
pub const fn src_addr(&self) -> &SrcAddr {
&self.src_addr
}
#[doc = "0x04 - Channel Destination Address Register"]
#[inline(always)]
pub const fn dst_addr(&self) -> &DstAddr {
&self.dst_addr
}
#[doc = "0x08 - Channel Linked List Item Register"]
#[inline(always)]
pub const fn lli(&self) -> &Lli {
&self.lli
}
#[doc = "0x0c - Channel Control Register"]
#[inline(always)]
pub const fn control(&self) -> &Control {
&self.control
}
#[doc = "0x10 - Channel Configuration Register"]
#[inline(always)]
pub const fn configuration(&self) -> &Configuration {
&self.configuration
}
}
#[doc = "SrcAddr (rw) register accessor: Channel Source Address Register\n\nYou can [`read`](crate::Reg::read) this register and get [`src_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`src_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@src_addr`] module"]
pub type SrcAddr = crate::Reg<src_addr::SrcAddrSpec>;
#[doc = "Channel Source Address Register"]
pub mod src_addr {
#[doc = "Register `SrcAddr` reader"]
pub type R = crate::R<SrcAddrSpec>;
#[doc = "Register `SrcAddr` writer"]
pub type W = crate::W<SrcAddrSpec>;
#[doc = "Field `SrcAddr` reader - SrcAddr"]
pub type SrcAddrR = crate::FieldReader<u32>;
#[doc = "Field `SrcAddr` writer - SrcAddr"]
pub type SrcAddrW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - SrcAddr"]
#[inline(always)]
pub fn src_addr(&self) -> SrcAddrR {
SrcAddrR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - SrcAddr"]
#[inline(always)]
pub fn src_addr(&mut self) -> SrcAddrW<SrcAddrSpec> {
SrcAddrW::new(self, 0)
}
}
#[doc = "Channel Source Address Register\n\nYou can [`read`](crate::Reg::read) this register and get [`src_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`src_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SrcAddrSpec;
impl crate::RegisterSpec for SrcAddrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`src_addr::R`](R) reader structure"]
impl crate::Readable for SrcAddrSpec {}
#[doc = "`write(|w| ..)` method takes [`src_addr::W`](W) writer structure"]
impl crate::Writable for SrcAddrSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets SrcAddr to value 0"]
impl crate::Resettable for SrcAddrSpec {}
}
#[doc = "DstAddr (rw) register accessor: Channel Destination Address Register\n\nYou can [`read`](crate::Reg::read) this register and get [`dst_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dst_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dst_addr`] module"]
pub type DstAddr = crate::Reg<dst_addr::DstAddrSpec>;
#[doc = "Channel Destination Address Register"]
pub mod dst_addr {
#[doc = "Register `DstAddr` reader"]
pub type R = crate::R<DstAddrSpec>;
#[doc = "Register `DstAddr` writer"]
pub type W = crate::W<DstAddrSpec>;
#[doc = "Field `DstAddr` reader - DstAddr"]
pub type DstAddrR = crate::FieldReader<u32>;
#[doc = "Field `DstAddr` writer - DstAddr"]
pub type DstAddrW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - DstAddr"]
#[inline(always)]
pub fn dst_addr(&self) -> DstAddrR {
DstAddrR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - DstAddr"]
#[inline(always)]
pub fn dst_addr(&mut self) -> DstAddrW<DstAddrSpec> {
DstAddrW::new(self, 0)
}
}
#[doc = "Channel Destination Address Register\n\nYou can [`read`](crate::Reg::read) this register and get [`dst_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dst_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DstAddrSpec;
impl crate::RegisterSpec for DstAddrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`dst_addr::R`](R) reader structure"]
impl crate::Readable for DstAddrSpec {}
#[doc = "`write(|w| ..)` method takes [`dst_addr::W`](W) writer structure"]
impl crate::Writable for DstAddrSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets DstAddr to value 0"]
impl crate::Resettable for DstAddrSpec {}
}
#[doc = "LLI (rw) register accessor: Channel Linked List Item Register\n\nYou can [`read`](crate::Reg::read) this register and get [`lli::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lli::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lli`] module"]
#[doc(alias = "LLI")]
pub type Lli = crate::Reg<lli::LliSpec>;
#[doc = "Channel Linked List Item Register"]
pub mod lli {
#[doc = "Register `LLI` reader"]
pub type R = crate::R<LliSpec>;
#[doc = "Register `LLI` writer"]
pub type W = crate::W<LliSpec>;
#[doc = "Field `LLI` reader - LLI"]
pub type LliR = crate::FieldReader<u32>;
#[doc = "Field `LLI` writer - LLI"]
pub type LliW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - LLI"]
#[inline(always)]
pub fn lli(&self) -> LliR {
LliR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - LLI"]
#[inline(always)]
pub fn lli(&mut self) -> LliW<LliSpec> {
LliW::new(self, 0)
}
}
#[doc = "Channel Linked List Item Register\n\nYou can [`read`](crate::Reg::read) this register and get [`lli::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lli::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct LliSpec;
impl crate::RegisterSpec for LliSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`lli::R`](R) reader structure"]
impl crate::Readable for LliSpec {}
#[doc = "`write(|w| ..)` method takes [`lli::W`](W) writer structure"]
impl crate::Writable for LliSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets LLI to value 0"]
impl crate::Resettable for LliSpec {}
}
#[doc = "Control (rw) register accessor: Channel Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`control::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`control::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@control`] module"]
pub type Control = crate::Reg<control::ControlSpec>;
#[doc = "Channel Control Register"]
pub mod control {
#[doc = "Register `Control` reader"]
pub type R = crate::R<ControlSpec>;
#[doc = "Register `Control` writer"]
pub type W = crate::W<ControlSpec>;
#[doc = "Field `TransferSize` reader - Transfer size"]
pub type TransferSizeR = crate::FieldReader<u16>;
#[doc = "Field `TransferSize` writer - Transfer size"]
pub type TransferSizeW<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
#[doc = "Source burst size\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Sbsize {
#[doc = "0: 1"]
_1 = 0,
#[doc = "1: 4"]
_4 = 1,
#[doc = "2: 8"]
_8 = 2,
#[doc = "3: 16"]
_16 = 3,
#[doc = "4: 32"]
_32 = 4,
#[doc = "5: 64"]
_64 = 5,
#[doc = "6: 128"]
_128 = 6,
#[doc = "7: 256"]
_256 = 7,
}
impl From<Sbsize> for u8 {
#[inline(always)]
fn from(variant: Sbsize) -> Self {
variant as _
}
}
impl crate::FieldSpec for Sbsize {
type Ux = u8;
}
impl crate::IsEnum for Sbsize {}
#[doc = "Field `SBSize` reader - Source burst size"]
pub type SbsizeR = crate::FieldReader<Sbsize>;
impl SbsizeR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Sbsize {
match self.bits {
0 => Sbsize::_1,
1 => Sbsize::_4,
2 => Sbsize::_8,
3 => Sbsize::_16,
4 => Sbsize::_32,
5 => Sbsize::_64,
6 => Sbsize::_128,
7 => Sbsize::_256,
_ => unreachable!(),
}
}
#[doc = "1"]
#[inline(always)]
pub fn is_1(&self) -> bool {
*self == Sbsize::_1
}
#[doc = "4"]
#[inline(always)]
pub fn is_4(&self) -> bool {
*self == Sbsize::_4
}
#[doc = "8"]
#[inline(always)]
pub fn is_8(&self) -> bool {
*self == Sbsize::_8
}
#[doc = "16"]
#[inline(always)]
pub fn is_16(&self) -> bool {
*self == Sbsize::_16
}
#[doc = "32"]
#[inline(always)]
pub fn is_32(&self) -> bool {
*self == Sbsize::_32
}
#[doc = "64"]
#[inline(always)]
pub fn is_64(&self) -> bool {
*self == Sbsize::_64
}
#[doc = "128"]
#[inline(always)]
pub fn is_128(&self) -> bool {
*self == Sbsize::_128
}
#[doc = "256"]
#[inline(always)]
pub fn is_256(&self) -> bool {
*self == Sbsize::_256
}
}
#[doc = "Field `SBSize` writer - Source burst size"]
pub type SbsizeW<'a, REG> = crate::FieldWriter<'a, REG, 3, Sbsize, crate::Safe>;
impl<'a, REG> SbsizeW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "1"]
#[inline(always)]
pub fn _1(self) -> &'a mut crate::W<REG> {
self.variant(Sbsize::_1)
}
#[doc = "4"]
#[inline(always)]
pub fn _4(self) -> &'a mut crate::W<REG> {
self.variant(Sbsize::_4)
}
#[doc = "8"]
#[inline(always)]
pub fn _8(self) -> &'a mut crate::W<REG> {
self.variant(Sbsize::_8)
}
#[doc = "16"]
#[inline(always)]
pub fn _16(self) -> &'a mut crate::W<REG> {
self.variant(Sbsize::_16)
}
#[doc = "32"]
#[inline(always)]
pub fn _32(self) -> &'a mut crate::W<REG> {
self.variant(Sbsize::_32)
}
#[doc = "64"]
#[inline(always)]
pub fn _64(self) -> &'a mut crate::W<REG> {
self.variant(Sbsize::_64)
}
#[doc = "128"]
#[inline(always)]
pub fn _128(self) -> &'a mut crate::W<REG> {
self.variant(Sbsize::_128)
}
#[doc = "256"]
#[inline(always)]
pub fn _256(self) -> &'a mut crate::W<REG> {
self.variant(Sbsize::_256)
}
}
#[doc = "Destination burst size\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Dbsize {
#[doc = "0: 1"]
_1 = 0,
#[doc = "1: 4"]
_4 = 1,
#[doc = "2: 8"]
_8 = 2,
#[doc = "3: 16"]
_16 = 3,
#[doc = "4: 32"]
_32 = 4,
#[doc = "5: 64"]
_64 = 5,
#[doc = "6: 128"]
_128 = 6,
#[doc = "7: 256"]
_256 = 7,
}
impl From<Dbsize> for u8 {
#[inline(always)]
fn from(variant: Dbsize) -> Self {
variant as _
}
}
impl crate::FieldSpec for Dbsize {
type Ux = u8;
}
impl crate::IsEnum for Dbsize {}
#[doc = "Field `DBSize` reader - Destination burst size"]
pub type DbsizeR = crate::FieldReader<Dbsize>;
impl DbsizeR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Dbsize {
match self.bits {
0 => Dbsize::_1,
1 => Dbsize::_4,
2 => Dbsize::_8,
3 => Dbsize::_16,
4 => Dbsize::_32,
5 => Dbsize::_64,
6 => Dbsize::_128,
7 => Dbsize::_256,
_ => unreachable!(),
}
}
#[doc = "1"]
#[inline(always)]
pub fn is_1(&self) -> bool {
*self == Dbsize::_1
}
#[doc = "4"]
#[inline(always)]
pub fn is_4(&self) -> bool {
*self == Dbsize::_4
}
#[doc = "8"]
#[inline(always)]
pub fn is_8(&self) -> bool {
*self == Dbsize::_8
}
#[doc = "16"]
#[inline(always)]
pub fn is_16(&self) -> bool {
*self == Dbsize::_16
}
#[doc = "32"]
#[inline(always)]
pub fn is_32(&self) -> bool {
*self == Dbsize::_32
}
#[doc = "64"]
#[inline(always)]
pub fn is_64(&self) -> bool {
*self == Dbsize::_64
}
#[doc = "128"]
#[inline(always)]
pub fn is_128(&self) -> bool {
*self == Dbsize::_128
}
#[doc = "256"]
#[inline(always)]
pub fn is_256(&self) -> bool {
*self == Dbsize::_256
}
}
#[doc = "Field `DBSize` writer - Destination burst size"]
pub type DbsizeW<'a, REG> = crate::FieldWriter<'a, REG, 3, Dbsize, crate::Safe>;
impl<'a, REG> DbsizeW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "1"]
#[inline(always)]
pub fn _1(self) -> &'a mut crate::W<REG> {
self.variant(Dbsize::_1)
}
#[doc = "4"]
#[inline(always)]
pub fn _4(self) -> &'a mut crate::W<REG> {
self.variant(Dbsize::_4)
}
#[doc = "8"]
#[inline(always)]
pub fn _8(self) -> &'a mut crate::W<REG> {
self.variant(Dbsize::_8)
}
#[doc = "16"]
#[inline(always)]
pub fn _16(self) -> &'a mut crate::W<REG> {
self.variant(Dbsize::_16)
}
#[doc = "32"]
#[inline(always)]
pub fn _32(self) -> &'a mut crate::W<REG> {
self.variant(Dbsize::_32)
}
#[doc = "64"]
#[inline(always)]
pub fn _64(self) -> &'a mut crate::W<REG> {
self.variant(Dbsize::_64)
}
#[doc = "128"]
#[inline(always)]
pub fn _128(self) -> &'a mut crate::W<REG> {
self.variant(Dbsize::_128)
}
#[doc = "256"]
#[inline(always)]
pub fn _256(self) -> &'a mut crate::W<REG> {
self.variant(Dbsize::_256)
}
}
#[doc = "Source transfer width\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Swidth {
#[doc = "0: 8-bit"]
_8bit = 0,
#[doc = "1: 16-bit"]
_16bit = 1,
#[doc = "2: 32-bit"]
_32bit = 2,
}
impl From<Swidth> for u8 {
#[inline(always)]
fn from(variant: Swidth) -> Self {
variant as _
}
}
impl crate::FieldSpec for Swidth {
type Ux = u8;
}
impl crate::IsEnum for Swidth {}
#[doc = "Field `SWidth` reader - Source transfer width"]
pub type SwidthR = crate::FieldReader<Swidth>;
impl SwidthR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<Swidth> {
match self.bits {
0 => Some(Swidth::_8bit),
1 => Some(Swidth::_16bit),
2 => Some(Swidth::_32bit),
_ => None,
}
}
#[doc = "8-bit"]
#[inline(always)]
pub fn is_8bit(&self) -> bool {
*self == Swidth::_8bit
}
#[doc = "16-bit"]
#[inline(always)]
pub fn is_16bit(&self) -> bool {
*self == Swidth::_16bit
}
#[doc = "32-bit"]
#[inline(always)]
pub fn is_32bit(&self) -> bool {
*self == Swidth::_32bit
}
}
#[doc = "Field `SWidth` writer - Source transfer width"]
pub type SwidthW<'a, REG> = crate::FieldWriter<'a, REG, 3, Swidth>;
impl<'a, REG> SwidthW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "8-bit"]
#[inline(always)]
pub fn _8bit(self) -> &'a mut crate::W<REG> {
self.variant(Swidth::_8bit)
}
#[doc = "16-bit"]
#[inline(always)]
pub fn _16bit(self) -> &'a mut crate::W<REG> {
self.variant(Swidth::_16bit)
}
#[doc = "32-bit"]
#[inline(always)]
pub fn _32bit(self) -> &'a mut crate::W<REG> {
self.variant(Swidth::_32bit)
}
}
#[doc = "Destination transfer width\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Dwidth {
#[doc = "0: 8-bit"]
_8bit = 0,
#[doc = "1: 16-bit"]
_16bit = 1,
#[doc = "2: 32-bit"]
_32bit = 2,
}
impl From<Dwidth> for u8 {
#[inline(always)]
fn from(variant: Dwidth) -> Self {
variant as _
}
}
impl crate::FieldSpec for Dwidth {
type Ux = u8;
}
impl crate::IsEnum for Dwidth {}
#[doc = "Field `DWidth` reader - Destination transfer width"]
pub type DwidthR = crate::FieldReader<Dwidth>;
impl DwidthR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<Dwidth> {
match self.bits {
0 => Some(Dwidth::_8bit),
1 => Some(Dwidth::_16bit),
2 => Some(Dwidth::_32bit),
_ => None,
}
}
#[doc = "8-bit"]
#[inline(always)]
pub fn is_8bit(&self) -> bool {
*self == Dwidth::_8bit
}
#[doc = "16-bit"]
#[inline(always)]
pub fn is_16bit(&self) -> bool {
*self == Dwidth::_16bit
}
#[doc = "32-bit"]
#[inline(always)]
pub fn is_32bit(&self) -> bool {
*self == Dwidth::_32bit
}
}
#[doc = "Field `DWidth` writer - Destination transfer width"]
pub type DwidthW<'a, REG> = crate::FieldWriter<'a, REG, 3, Dwidth>;
impl<'a, REG> DwidthW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "8-bit"]
#[inline(always)]
pub fn _8bit(self) -> &'a mut crate::W<REG> {
self.variant(Dwidth::_8bit)
}
#[doc = "16-bit"]
#[inline(always)]
pub fn _16bit(self) -> &'a mut crate::W<REG> {
self.variant(Dwidth::_16bit)
}
#[doc = "32-bit"]
#[inline(always)]
pub fn _32bit(self) -> &'a mut crate::W<REG> {
self.variant(Dwidth::_32bit)
}
}
#[doc = "Field `S` reader - Source AHB master select"]
pub type SR = crate::BitReader;
#[doc = "Field `S` writer - Source AHB master select"]
pub type SW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `D` reader - Destination AHB master select"]
pub type DR = crate::BitReader;
#[doc = "Field `D` writer - Destination AHB master select"]
pub type DW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SI` reader - Source increment"]
pub type SiR = crate::BitReader;
#[doc = "Field `SI` writer - Source increment"]
pub type SiW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DI` reader - Destination increment"]
pub type DiR = crate::BitReader;
#[doc = "Field `DI` writer - Destination increment"]
pub type DiW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `I` reader - Terminal count interrupt enable"]
pub type IR = crate::BitReader;
#[doc = "Field `I` writer - Terminal count interrupt enable"]
pub type IW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:11 - Transfer size"]
#[inline(always)]
pub fn transfer_size(&self) -> TransferSizeR {
TransferSizeR::new((self.bits & 0x0fff) as u16)
}
#[doc = "Bits 12:14 - Source burst size"]
#[inline(always)]
pub fn sbsize(&self) -> SbsizeR {
SbsizeR::new(((self.bits >> 12) & 7) as u8)
}
#[doc = "Bits 15:17 - Destination burst size"]
#[inline(always)]
pub fn dbsize(&self) -> DbsizeR {
DbsizeR::new(((self.bits >> 15) & 7) as u8)
}
#[doc = "Bits 18:20 - Source transfer width"]
#[inline(always)]
pub fn swidth(&self) -> SwidthR {
SwidthR::new(((self.bits >> 18) & 7) as u8)
}
#[doc = "Bits 21:23 - Destination transfer width"]
#[inline(always)]
pub fn dwidth(&self) -> DwidthR {
DwidthR::new(((self.bits >> 21) & 7) as u8)
}
#[doc = "Bit 24 - Source AHB master select"]
#[inline(always)]
pub fn s(&self) -> SR {
SR::new(((self.bits >> 24) & 1) != 0)
}
#[doc = "Bit 25 - Destination AHB master select"]
#[inline(always)]
pub fn d(&self) -> DR {
DR::new(((self.bits >> 25) & 1) != 0)
}
#[doc = "Bit 26 - Source increment"]
#[inline(always)]
pub fn si(&self) -> SiR {
SiR::new(((self.bits >> 26) & 1) != 0)
}
#[doc = "Bit 27 - Destination increment"]
#[inline(always)]
pub fn di(&self) -> DiR {
DiR::new(((self.bits >> 27) & 1) != 0)
}
#[doc = "Bit 31 - Terminal count interrupt enable"]
#[inline(always)]
pub fn i(&self) -> IR {
IR::new(((self.bits >> 31) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:11 - Transfer size"]
#[inline(always)]
pub fn transfer_size(&mut self) -> TransferSizeW<ControlSpec> {
TransferSizeW::new(self, 0)
}
#[doc = "Bits 12:14 - Source burst size"]
#[inline(always)]
pub fn sbsize(&mut self) -> SbsizeW<ControlSpec> {
SbsizeW::new(self, 12)
}
#[doc = "Bits 15:17 - Destination burst size"]
#[inline(always)]
pub fn dbsize(&mut self) -> DbsizeW<ControlSpec> {
DbsizeW::new(self, 15)
}
#[doc = "Bits 18:20 - Source transfer width"]
#[inline(always)]
pub fn swidth(&mut self) -> SwidthW<ControlSpec> {
SwidthW::new(self, 18)
}
#[doc = "Bits 21:23 - Destination transfer width"]
#[inline(always)]
pub fn dwidth(&mut self) -> DwidthW<ControlSpec> {
DwidthW::new(self, 21)
}
#[doc = "Bit 24 - Source AHB master select"]
#[inline(always)]
pub fn s(&mut self) -> SW<ControlSpec> {
SW::new(self, 24)
}
#[doc = "Bit 25 - Destination AHB master select"]
#[inline(always)]
pub fn d(&mut self) -> DW<ControlSpec> {
DW::new(self, 25)
}
#[doc = "Bit 26 - Source increment"]
#[inline(always)]
pub fn si(&mut self) -> SiW<ControlSpec> {
SiW::new(self, 26)
}
#[doc = "Bit 27 - Destination increment"]
#[inline(always)]
pub fn di(&mut self) -> DiW<ControlSpec> {
DiW::new(self, 27)
}
#[doc = "Bit 31 - Terminal count interrupt enable"]
#[inline(always)]
pub fn i(&mut self) -> IW<ControlSpec> {
IW::new(self, 31)
}
}
#[doc = "Channel Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`control::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`control::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ControlSpec;
impl crate::RegisterSpec for ControlSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`control::R`](R) reader structure"]
impl crate::Readable for ControlSpec {}
#[doc = "`write(|w| ..)` method takes [`control::W`](W) writer structure"]
impl crate::Writable for ControlSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets Control to value 0"]
impl crate::Resettable for ControlSpec {}
}
#[doc = "Configuration (rw) register accessor: Channel Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`configuration::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`configuration::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@configuration`] module"]
pub type Configuration = crate::Reg<configuration::ConfigurationSpec>;
#[doc = "Channel Configuration Register"]
pub mod configuration {
#[doc = "Register `Configuration` reader"]
pub type R = crate::R<ConfigurationSpec>;
#[doc = "Register `Configuration` writer"]
pub type W = crate::W<ConfigurationSpec>;
#[doc = "Field `E` reader - Channel enable"]
pub type ER = crate::BitReader;
#[doc = "Field `E` writer - Channel enable"]
pub type EW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SrcPeripheral` reader - Source peripheral"]
pub type SrcPeripheralR = crate::FieldReader;
#[doc = "Field `SrcPeripheral` writer - Source peripheral"]
pub type SrcPeripheralW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `DstPeripheral` reader - Destination peripheral"]
pub type DstPeripheralR = crate::FieldReader;
#[doc = "Field `DstPeripheral` writer - Destination peripheral"]
pub type DstPeripheralW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Flow control\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum FlowCntrl {
#[doc = "0: MEM_TO_MEM_DMA_CTRL"]
MemToMemDmaCtrl = 0,
#[doc = "1: MEM_TO_PER_DMA_CTRL"]
MemToPerDmaCtrl = 1,
#[doc = "2: PER_TO_MEM_DMA_CTRL"]
PerToMemDmaCtrl = 2,
#[doc = "3: PER_TO_PER_DMA_CTRL"]
PerToPerDmaCtrl = 3,
#[doc = "4: PER_TO_PER_DST_CTRL"]
PerToPerDstCtrl = 4,
#[doc = "5: MEM_TO_PER_PER_CTRL"]
MemToPerPerCtrl = 5,
#[doc = "6: PER_TO_MEM_PER_CTRL"]
PerToMemPerCtrl = 6,
#[doc = "7: PER_TO_PER_SRC_CTRL"]
PerToPerSrcCtrl = 7,
}
impl From<FlowCntrl> for u8 {
#[inline(always)]
fn from(variant: FlowCntrl) -> Self {
variant as _
}
}
impl crate::FieldSpec for FlowCntrl {
type Ux = u8;
}
impl crate::IsEnum for FlowCntrl {}
#[doc = "Field `FlowCntrl` reader - Flow control"]
pub type FlowCntrlR = crate::FieldReader<FlowCntrl>;
impl FlowCntrlR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> FlowCntrl {
match self.bits {
0 => FlowCntrl::MemToMemDmaCtrl,
1 => FlowCntrl::MemToPerDmaCtrl,
2 => FlowCntrl::PerToMemDmaCtrl,
3 => FlowCntrl::PerToPerDmaCtrl,
4 => FlowCntrl::PerToPerDstCtrl,
5 => FlowCntrl::MemToPerPerCtrl,
6 => FlowCntrl::PerToMemPerCtrl,
7 => FlowCntrl::PerToPerSrcCtrl,
_ => unreachable!(),
}
}
#[doc = "MEM_TO_MEM_DMA_CTRL"]
#[inline(always)]
pub fn is_mem_to_mem_dma_ctrl(&self) -> bool {
*self == FlowCntrl::MemToMemDmaCtrl
}
#[doc = "MEM_TO_PER_DMA_CTRL"]
#[inline(always)]
pub fn is_mem_to_per_dma_ctrl(&self) -> bool {
*self == FlowCntrl::MemToPerDmaCtrl
}
#[doc = "PER_TO_MEM_DMA_CTRL"]
#[inline(always)]
pub fn is_per_to_mem_dma_ctrl(&self) -> bool {
*self == FlowCntrl::PerToMemDmaCtrl
}
#[doc = "PER_TO_PER_DMA_CTRL"]
#[inline(always)]
pub fn is_per_to_per_dma_ctrl(&self) -> bool {
*self == FlowCntrl::PerToPerDmaCtrl
}
#[doc = "PER_TO_PER_DST_CTRL"]
#[inline(always)]
pub fn is_per_to_per_dst_ctrl(&self) -> bool {
*self == FlowCntrl::PerToPerDstCtrl
}
#[doc = "MEM_TO_PER_PER_CTRL"]
#[inline(always)]
pub fn is_mem_to_per_per_ctrl(&self) -> bool {
*self == FlowCntrl::MemToPerPerCtrl
}
#[doc = "PER_TO_MEM_PER_CTRL"]
#[inline(always)]
pub fn is_per_to_mem_per_ctrl(&self) -> bool {
*self == FlowCntrl::PerToMemPerCtrl
}
#[doc = "PER_TO_PER_SRC_CTRL"]
#[inline(always)]
pub fn is_per_to_per_src_ctrl(&self) -> bool {
*self == FlowCntrl::PerToPerSrcCtrl
}
}
#[doc = "Field `FlowCntrl` writer - Flow control"]
pub type FlowCntrlW<'a, REG> = crate::FieldWriter<'a, REG, 3, FlowCntrl, crate::Safe>;
impl<'a, REG> FlowCntrlW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "MEM_TO_MEM_DMA_CTRL"]
#[inline(always)]
pub fn mem_to_mem_dma_ctrl(self) -> &'a mut crate::W<REG> {
self.variant(FlowCntrl::MemToMemDmaCtrl)
}
#[doc = "MEM_TO_PER_DMA_CTRL"]
#[inline(always)]
pub fn mem_to_per_dma_ctrl(self) -> &'a mut crate::W<REG> {
self.variant(FlowCntrl::MemToPerDmaCtrl)
}
#[doc = "PER_TO_MEM_DMA_CTRL"]
#[inline(always)]
pub fn per_to_mem_dma_ctrl(self) -> &'a mut crate::W<REG> {
self.variant(FlowCntrl::PerToMemDmaCtrl)
}
#[doc = "PER_TO_PER_DMA_CTRL"]
#[inline(always)]
pub fn per_to_per_dma_ctrl(self) -> &'a mut crate::W<REG> {
self.variant(FlowCntrl::PerToPerDmaCtrl)
}
#[doc = "PER_TO_PER_DST_CTRL"]
#[inline(always)]
pub fn per_to_per_dst_ctrl(self) -> &'a mut crate::W<REG> {
self.variant(FlowCntrl::PerToPerDstCtrl)
}
#[doc = "MEM_TO_PER_PER_CTRL"]
#[inline(always)]
pub fn mem_to_per_per_ctrl(self) -> &'a mut crate::W<REG> {
self.variant(FlowCntrl::MemToPerPerCtrl)
}
#[doc = "PER_TO_MEM_PER_CTRL"]
#[inline(always)]
pub fn per_to_mem_per_ctrl(self) -> &'a mut crate::W<REG> {
self.variant(FlowCntrl::PerToMemPerCtrl)
}
#[doc = "PER_TO_PER_SRC_CTRL"]
#[inline(always)]
pub fn per_to_per_src_ctrl(self) -> &'a mut crate::W<REG> {
self.variant(FlowCntrl::PerToPerSrcCtrl)
}
}
#[doc = "Field `IE` reader - Interrupt error mask"]
pub type IeR = crate::BitReader;
#[doc = "Field `IE` writer - Interrupt error mask"]
pub type IeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ITC` reader - Terminal count interrupt mask"]
pub type ItcR = crate::BitReader;
#[doc = "Field `ITC` writer - Terminal count interrupt mask"]
pub type ItcW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `A` reader - Active"]
pub type AR = crate::BitReader;
#[doc = "Field `H` reader - Halt"]
pub type HR = crate::BitReader;
#[doc = "Field `H` writer - Halt"]
pub type HW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - Channel enable"]
#[inline(always)]
pub fn e(&self) -> ER {
ER::new((self.bits & 1) != 0)
}
#[doc = "Bits 1:4 - Source peripheral"]
#[inline(always)]
pub fn src_peripheral(&self) -> SrcPeripheralR {
SrcPeripheralR::new(((self.bits >> 1) & 0x0f) as u8)
}
#[doc = "Bits 6:9 - Destination peripheral"]
#[inline(always)]
pub fn dst_peripheral(&self) -> DstPeripheralR {
DstPeripheralR::new(((self.bits >> 6) & 0x0f) as u8)
}
#[doc = "Bits 11:13 - Flow control"]
#[inline(always)]
pub fn flow_cntrl(&self) -> FlowCntrlR {
FlowCntrlR::new(((self.bits >> 11) & 7) as u8)
}
#[doc = "Bit 14 - Interrupt error mask"]
#[inline(always)]
pub fn ie(&self) -> IeR {
IeR::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15 - Terminal count interrupt mask"]
#[inline(always)]
pub fn itc(&self) -> ItcR {
ItcR::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bit 17 - Active"]
#[inline(always)]
pub fn a(&self) -> AR {
AR::new(((self.bits >> 17) & 1) != 0)
}
#[doc = "Bit 18 - Halt"]
#[inline(always)]
pub fn h(&self) -> HR {
HR::new(((self.bits >> 18) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Channel enable"]
#[inline(always)]
pub fn e(&mut self) -> EW<ConfigurationSpec> {
EW::new(self, 0)
}
#[doc = "Bits 1:4 - Source peripheral"]
#[inline(always)]
pub fn src_peripheral(&mut self) -> SrcPeripheralW<ConfigurationSpec> {
SrcPeripheralW::new(self, 1)
}
#[doc = "Bits 6:9 - Destination peripheral"]
#[inline(always)]
pub fn dst_peripheral(&mut self) -> DstPeripheralW<ConfigurationSpec> {
DstPeripheralW::new(self, 6)
}
#[doc = "Bits 11:13 - Flow control"]
#[inline(always)]
pub fn flow_cntrl(&mut self) -> FlowCntrlW<ConfigurationSpec> {
FlowCntrlW::new(self, 11)
}
#[doc = "Bit 14 - Interrupt error mask"]
#[inline(always)]
pub fn ie(&mut self) -> IeW<ConfigurationSpec> {
IeW::new(self, 14)
}
#[doc = "Bit 15 - Terminal count interrupt mask"]
#[inline(always)]
pub fn itc(&mut self) -> ItcW<ConfigurationSpec> {
ItcW::new(self, 15)
}
#[doc = "Bit 18 - Halt"]
#[inline(always)]
pub fn h(&mut self) -> HW<ConfigurationSpec> {
HW::new(self, 18)
}
}
#[doc = "Channel Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`configuration::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`configuration::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ConfigurationSpec;
impl crate::RegisterSpec for ConfigurationSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`configuration::R`](R) reader structure"]
impl crate::Readable for ConfigurationSpec {}
#[doc = "`write(|w| ..)` method takes [`configuration::W`](W) writer structure"]
impl crate::Writable for ConfigurationSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets Configuration to value 0"]
impl crate::Resettable for ConfigurationSpec {}
}
}
#[doc = "IntStatus (r) register accessor: Interrupt Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_status`] module"]
pub type IntStatus = crate::Reg<int_status::IntStatusSpec>;
#[doc = "Interrupt Status Register"]
pub mod int_status {
#[doc = "Register `IntStatus` reader"]
pub type R = crate::R<IntStatusSpec>;
#[doc = "Field `Channel0` reader - Channel0"]
pub type Channel0R = crate::BitReader;
#[doc = "Field `Channel1` reader - Channel1"]
pub type Channel1R = crate::BitReader;
#[doc = "Field `Channel2` reader - Channel2"]
pub type Channel2R = crate::BitReader;
#[doc = "Field `Channel3` reader - Channel3"]
pub type Channel3R = crate::BitReader;
#[doc = "Field `Channel4` reader - Channel4"]
pub type Channel4R = crate::BitReader;
#[doc = "Field `Channel5` reader - Channel5"]
pub type Channel5R = crate::BitReader;
#[doc = "Field `Channel6` reader - Channel6"]
pub type Channel6R = crate::BitReader;
#[doc = "Field `Channel7` reader - Channel7"]
pub type Channel7R = crate::BitReader;
impl R {
#[doc = "Bit 0 - Channel0"]
#[inline(always)]
pub fn channel0(&self) -> Channel0R {
Channel0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Channel1"]
#[inline(always)]
pub fn channel1(&self) -> Channel1R {
Channel1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Channel2"]
#[inline(always)]
pub fn channel2(&self) -> Channel2R {
Channel2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Channel3"]
#[inline(always)]
pub fn channel3(&self) -> Channel3R {
Channel3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Channel4"]
#[inline(always)]
pub fn channel4(&self) -> Channel4R {
Channel4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Channel5"]
#[inline(always)]
pub fn channel5(&self) -> Channel5R {
Channel5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Channel6"]
#[inline(always)]
pub fn channel6(&self) -> Channel6R {
Channel6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Channel7"]
#[inline(always)]
pub fn channel7(&self) -> Channel7R {
Channel7R::new(((self.bits >> 7) & 1) != 0)
}
}
#[doc = "Interrupt Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntStatusSpec;
impl crate::RegisterSpec for IntStatusSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`int_status::R`](R) reader structure"]
impl crate::Readable for IntStatusSpec {}
#[doc = "`reset()` method sets IntStatus to value 0"]
impl crate::Resettable for IntStatusSpec {}
}
#[doc = "IntTCStatus (r) register accessor: Interrupt Terminal Count Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_tcstatus::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_tcstatus`] module"]
#[doc(alias = "IntTCStatus")]
pub type IntTcstatus = crate::Reg<int_tcstatus::IntTcstatusSpec>;
#[doc = "Interrupt Terminal Count Status Register"]
pub mod int_tcstatus {
#[doc = "Register `IntTCStatus` reader"]
pub type R = crate::R<IntTcstatusSpec>;
#[doc = "Field `Channel0` reader - Channel0"]
pub type Channel0R = crate::BitReader;
#[doc = "Field `Channel1` reader - Channel1"]
pub type Channel1R = crate::BitReader;
#[doc = "Field `Channel2` reader - Channel2"]
pub type Channel2R = crate::BitReader;
#[doc = "Field `Channel3` reader - Channel3"]
pub type Channel3R = crate::BitReader;
#[doc = "Field `Channel4` reader - Channel4"]
pub type Channel4R = crate::BitReader;
#[doc = "Field `Channel5` reader - Channel5"]
pub type Channel5R = crate::BitReader;
#[doc = "Field `Channel6` reader - Channel6"]
pub type Channel6R = crate::BitReader;
#[doc = "Field `Channel7` reader - Channel7"]
pub type Channel7R = crate::BitReader;
impl R {
#[doc = "Bit 0 - Channel0"]
#[inline(always)]
pub fn channel0(&self) -> Channel0R {
Channel0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Channel1"]
#[inline(always)]
pub fn channel1(&self) -> Channel1R {
Channel1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Channel2"]
#[inline(always)]
pub fn channel2(&self) -> Channel2R {
Channel2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Channel3"]
#[inline(always)]
pub fn channel3(&self) -> Channel3R {
Channel3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Channel4"]
#[inline(always)]
pub fn channel4(&self) -> Channel4R {
Channel4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Channel5"]
#[inline(always)]
pub fn channel5(&self) -> Channel5R {
Channel5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Channel6"]
#[inline(always)]
pub fn channel6(&self) -> Channel6R {
Channel6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Channel7"]
#[inline(always)]
pub fn channel7(&self) -> Channel7R {
Channel7R::new(((self.bits >> 7) & 1) != 0)
}
}
#[doc = "Interrupt Terminal Count Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_tcstatus::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntTcstatusSpec;
impl crate::RegisterSpec for IntTcstatusSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`int_tcstatus::R`](R) reader structure"]
impl crate::Readable for IntTcstatusSpec {}
#[doc = "`reset()` method sets IntTCStatus to value 0"]
impl crate::Resettable for IntTcstatusSpec {}
}
#[doc = "IntTCClear (w) register accessor: Interrupt Terminal Count Clear Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_tcclear::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_tcclear`] module"]
#[doc(alias = "IntTCClear")]
pub type IntTcclear = crate::Reg<int_tcclear::IntTcclearSpec>;
#[doc = "Interrupt Terminal Count Clear Register"]
pub mod int_tcclear {
#[doc = "Register `IntTCClear` writer"]
pub type W = crate::W<IntTcclearSpec>;
#[doc = "Field `Channel0` writer - Channel0"]
pub type Channel0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Channel1` writer - Channel1"]
pub type Channel1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Channel2` writer - Channel2"]
pub type Channel2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Channel3` writer - Channel3"]
pub type Channel3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Channel4` writer - Channel4"]
pub type Channel4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Channel5` writer - Channel5"]
pub type Channel5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Channel6` writer - Channel6"]
pub type Channel6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Channel7` writer - Channel7"]
pub type Channel7W<'a, REG> = crate::BitWriter<'a, REG>;
impl W {
#[doc = "Bit 0 - Channel0"]
#[inline(always)]
pub fn channel0(&mut self) -> Channel0W<IntTcclearSpec> {
Channel0W::new(self, 0)
}
#[doc = "Bit 1 - Channel1"]
#[inline(always)]
pub fn channel1(&mut self) -> Channel1W<IntTcclearSpec> {
Channel1W::new(self, 1)
}
#[doc = "Bit 2 - Channel2"]
#[inline(always)]
pub fn channel2(&mut self) -> Channel2W<IntTcclearSpec> {
Channel2W::new(self, 2)
}
#[doc = "Bit 3 - Channel3"]
#[inline(always)]
pub fn channel3(&mut self) -> Channel3W<IntTcclearSpec> {
Channel3W::new(self, 3)
}
#[doc = "Bit 4 - Channel4"]
#[inline(always)]
pub fn channel4(&mut self) -> Channel4W<IntTcclearSpec> {
Channel4W::new(self, 4)
}
#[doc = "Bit 5 - Channel5"]
#[inline(always)]
pub fn channel5(&mut self) -> Channel5W<IntTcclearSpec> {
Channel5W::new(self, 5)
}
#[doc = "Bit 6 - Channel6"]
#[inline(always)]
pub fn channel6(&mut self) -> Channel6W<IntTcclearSpec> {
Channel6W::new(self, 6)
}
#[doc = "Bit 7 - Channel7"]
#[inline(always)]
pub fn channel7(&mut self) -> Channel7W<IntTcclearSpec> {
Channel7W::new(self, 7)
}
}
#[doc = "Interrupt Terminal Count Clear Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_tcclear::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntTcclearSpec;
impl crate::RegisterSpec for IntTcclearSpec {
type Ux = u32;
}
#[doc = "`write(|w| ..)` method takes [`int_tcclear::W`](W) writer structure"]
impl crate::Writable for IntTcclearSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets IntTCClear to value 0"]
impl crate::Resettable for IntTcclearSpec {}
}
#[doc = "IntErrorStatus (r) register accessor: Interrupt Error Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_error_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_error_status`] module"]
pub type IntErrorStatus = crate::Reg<int_error_status::IntErrorStatusSpec>;
#[doc = "Interrupt Error Status Register"]
pub mod int_error_status {
#[doc = "Register `IntErrorStatus` reader"]
pub type R = crate::R<IntErrorStatusSpec>;
#[doc = "Field `Channel0` reader - Channel0"]
pub type Channel0R = crate::BitReader;
#[doc = "Field `Channel1` reader - Channel1"]
pub type Channel1R = crate::BitReader;
#[doc = "Field `Channel2` reader - Channel2"]
pub type Channel2R = crate::BitReader;
#[doc = "Field `Channel3` reader - Channel3"]
pub type Channel3R = crate::BitReader;
#[doc = "Field `Channel4` reader - Channel4"]
pub type Channel4R = crate::BitReader;
#[doc = "Field `Channel5` reader - Channel5"]
pub type Channel5R = crate::BitReader;
#[doc = "Field `Channel6` reader - Channel6"]
pub type Channel6R = crate::BitReader;
#[doc = "Field `Channel7` reader - Channel7"]
pub type Channel7R = crate::BitReader;
impl R {
#[doc = "Bit 0 - Channel0"]
#[inline(always)]
pub fn channel0(&self) -> Channel0R {
Channel0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Channel1"]
#[inline(always)]
pub fn channel1(&self) -> Channel1R {
Channel1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Channel2"]
#[inline(always)]
pub fn channel2(&self) -> Channel2R {
Channel2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Channel3"]
#[inline(always)]
pub fn channel3(&self) -> Channel3R {
Channel3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Channel4"]
#[inline(always)]
pub fn channel4(&self) -> Channel4R {
Channel4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Channel5"]
#[inline(always)]
pub fn channel5(&self) -> Channel5R {
Channel5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Channel6"]
#[inline(always)]
pub fn channel6(&self) -> Channel6R {
Channel6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Channel7"]
#[inline(always)]
pub fn channel7(&self) -> Channel7R {
Channel7R::new(((self.bits >> 7) & 1) != 0)
}
}
#[doc = "Interrupt Error Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_error_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntErrorStatusSpec;
impl crate::RegisterSpec for IntErrorStatusSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`int_error_status::R`](R) reader structure"]
impl crate::Readable for IntErrorStatusSpec {}
#[doc = "`reset()` method sets IntErrorStatus to value 0"]
impl crate::Resettable for IntErrorStatusSpec {}
}
#[doc = "IntErrorClear (w) register accessor: Interrupt Error Clear Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_error_clear::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_error_clear`] module"]
pub type IntErrorClear = crate::Reg<int_error_clear::IntErrorClearSpec>;
#[doc = "Interrupt Error Clear Register"]
pub mod int_error_clear {
#[doc = "Register `IntErrorClear` writer"]
pub type W = crate::W<IntErrorClearSpec>;
#[doc = "Field `Channel0` writer - Channel0"]
pub type Channel0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Channel1` writer - Channel1"]
pub type Channel1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Channel2` writer - Channel2"]
pub type Channel2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Channel3` writer - Channel3"]
pub type Channel3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Channel4` writer - Channel4"]
pub type Channel4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Channel5` writer - Channel5"]
pub type Channel5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Channel6` writer - Channel6"]
pub type Channel6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Channel7` writer - Channel7"]
pub type Channel7W<'a, REG> = crate::BitWriter<'a, REG>;
impl W {
#[doc = "Bit 0 - Channel0"]
#[inline(always)]
pub fn channel0(&mut self) -> Channel0W<IntErrorClearSpec> {
Channel0W::new(self, 0)
}
#[doc = "Bit 1 - Channel1"]
#[inline(always)]
pub fn channel1(&mut self) -> Channel1W<IntErrorClearSpec> {
Channel1W::new(self, 1)
}
#[doc = "Bit 2 - Channel2"]
#[inline(always)]
pub fn channel2(&mut self) -> Channel2W<IntErrorClearSpec> {
Channel2W::new(self, 2)
}
#[doc = "Bit 3 - Channel3"]
#[inline(always)]
pub fn channel3(&mut self) -> Channel3W<IntErrorClearSpec> {
Channel3W::new(self, 3)
}
#[doc = "Bit 4 - Channel4"]
#[inline(always)]
pub fn channel4(&mut self) -> Channel4W<IntErrorClearSpec> {
Channel4W::new(self, 4)
}
#[doc = "Bit 5 - Channel5"]
#[inline(always)]
pub fn channel5(&mut self) -> Channel5W<IntErrorClearSpec> {
Channel5W::new(self, 5)
}
#[doc = "Bit 6 - Channel6"]
#[inline(always)]
pub fn channel6(&mut self) -> Channel6W<IntErrorClearSpec> {
Channel6W::new(self, 6)
}
#[doc = "Bit 7 - Channel7"]
#[inline(always)]
pub fn channel7(&mut self) -> Channel7W<IntErrorClearSpec> {
Channel7W::new(self, 7)
}
}
#[doc = "Interrupt Error Clear Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_error_clear::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntErrorClearSpec;
impl crate::RegisterSpec for IntErrorClearSpec {
type Ux = u32;
}
#[doc = "`write(|w| ..)` method takes [`int_error_clear::W`](W) writer structure"]
impl crate::Writable for IntErrorClearSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets IntErrorClear to value 0"]
impl crate::Resettable for IntErrorClearSpec {}
}
#[doc = "RawIntTCStatus (r) register accessor: Raw Interrupt Terminal Count Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`raw_int_tcstatus::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@raw_int_tcstatus`] module"]
#[doc(alias = "RawIntTCStatus")]
pub type RawIntTcstatus = crate::Reg<raw_int_tcstatus::RawIntTcstatusSpec>;
#[doc = "Raw Interrupt Terminal Count Status Register"]
pub mod raw_int_tcstatus {
#[doc = "Register `RawIntTCStatus` reader"]
pub type R = crate::R<RawIntTcstatusSpec>;
#[doc = "Field `Channel0` reader - Channel0"]
pub type Channel0R = crate::BitReader;
#[doc = "Field `Channel1` reader - Channel1"]
pub type Channel1R = crate::BitReader;
#[doc = "Field `Channel2` reader - Channel2"]
pub type Channel2R = crate::BitReader;
#[doc = "Field `Channel3` reader - Channel3"]
pub type Channel3R = crate::BitReader;
#[doc = "Field `Channel4` reader - Channel4"]
pub type Channel4R = crate::BitReader;
#[doc = "Field `Channel5` reader - Channel5"]
pub type Channel5R = crate::BitReader;
#[doc = "Field `Channel6` reader - Channel6"]
pub type Channel6R = crate::BitReader;
#[doc = "Field `Channel7` reader - Channel7"]
pub type Channel7R = crate::BitReader;
impl R {
#[doc = "Bit 0 - Channel0"]
#[inline(always)]
pub fn channel0(&self) -> Channel0R {
Channel0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Channel1"]
#[inline(always)]
pub fn channel1(&self) -> Channel1R {
Channel1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Channel2"]
#[inline(always)]
pub fn channel2(&self) -> Channel2R {
Channel2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Channel3"]
#[inline(always)]
pub fn channel3(&self) -> Channel3R {
Channel3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Channel4"]
#[inline(always)]
pub fn channel4(&self) -> Channel4R {
Channel4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Channel5"]
#[inline(always)]
pub fn channel5(&self) -> Channel5R {
Channel5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Channel6"]
#[inline(always)]
pub fn channel6(&self) -> Channel6R {
Channel6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Channel7"]
#[inline(always)]
pub fn channel7(&self) -> Channel7R {
Channel7R::new(((self.bits >> 7) & 1) != 0)
}
}
#[doc = "Raw Interrupt Terminal Count Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`raw_int_tcstatus::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RawIntTcstatusSpec;
impl crate::RegisterSpec for RawIntTcstatusSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`raw_int_tcstatus::R`](R) reader structure"]
impl crate::Readable for RawIntTcstatusSpec {}
#[doc = "`reset()` method sets RawIntTCStatus to value 0"]
impl crate::Resettable for RawIntTcstatusSpec {}
}
#[doc = "RawIntErrorStatus (r) register accessor: Raw Error Interrupt Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`raw_int_error_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@raw_int_error_status`] module"]
pub type RawIntErrorStatus = crate::Reg<raw_int_error_status::RawIntErrorStatusSpec>;
#[doc = "Raw Error Interrupt Status Register"]
pub mod raw_int_error_status {
#[doc = "Register `RawIntErrorStatus` reader"]
pub type R = crate::R<RawIntErrorStatusSpec>;
#[doc = "Field `Channel0` reader - Channel0"]
pub type Channel0R = crate::BitReader;
#[doc = "Field `Channel1` reader - Channel1"]
pub type Channel1R = crate::BitReader;
#[doc = "Field `Channel2` reader - Channel2"]
pub type Channel2R = crate::BitReader;
#[doc = "Field `Channel3` reader - Channel3"]
pub type Channel3R = crate::BitReader;
#[doc = "Field `Channel4` reader - Channel4"]
pub type Channel4R = crate::BitReader;
#[doc = "Field `Channel5` reader - Channel5"]
pub type Channel5R = crate::BitReader;
#[doc = "Field `Channel6` reader - Channel6"]
pub type Channel6R = crate::BitReader;
#[doc = "Field `Channel7` reader - Channel7"]
pub type Channel7R = crate::BitReader;
impl R {
#[doc = "Bit 0 - Channel0"]
#[inline(always)]
pub fn channel0(&self) -> Channel0R {
Channel0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Channel1"]
#[inline(always)]
pub fn channel1(&self) -> Channel1R {
Channel1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Channel2"]
#[inline(always)]
pub fn channel2(&self) -> Channel2R {
Channel2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Channel3"]
#[inline(always)]
pub fn channel3(&self) -> Channel3R {
Channel3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Channel4"]
#[inline(always)]
pub fn channel4(&self) -> Channel4R {
Channel4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Channel5"]
#[inline(always)]
pub fn channel5(&self) -> Channel5R {
Channel5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Channel6"]
#[inline(always)]
pub fn channel6(&self) -> Channel6R {
Channel6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Channel7"]
#[inline(always)]
pub fn channel7(&self) -> Channel7R {
Channel7R::new(((self.bits >> 7) & 1) != 0)
}
}
#[doc = "Raw Error Interrupt Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`raw_int_error_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RawIntErrorStatusSpec;
impl crate::RegisterSpec for RawIntErrorStatusSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`raw_int_error_status::R`](R) reader structure"]
impl crate::Readable for RawIntErrorStatusSpec {}
#[doc = "`reset()` method sets RawIntErrorStatus to value 0"]
impl crate::Resettable for RawIntErrorStatusSpec {}
}
#[doc = "EnabledChannels (r) register accessor: Enabled Channel Register\n\nYou can [`read`](crate::Reg::read) this register and get [`enabled_channels::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enabled_channels`] module"]
pub type EnabledChannels = crate::Reg<enabled_channels::EnabledChannelsSpec>;
#[doc = "Enabled Channel Register"]
pub mod enabled_channels {
#[doc = "Register `EnabledChannels` reader"]
pub type R = crate::R<EnabledChannelsSpec>;
#[doc = "Field `Channel0` reader - Channel0"]
pub type Channel0R = crate::BitReader;
#[doc = "Field `Channel1` reader - Channel1"]
pub type Channel1R = crate::BitReader;
#[doc = "Field `Channel2` reader - Channel2"]
pub type Channel2R = crate::BitReader;
#[doc = "Field `Channel3` reader - Channel3"]
pub type Channel3R = crate::BitReader;
#[doc = "Field `Channel4` reader - Channel4"]
pub type Channel4R = crate::BitReader;
#[doc = "Field `Channel5` reader - Channel5"]
pub type Channel5R = crate::BitReader;
#[doc = "Field `Channel6` reader - Channel6"]
pub type Channel6R = crate::BitReader;
#[doc = "Field `Channel7` reader - Channel7"]
pub type Channel7R = crate::BitReader;
impl R {
#[doc = "Bit 0 - Channel0"]
#[inline(always)]
pub fn channel0(&self) -> Channel0R {
Channel0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Channel1"]
#[inline(always)]
pub fn channel1(&self) -> Channel1R {
Channel1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Channel2"]
#[inline(always)]
pub fn channel2(&self) -> Channel2R {
Channel2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Channel3"]
#[inline(always)]
pub fn channel3(&self) -> Channel3R {
Channel3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Channel4"]
#[inline(always)]
pub fn channel4(&self) -> Channel4R {
Channel4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Channel5"]
#[inline(always)]
pub fn channel5(&self) -> Channel5R {
Channel5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Channel6"]
#[inline(always)]
pub fn channel6(&self) -> Channel6R {
Channel6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Channel7"]
#[inline(always)]
pub fn channel7(&self) -> Channel7R {
Channel7R::new(((self.bits >> 7) & 1) != 0)
}
}
#[doc = "Enabled Channel Register\n\nYou can [`read`](crate::Reg::read) this register and get [`enabled_channels::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EnabledChannelsSpec;
impl crate::RegisterSpec for EnabledChannelsSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`enabled_channels::R`](R) reader structure"]
impl crate::Readable for EnabledChannelsSpec {}
#[doc = "`reset()` method sets EnabledChannels to value 0"]
impl crate::Resettable for EnabledChannelsSpec {}
}
#[doc = "SoftBReq (rw) register accessor: Software Burst Request Register\n\nYou can [`read`](crate::Reg::read) this register and get [`soft_breq::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`soft_breq::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@soft_breq`] module"]
#[doc(alias = "SoftBReq")]
pub type SoftBreq = crate::Reg<soft_breq::SoftBreqSpec>;
#[doc = "Software Burst Request Register"]
pub mod soft_breq {
#[doc = "Register `SoftBReq` reader"]
pub type R = crate::R<SoftBreqSpec>;
#[doc = "Register `SoftBReq` writer"]
pub type W = crate::W<SoftBreqSpec>;
#[doc = "Field `Request0` reader - Request0"]
pub type Request0R = crate::BitReader;
#[doc = "Field `Request0` writer - Request0"]
pub type Request0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Request1` reader - Request1"]
pub type Request1R = crate::BitReader;
#[doc = "Field `Request1` writer - Request1"]
pub type Request1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Request2` reader - Request2"]
pub type Request2R = crate::BitReader;
#[doc = "Field `Request2` writer - Request2"]
pub type Request2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Request3` reader - Request3"]
pub type Request3R = crate::BitReader;
#[doc = "Field `Request3` writer - Request3"]
pub type Request3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Request4` reader - Request4"]
pub type Request4R = crate::BitReader;
#[doc = "Field `Request4` writer - Request4"]
pub type Request4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Request5` reader - Request5"]
pub type Request5R = crate::BitReader;
#[doc = "Field `Request5` writer - Request5"]
pub type Request5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Request6` reader - Request6"]
pub type Request6R = crate::BitReader;
#[doc = "Field `Request6` writer - Request6"]
pub type Request6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Request7` reader - Request7"]
pub type Request7R = crate::BitReader;
#[doc = "Field `Request7` writer - Request7"]
pub type Request7W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Request8` reader - Request8"]
pub type Request8R = crate::BitReader;
#[doc = "Field `Request8` writer - Request8"]
pub type Request8W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Request9` reader - Request9"]
pub type Request9R = crate::BitReader;
#[doc = "Field `Request9` writer - Request9"]
pub type Request9W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Request10` reader - Request10"]
pub type Request10R = crate::BitReader;
#[doc = "Field `Request10` writer - Request10"]
pub type Request10W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Request11` reader - Request11"]
pub type Request11R = crate::BitReader;
#[doc = "Field `Request11` writer - Request11"]
pub type Request11W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Request12` reader - Request12"]
pub type Request12R = crate::BitReader;
#[doc = "Field `Request12` writer - Request12"]
pub type Request12W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Request13` reader - Request13"]
pub type Request13R = crate::BitReader;
#[doc = "Field `Request13` writer - Request13"]
pub type Request13W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Request14` reader - Request14"]
pub type Request14R = crate::BitReader;
#[doc = "Field `Request14` writer - Request14"]
pub type Request14W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Request15` reader - Request15"]
pub type Request15R = crate::BitReader;
#[doc = "Field `Request15` writer - Request15"]
pub type Request15W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - Request0"]
#[inline(always)]
pub fn request0(&self) -> Request0R {
Request0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Request1"]
#[inline(always)]
pub fn request1(&self) -> Request1R {
Request1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Request2"]
#[inline(always)]
pub fn request2(&self) -> Request2R {
Request2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Request3"]
#[inline(always)]
pub fn request3(&self) -> Request3R {
Request3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Request4"]
#[inline(always)]
pub fn request4(&self) -> Request4R {
Request4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Request5"]
#[inline(always)]
pub fn request5(&self) -> Request5R {
Request5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Request6"]
#[inline(always)]
pub fn request6(&self) -> Request6R {
Request6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Request7"]
#[inline(always)]
pub fn request7(&self) -> Request7R {
Request7R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - Request8"]
#[inline(always)]
pub fn request8(&self) -> Request8R {
Request8R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - Request9"]
#[inline(always)]
pub fn request9(&self) -> Request9R {
Request9R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - Request10"]
#[inline(always)]
pub fn request10(&self) -> Request10R {
Request10R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - Request11"]
#[inline(always)]
pub fn request11(&self) -> Request11R {
Request11R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12 - Request12"]
#[inline(always)]
pub fn request12(&self) -> Request12R {
Request12R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13 - Request13"]
#[inline(always)]
pub fn request13(&self) -> Request13R {
Request13R::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - Request14"]
#[inline(always)]
pub fn request14(&self) -> Request14R {
Request14R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15 - Request15"]
#[inline(always)]
pub fn request15(&self) -> Request15R {
Request15R::new(((self.bits >> 15) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Request0"]
#[inline(always)]
pub fn request0(&mut self) -> Request0W<SoftBreqSpec> {
Request0W::new(self, 0)
}
#[doc = "Bit 1 - Request1"]
#[inline(always)]
pub fn request1(&mut self) -> Request1W<SoftBreqSpec> {
Request1W::new(self, 1)
}
#[doc = "Bit 2 - Request2"]
#[inline(always)]
pub fn request2(&mut self) -> Request2W<SoftBreqSpec> {
Request2W::new(self, 2)
}
#[doc = "Bit 3 - Request3"]
#[inline(always)]
pub fn request3(&mut self) -> Request3W<SoftBreqSpec> {
Request3W::new(self, 3)
}
#[doc = "Bit 4 - Request4"]
#[inline(always)]
pub fn request4(&mut self) -> Request4W<SoftBreqSpec> {
Request4W::new(self, 4)
}
#[doc = "Bit 5 - Request5"]
#[inline(always)]
pub fn request5(&mut self) -> Request5W<SoftBreqSpec> {
Request5W::new(self, 5)
}
#[doc = "Bit 6 - Request6"]
#[inline(always)]
pub fn request6(&mut self) -> Request6W<SoftBreqSpec> {
Request6W::new(self, 6)
}
#[doc = "Bit 7 - Request7"]
#[inline(always)]
pub fn request7(&mut self) -> Request7W<SoftBreqSpec> {
Request7W::new(self, 7)
}
#[doc = "Bit 8 - Request8"]
#[inline(always)]
pub fn request8(&mut self) -> Request8W<SoftBreqSpec> {
Request8W::new(self, 8)
}
#[doc = "Bit 9 - Request9"]
#[inline(always)]
pub fn request9(&mut self) -> Request9W<SoftBreqSpec> {
Request9W::new(self, 9)
}
#[doc = "Bit 10 - Request10"]
#[inline(always)]
pub fn request10(&mut self) -> Request10W<SoftBreqSpec> {
Request10W::new(self, 10)
}
#[doc = "Bit 11 - Request11"]
#[inline(always)]
pub fn request11(&mut self) -> Request11W<SoftBreqSpec> {
Request11W::new(self, 11)
}
#[doc = "Bit 12 - Request12"]
#[inline(always)]
pub fn request12(&mut self) -> Request12W<SoftBreqSpec> {
Request12W::new(self, 12)
}
#[doc = "Bit 13 - Request13"]
#[inline(always)]
pub fn request13(&mut self) -> Request13W<SoftBreqSpec> {
Request13W::new(self, 13)
}
#[doc = "Bit 14 - Request14"]
#[inline(always)]
pub fn request14(&mut self) -> Request14W<SoftBreqSpec> {
Request14W::new(self, 14)
}
#[doc = "Bit 15 - Request15"]
#[inline(always)]
pub fn request15(&mut self) -> Request15W<SoftBreqSpec> {
Request15W::new(self, 15)
}
}
#[doc = "Software Burst Request Register\n\nYou can [`read`](crate::Reg::read) this register and get [`soft_breq::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`soft_breq::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SoftBreqSpec;
impl crate::RegisterSpec for SoftBreqSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`soft_breq::R`](R) reader structure"]
impl crate::Readable for SoftBreqSpec {}
#[doc = "`write(|w| ..)` method takes [`soft_breq::W`](W) writer structure"]
impl crate::Writable for SoftBreqSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets SoftBReq to value 0"]
impl crate::Resettable for SoftBreqSpec {}
}
#[doc = "SoftSReq (rw) register accessor: Software Single Request Register\n\nYou can [`read`](crate::Reg::read) this register and get [`soft_sreq::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`soft_sreq::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@soft_sreq`] module"]
#[doc(alias = "SoftSReq")]
pub type SoftSreq = crate::Reg<soft_sreq::SoftSreqSpec>;
#[doc = "Software Single Request Register"]
pub mod soft_sreq {
#[doc = "Register `SoftSReq` reader"]
pub type R = crate::R<SoftSreqSpec>;
#[doc = "Register `SoftSReq` writer"]
pub type W = crate::W<SoftSreqSpec>;
#[doc = "Field `Request0` reader - Request0"]
pub type Request0R = crate::BitReader;
#[doc = "Field `Request0` writer - Request0"]
pub type Request0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Request1` reader - Request1"]
pub type Request1R = crate::BitReader;
#[doc = "Field `Request1` writer - Request1"]
pub type Request1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Request2` reader - Request2"]
pub type Request2R = crate::BitReader;
#[doc = "Field `Request2` writer - Request2"]
pub type Request2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Request3` reader - Request3"]
pub type Request3R = crate::BitReader;
#[doc = "Field `Request3` writer - Request3"]
pub type Request3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Request4` reader - Request4"]
pub type Request4R = crate::BitReader;
#[doc = "Field `Request4` writer - Request4"]
pub type Request4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Request5` reader - Request5"]
pub type Request5R = crate::BitReader;
#[doc = "Field `Request5` writer - Request5"]
pub type Request5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Request6` reader - Request6"]
pub type Request6R = crate::BitReader;
#[doc = "Field `Request6` writer - Request6"]
pub type Request6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Request7` reader - Request7"]
pub type Request7R = crate::BitReader;
#[doc = "Field `Request7` writer - Request7"]
pub type Request7W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Request8` reader - Request8"]
pub type Request8R = crate::BitReader;
#[doc = "Field `Request8` writer - Request8"]
pub type Request8W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Request9` reader - Request9"]
pub type Request9R = crate::BitReader;
#[doc = "Field `Request9` writer - Request9"]
pub type Request9W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Request10` reader - Request10"]
pub type Request10R = crate::BitReader;
#[doc = "Field `Request10` writer - Request10"]
pub type Request10W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Request11` reader - Request11"]
pub type Request11R = crate::BitReader;
#[doc = "Field `Request11` writer - Request11"]
pub type Request11W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Request12` reader - Request12"]
pub type Request12R = crate::BitReader;
#[doc = "Field `Request12` writer - Request12"]
pub type Request12W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Request13` reader - Request13"]
pub type Request13R = crate::BitReader;
#[doc = "Field `Request13` writer - Request13"]
pub type Request13W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Request14` reader - Request14"]
pub type Request14R = crate::BitReader;
#[doc = "Field `Request14` writer - Request14"]
pub type Request14W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Request15` reader - Request15"]
pub type Request15R = crate::BitReader;
#[doc = "Field `Request15` writer - Request15"]
pub type Request15W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - Request0"]
#[inline(always)]
pub fn request0(&self) -> Request0R {
Request0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Request1"]
#[inline(always)]
pub fn request1(&self) -> Request1R {
Request1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Request2"]
#[inline(always)]
pub fn request2(&self) -> Request2R {
Request2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Request3"]
#[inline(always)]
pub fn request3(&self) -> Request3R {
Request3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Request4"]
#[inline(always)]
pub fn request4(&self) -> Request4R {
Request4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Request5"]
#[inline(always)]
pub fn request5(&self) -> Request5R {
Request5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Request6"]
#[inline(always)]
pub fn request6(&self) -> Request6R {
Request6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Request7"]
#[inline(always)]
pub fn request7(&self) -> Request7R {
Request7R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - Request8"]
#[inline(always)]
pub fn request8(&self) -> Request8R {
Request8R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - Request9"]
#[inline(always)]
pub fn request9(&self) -> Request9R {
Request9R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - Request10"]
#[inline(always)]
pub fn request10(&self) -> Request10R {
Request10R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - Request11"]
#[inline(always)]
pub fn request11(&self) -> Request11R {
Request11R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12 - Request12"]
#[inline(always)]
pub fn request12(&self) -> Request12R {
Request12R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13 - Request13"]
#[inline(always)]
pub fn request13(&self) -> Request13R {
Request13R::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - Request14"]
#[inline(always)]
pub fn request14(&self) -> Request14R {
Request14R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15 - Request15"]
#[inline(always)]
pub fn request15(&self) -> Request15R {
Request15R::new(((self.bits >> 15) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Request0"]
#[inline(always)]
pub fn request0(&mut self) -> Request0W<SoftSreqSpec> {
Request0W::new(self, 0)
}
#[doc = "Bit 1 - Request1"]
#[inline(always)]
pub fn request1(&mut self) -> Request1W<SoftSreqSpec> {
Request1W::new(self, 1)
}
#[doc = "Bit 2 - Request2"]
#[inline(always)]
pub fn request2(&mut self) -> Request2W<SoftSreqSpec> {
Request2W::new(self, 2)
}
#[doc = "Bit 3 - Request3"]
#[inline(always)]
pub fn request3(&mut self) -> Request3W<SoftSreqSpec> {
Request3W::new(self, 3)
}
#[doc = "Bit 4 - Request4"]
#[inline(always)]
pub fn request4(&mut self) -> Request4W<SoftSreqSpec> {
Request4W::new(self, 4)
}
#[doc = "Bit 5 - Request5"]
#[inline(always)]
pub fn request5(&mut self) -> Request5W<SoftSreqSpec> {
Request5W::new(self, 5)
}
#[doc = "Bit 6 - Request6"]
#[inline(always)]
pub fn request6(&mut self) -> Request6W<SoftSreqSpec> {
Request6W::new(self, 6)
}
#[doc = "Bit 7 - Request7"]
#[inline(always)]
pub fn request7(&mut self) -> Request7W<SoftSreqSpec> {
Request7W::new(self, 7)
}
#[doc = "Bit 8 - Request8"]
#[inline(always)]
pub fn request8(&mut self) -> Request8W<SoftSreqSpec> {
Request8W::new(self, 8)
}
#[doc = "Bit 9 - Request9"]
#[inline(always)]
pub fn request9(&mut self) -> Request9W<SoftSreqSpec> {
Request9W::new(self, 9)
}
#[doc = "Bit 10 - Request10"]
#[inline(always)]
pub fn request10(&mut self) -> Request10W<SoftSreqSpec> {
Request10W::new(self, 10)
}
#[doc = "Bit 11 - Request11"]
#[inline(always)]
pub fn request11(&mut self) -> Request11W<SoftSreqSpec> {
Request11W::new(self, 11)
}
#[doc = "Bit 12 - Request12"]
#[inline(always)]
pub fn request12(&mut self) -> Request12W<SoftSreqSpec> {
Request12W::new(self, 12)
}
#[doc = "Bit 13 - Request13"]
#[inline(always)]
pub fn request13(&mut self) -> Request13W<SoftSreqSpec> {
Request13W::new(self, 13)
}
#[doc = "Bit 14 - Request14"]
#[inline(always)]
pub fn request14(&mut self) -> Request14W<SoftSreqSpec> {
Request14W::new(self, 14)
}
#[doc = "Bit 15 - Request15"]
#[inline(always)]
pub fn request15(&mut self) -> Request15W<SoftSreqSpec> {
Request15W::new(self, 15)
}
}
#[doc = "Software Single Request Register\n\nYou can [`read`](crate::Reg::read) this register and get [`soft_sreq::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`soft_sreq::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SoftSreqSpec;
impl crate::RegisterSpec for SoftSreqSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`soft_sreq::R`](R) reader structure"]
impl crate::Readable for SoftSreqSpec {}
#[doc = "`write(|w| ..)` method takes [`soft_sreq::W`](W) writer structure"]
impl crate::Writable for SoftSreqSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets SoftSReq to value 0"]
impl crate::Resettable for SoftSreqSpec {}
}
#[doc = "SoftLBReq (rw) register accessor: Software Last Burst Request Register\n\nYou can [`read`](crate::Reg::read) this register and get [`soft_lbreq::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`soft_lbreq::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@soft_lbreq`] module"]
#[doc(alias = "SoftLBReq")]
pub type SoftLbreq = crate::Reg<soft_lbreq::SoftLbreqSpec>;
#[doc = "Software Last Burst Request Register"]
pub mod soft_lbreq {
#[doc = "Register `SoftLBReq` reader"]
pub type R = crate::R<SoftLbreqSpec>;
#[doc = "Register `SoftLBReq` writer"]
pub type W = crate::W<SoftLbreqSpec>;
#[doc = "Field `Request0` reader - Request0"]
pub type Request0R = crate::BitReader;
#[doc = "Field `Request0` writer - Request0"]
pub type Request0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Request1` reader - Request1"]
pub type Request1R = crate::BitReader;
#[doc = "Field `Request1` writer - Request1"]
pub type Request1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Request2` reader - Request2"]
pub type Request2R = crate::BitReader;
#[doc = "Field `Request2` writer - Request2"]
pub type Request2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Request3` reader - Request3"]
pub type Request3R = crate::BitReader;
#[doc = "Field `Request3` writer - Request3"]
pub type Request3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Request4` reader - Request4"]
pub type Request4R = crate::BitReader;
#[doc = "Field `Request4` writer - Request4"]
pub type Request4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Request5` reader - Request5"]
pub type Request5R = crate::BitReader;
#[doc = "Field `Request5` writer - Request5"]
pub type Request5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Request6` reader - Request6"]
pub type Request6R = crate::BitReader;
#[doc = "Field `Request6` writer - Request6"]
pub type Request6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Request7` reader - Request7"]
pub type Request7R = crate::BitReader;
#[doc = "Field `Request7` writer - Request7"]
pub type Request7W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Request8` reader - Request8"]
pub type Request8R = crate::BitReader;
#[doc = "Field `Request8` writer - Request8"]
pub type Request8W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Request9` reader - Request9"]
pub type Request9R = crate::BitReader;
#[doc = "Field `Request9` writer - Request9"]
pub type Request9W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Request10` reader - Request10"]
pub type Request10R = crate::BitReader;
#[doc = "Field `Request10` writer - Request10"]
pub type Request10W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Request11` reader - Request11"]
pub type Request11R = crate::BitReader;
#[doc = "Field `Request11` writer - Request11"]
pub type Request11W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Request12` reader - Request12"]
pub type Request12R = crate::BitReader;
#[doc = "Field `Request12` writer - Request12"]
pub type Request12W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Request13` reader - Request13"]
pub type Request13R = crate::BitReader;
#[doc = "Field `Request13` writer - Request13"]
pub type Request13W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Request14` reader - Request14"]
pub type Request14R = crate::BitReader;
#[doc = "Field `Request14` writer - Request14"]
pub type Request14W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Request15` reader - Request15"]
pub type Request15R = crate::BitReader;
#[doc = "Field `Request15` writer - Request15"]
pub type Request15W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - Request0"]
#[inline(always)]
pub fn request0(&self) -> Request0R {
Request0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Request1"]
#[inline(always)]
pub fn request1(&self) -> Request1R {
Request1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Request2"]
#[inline(always)]
pub fn request2(&self) -> Request2R {
Request2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Request3"]
#[inline(always)]
pub fn request3(&self) -> Request3R {
Request3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Request4"]
#[inline(always)]
pub fn request4(&self) -> Request4R {
Request4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Request5"]
#[inline(always)]
pub fn request5(&self) -> Request5R {
Request5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Request6"]
#[inline(always)]
pub fn request6(&self) -> Request6R {
Request6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Request7"]
#[inline(always)]
pub fn request7(&self) -> Request7R {
Request7R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - Request8"]
#[inline(always)]
pub fn request8(&self) -> Request8R {
Request8R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - Request9"]
#[inline(always)]
pub fn request9(&self) -> Request9R {
Request9R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - Request10"]
#[inline(always)]
pub fn request10(&self) -> Request10R {
Request10R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - Request11"]
#[inline(always)]
pub fn request11(&self) -> Request11R {
Request11R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12 - Request12"]
#[inline(always)]
pub fn request12(&self) -> Request12R {
Request12R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13 - Request13"]
#[inline(always)]
pub fn request13(&self) -> Request13R {
Request13R::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - Request14"]
#[inline(always)]
pub fn request14(&self) -> Request14R {
Request14R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15 - Request15"]
#[inline(always)]
pub fn request15(&self) -> Request15R {
Request15R::new(((self.bits >> 15) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Request0"]
#[inline(always)]
pub fn request0(&mut self) -> Request0W<SoftLbreqSpec> {
Request0W::new(self, 0)
}
#[doc = "Bit 1 - Request1"]
#[inline(always)]
pub fn request1(&mut self) -> Request1W<SoftLbreqSpec> {
Request1W::new(self, 1)
}
#[doc = "Bit 2 - Request2"]
#[inline(always)]
pub fn request2(&mut self) -> Request2W<SoftLbreqSpec> {
Request2W::new(self, 2)
}
#[doc = "Bit 3 - Request3"]
#[inline(always)]
pub fn request3(&mut self) -> Request3W<SoftLbreqSpec> {
Request3W::new(self, 3)
}
#[doc = "Bit 4 - Request4"]
#[inline(always)]
pub fn request4(&mut self) -> Request4W<SoftLbreqSpec> {
Request4W::new(self, 4)
}
#[doc = "Bit 5 - Request5"]
#[inline(always)]
pub fn request5(&mut self) -> Request5W<SoftLbreqSpec> {
Request5W::new(self, 5)
}
#[doc = "Bit 6 - Request6"]
#[inline(always)]
pub fn request6(&mut self) -> Request6W<SoftLbreqSpec> {
Request6W::new(self, 6)
}
#[doc = "Bit 7 - Request7"]
#[inline(always)]
pub fn request7(&mut self) -> Request7W<SoftLbreqSpec> {
Request7W::new(self, 7)
}
#[doc = "Bit 8 - Request8"]
#[inline(always)]
pub fn request8(&mut self) -> Request8W<SoftLbreqSpec> {
Request8W::new(self, 8)
}
#[doc = "Bit 9 - Request9"]
#[inline(always)]
pub fn request9(&mut self) -> Request9W<SoftLbreqSpec> {
Request9W::new(self, 9)
}
#[doc = "Bit 10 - Request10"]
#[inline(always)]
pub fn request10(&mut self) -> Request10W<SoftLbreqSpec> {
Request10W::new(self, 10)
}
#[doc = "Bit 11 - Request11"]
#[inline(always)]
pub fn request11(&mut self) -> Request11W<SoftLbreqSpec> {
Request11W::new(self, 11)
}
#[doc = "Bit 12 - Request12"]
#[inline(always)]
pub fn request12(&mut self) -> Request12W<SoftLbreqSpec> {
Request12W::new(self, 12)
}
#[doc = "Bit 13 - Request13"]
#[inline(always)]
pub fn request13(&mut self) -> Request13W<SoftLbreqSpec> {
Request13W::new(self, 13)
}
#[doc = "Bit 14 - Request14"]
#[inline(always)]
pub fn request14(&mut self) -> Request14W<SoftLbreqSpec> {
Request14W::new(self, 14)
}
#[doc = "Bit 15 - Request15"]
#[inline(always)]
pub fn request15(&mut self) -> Request15W<SoftLbreqSpec> {
Request15W::new(self, 15)
}
}
#[doc = "Software Last Burst Request Register\n\nYou can [`read`](crate::Reg::read) this register and get [`soft_lbreq::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`soft_lbreq::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SoftLbreqSpec;
impl crate::RegisterSpec for SoftLbreqSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`soft_lbreq::R`](R) reader structure"]
impl crate::Readable for SoftLbreqSpec {}
#[doc = "`write(|w| ..)` method takes [`soft_lbreq::W`](W) writer structure"]
impl crate::Writable for SoftLbreqSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets SoftLBReq to value 0"]
impl crate::Resettable for SoftLbreqSpec {}
}
#[doc = "SoftSBReq (rw) register accessor: Software Last Single Request Register\n\nYou can [`read`](crate::Reg::read) this register and get [`soft_sbreq::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`soft_sbreq::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@soft_sbreq`] module"]
#[doc(alias = "SoftSBReq")]
pub type SoftSbreq = crate::Reg<soft_sbreq::SoftSbreqSpec>;
#[doc = "Software Last Single Request Register"]
pub mod soft_sbreq {
#[doc = "Register `SoftSBReq` reader"]
pub type R = crate::R<SoftSbreqSpec>;
#[doc = "Register `SoftSBReq` writer"]
pub type W = crate::W<SoftSbreqSpec>;
#[doc = "Field `Request0` reader - Request0"]
pub type Request0R = crate::BitReader;
#[doc = "Field `Request0` writer - Request0"]
pub type Request0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Request1` reader - Request1"]
pub type Request1R = crate::BitReader;
#[doc = "Field `Request1` writer - Request1"]
pub type Request1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Request2` reader - Request2"]
pub type Request2R = crate::BitReader;
#[doc = "Field `Request2` writer - Request2"]
pub type Request2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Request3` reader - Request3"]
pub type Request3R = crate::BitReader;
#[doc = "Field `Request3` writer - Request3"]
pub type Request3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Request4` reader - Request4"]
pub type Request4R = crate::BitReader;
#[doc = "Field `Request4` writer - Request4"]
pub type Request4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Request5` reader - Request5"]
pub type Request5R = crate::BitReader;
#[doc = "Field `Request5` writer - Request5"]
pub type Request5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Request6` reader - Request6"]
pub type Request6R = crate::BitReader;
#[doc = "Field `Request6` writer - Request6"]
pub type Request6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Request7` reader - Request7"]
pub type Request7R = crate::BitReader;
#[doc = "Field `Request7` writer - Request7"]
pub type Request7W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Request8` reader - Request8"]
pub type Request8R = crate::BitReader;
#[doc = "Field `Request8` writer - Request8"]
pub type Request8W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Request9` reader - Request9"]
pub type Request9R = crate::BitReader;
#[doc = "Field `Request9` writer - Request9"]
pub type Request9W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Request10` reader - Request10"]
pub type Request10R = crate::BitReader;
#[doc = "Field `Request10` writer - Request10"]
pub type Request10W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Request11` reader - Request11"]
pub type Request11R = crate::BitReader;
#[doc = "Field `Request11` writer - Request11"]
pub type Request11W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Request12` reader - Request12"]
pub type Request12R = crate::BitReader;
#[doc = "Field `Request12` writer - Request12"]
pub type Request12W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Request13` reader - Request13"]
pub type Request13R = crate::BitReader;
#[doc = "Field `Request13` writer - Request13"]
pub type Request13W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Request14` reader - Request14"]
pub type Request14R = crate::BitReader;
#[doc = "Field `Request14` writer - Request14"]
pub type Request14W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Request15` reader - Request15"]
pub type Request15R = crate::BitReader;
#[doc = "Field `Request15` writer - Request15"]
pub type Request15W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - Request0"]
#[inline(always)]
pub fn request0(&self) -> Request0R {
Request0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Request1"]
#[inline(always)]
pub fn request1(&self) -> Request1R {
Request1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Request2"]
#[inline(always)]
pub fn request2(&self) -> Request2R {
Request2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Request3"]
#[inline(always)]
pub fn request3(&self) -> Request3R {
Request3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Request4"]
#[inline(always)]
pub fn request4(&self) -> Request4R {
Request4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Request5"]
#[inline(always)]
pub fn request5(&self) -> Request5R {
Request5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Request6"]
#[inline(always)]
pub fn request6(&self) -> Request6R {
Request6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Request7"]
#[inline(always)]
pub fn request7(&self) -> Request7R {
Request7R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - Request8"]
#[inline(always)]
pub fn request8(&self) -> Request8R {
Request8R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - Request9"]
#[inline(always)]
pub fn request9(&self) -> Request9R {
Request9R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - Request10"]
#[inline(always)]
pub fn request10(&self) -> Request10R {
Request10R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - Request11"]
#[inline(always)]
pub fn request11(&self) -> Request11R {
Request11R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12 - Request12"]
#[inline(always)]
pub fn request12(&self) -> Request12R {
Request12R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13 - Request13"]
#[inline(always)]
pub fn request13(&self) -> Request13R {
Request13R::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - Request14"]
#[inline(always)]
pub fn request14(&self) -> Request14R {
Request14R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15 - Request15"]
#[inline(always)]
pub fn request15(&self) -> Request15R {
Request15R::new(((self.bits >> 15) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Request0"]
#[inline(always)]
pub fn request0(&mut self) -> Request0W<SoftSbreqSpec> {
Request0W::new(self, 0)
}
#[doc = "Bit 1 - Request1"]
#[inline(always)]
pub fn request1(&mut self) -> Request1W<SoftSbreqSpec> {
Request1W::new(self, 1)
}
#[doc = "Bit 2 - Request2"]
#[inline(always)]
pub fn request2(&mut self) -> Request2W<SoftSbreqSpec> {
Request2W::new(self, 2)
}
#[doc = "Bit 3 - Request3"]
#[inline(always)]
pub fn request3(&mut self) -> Request3W<SoftSbreqSpec> {
Request3W::new(self, 3)
}
#[doc = "Bit 4 - Request4"]
#[inline(always)]
pub fn request4(&mut self) -> Request4W<SoftSbreqSpec> {
Request4W::new(self, 4)
}
#[doc = "Bit 5 - Request5"]
#[inline(always)]
pub fn request5(&mut self) -> Request5W<SoftSbreqSpec> {
Request5W::new(self, 5)
}
#[doc = "Bit 6 - Request6"]
#[inline(always)]
pub fn request6(&mut self) -> Request6W<SoftSbreqSpec> {
Request6W::new(self, 6)
}
#[doc = "Bit 7 - Request7"]
#[inline(always)]
pub fn request7(&mut self) -> Request7W<SoftSbreqSpec> {
Request7W::new(self, 7)
}
#[doc = "Bit 8 - Request8"]
#[inline(always)]
pub fn request8(&mut self) -> Request8W<SoftSbreqSpec> {
Request8W::new(self, 8)
}
#[doc = "Bit 9 - Request9"]
#[inline(always)]
pub fn request9(&mut self) -> Request9W<SoftSbreqSpec> {
Request9W::new(self, 9)
}
#[doc = "Bit 10 - Request10"]
#[inline(always)]
pub fn request10(&mut self) -> Request10W<SoftSbreqSpec> {
Request10W::new(self, 10)
}
#[doc = "Bit 11 - Request11"]
#[inline(always)]
pub fn request11(&mut self) -> Request11W<SoftSbreqSpec> {
Request11W::new(self, 11)
}
#[doc = "Bit 12 - Request12"]
#[inline(always)]
pub fn request12(&mut self) -> Request12W<SoftSbreqSpec> {
Request12W::new(self, 12)
}
#[doc = "Bit 13 - Request13"]
#[inline(always)]
pub fn request13(&mut self) -> Request13W<SoftSbreqSpec> {
Request13W::new(self, 13)
}
#[doc = "Bit 14 - Request14"]
#[inline(always)]
pub fn request14(&mut self) -> Request14W<SoftSbreqSpec> {
Request14W::new(self, 14)
}
#[doc = "Bit 15 - Request15"]
#[inline(always)]
pub fn request15(&mut self) -> Request15W<SoftSbreqSpec> {
Request15W::new(self, 15)
}
}
#[doc = "Software Last Single Request Register\n\nYou can [`read`](crate::Reg::read) this register and get [`soft_sbreq::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`soft_sbreq::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SoftSbreqSpec;
impl crate::RegisterSpec for SoftSbreqSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`soft_sbreq::R`](R) reader structure"]
impl crate::Readable for SoftSbreqSpec {}
#[doc = "`write(|w| ..)` method takes [`soft_sbreq::W`](W) writer structure"]
impl crate::Writable for SoftSbreqSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets SoftSBReq to value 0"]
impl crate::Resettable for SoftSbreqSpec {}
}
#[doc = "DmacConfiguration (rw) register accessor: Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_configuration::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_configuration::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmac_configuration`] module"]
pub type DmacConfiguration = crate::Reg<dmac_configuration::DmacConfigurationSpec>;
#[doc = "Configuration Register"]
pub mod dmac_configuration {
#[doc = "Register `DmacConfiguration` reader"]
pub type R = crate::R<DmacConfigurationSpec>;
#[doc = "Register `DmacConfiguration` writer"]
pub type W = crate::W<DmacConfigurationSpec>;
#[doc = "Field `E` reader - DMAC enable"]
pub type ER = crate::BitReader;
#[doc = "Field `E` writer - DMAC enable"]
pub type EW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "AHB Master 1 endianness\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum M1 {
#[doc = "0: LE"]
Le = 0,
#[doc = "1: BE"]
Be = 1,
}
impl From<M1> for bool {
#[inline(always)]
fn from(variant: M1) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `M1` reader - AHB Master 1 endianness"]
pub type M1R = crate::BitReader<M1>;
impl M1R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> M1 {
match self.bits {
false => M1::Le,
true => M1::Be,
}
}
#[doc = "LE"]
#[inline(always)]
pub fn is_le(&self) -> bool {
*self == M1::Le
}
#[doc = "BE"]
#[inline(always)]
pub fn is_be(&self) -> bool {
*self == M1::Be
}
}
#[doc = "Field `M1` writer - AHB Master 1 endianness"]
pub type M1W<'a, REG> = crate::BitWriter<'a, REG, M1>;
impl<'a, REG> M1W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "LE"]
#[inline(always)]
pub fn le(self) -> &'a mut crate::W<REG> {
self.variant(M1::Le)
}
#[doc = "BE"]
#[inline(always)]
pub fn be(self) -> &'a mut crate::W<REG> {
self.variant(M1::Be)
}
}
#[doc = "AHB Master 2 endianness\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum M2 {
#[doc = "0: LE"]
Le = 0,
#[doc = "1: BE"]
Be = 1,
}
impl From<M2> for bool {
#[inline(always)]
fn from(variant: M2) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `M2` reader - AHB Master 2 endianness"]
pub type M2R = crate::BitReader<M2>;
impl M2R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> M2 {
match self.bits {
false => M2::Le,
true => M2::Be,
}
}
#[doc = "LE"]
#[inline(always)]
pub fn is_le(&self) -> bool {
*self == M2::Le
}
#[doc = "BE"]
#[inline(always)]
pub fn is_be(&self) -> bool {
*self == M2::Be
}
}
#[doc = "Field `M2` writer - AHB Master 2 endianness"]
pub type M2W<'a, REG> = crate::BitWriter<'a, REG, M2>;
impl<'a, REG> M2W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "LE"]
#[inline(always)]
pub fn le(self) -> &'a mut crate::W<REG> {
self.variant(M2::Le)
}
#[doc = "BE"]
#[inline(always)]
pub fn be(self) -> &'a mut crate::W<REG> {
self.variant(M2::Be)
}
}
impl R {
#[doc = "Bit 0 - DMAC enable"]
#[inline(always)]
pub fn e(&self) -> ER {
ER::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - AHB Master 1 endianness"]
#[inline(always)]
pub fn m1(&self) -> M1R {
M1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - AHB Master 2 endianness"]
#[inline(always)]
pub fn m2(&self) -> M2R {
M2R::new(((self.bits >> 2) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - DMAC enable"]
#[inline(always)]
pub fn e(&mut self) -> EW<DmacConfigurationSpec> {
EW::new(self, 0)
}
#[doc = "Bit 1 - AHB Master 1 endianness"]
#[inline(always)]
pub fn m1(&mut self) -> M1W<DmacConfigurationSpec> {
M1W::new(self, 1)
}
#[doc = "Bit 2 - AHB Master 2 endianness"]
#[inline(always)]
pub fn m2(&mut self) -> M2W<DmacConfigurationSpec> {
M2W::new(self, 2)
}
}
#[doc = "Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`dmac_configuration::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac_configuration::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DmacConfigurationSpec;
impl crate::RegisterSpec for DmacConfigurationSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`dmac_configuration::R`](R) reader structure"]
impl crate::Readable for DmacConfigurationSpec {}
#[doc = "`write(|w| ..)` method takes [`dmac_configuration::W`](W) writer structure"]
impl crate::Writable for DmacConfigurationSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets DmacConfiguration to value 0"]
impl crate::Resettable for DmacConfigurationSpec {}
}
#[doc = "Sync (rw) register accessor: Synchronization Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sync::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sync::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sync`] module"]
pub type Sync = crate::Reg<sync::SyncSpec>;
#[doc = "Synchronization Register"]
pub mod sync {
#[doc = "Register `Sync` reader"]
pub type R = crate::R<SyncSpec>;
#[doc = "Register `Sync` writer"]
pub type W = crate::W<SyncSpec>;
#[doc = "Field `Request0` reader - Request0"]
pub type Request0R = crate::BitReader;
#[doc = "Field `Request0` writer - Request0"]
pub type Request0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Request1` reader - Request1"]
pub type Request1R = crate::BitReader;
#[doc = "Field `Request1` writer - Request1"]
pub type Request1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Request2` reader - Request2"]
pub type Request2R = crate::BitReader;
#[doc = "Field `Request2` writer - Request2"]
pub type Request2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Request3` reader - Request3"]
pub type Request3R = crate::BitReader;
#[doc = "Field `Request3` writer - Request3"]
pub type Request3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Request4` reader - Request4"]
pub type Request4R = crate::BitReader;
#[doc = "Field `Request4` writer - Request4"]
pub type Request4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Request5` reader - Request5"]
pub type Request5R = crate::BitReader;
#[doc = "Field `Request5` writer - Request5"]
pub type Request5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Request6` reader - Request6"]
pub type Request6R = crate::BitReader;
#[doc = "Field `Request6` writer - Request6"]
pub type Request6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Request7` reader - Request7"]
pub type Request7R = crate::BitReader;
#[doc = "Field `Request7` writer - Request7"]
pub type Request7W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Request8` reader - Request8"]
pub type Request8R = crate::BitReader;
#[doc = "Field `Request8` writer - Request8"]
pub type Request8W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Request9` reader - Request9"]
pub type Request9R = crate::BitReader;
#[doc = "Field `Request9` writer - Request9"]
pub type Request9W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Request10` reader - Request10"]
pub type Request10R = crate::BitReader;
#[doc = "Field `Request10` writer - Request10"]
pub type Request10W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Request11` reader - Request11"]
pub type Request11R = crate::BitReader;
#[doc = "Field `Request11` writer - Request11"]
pub type Request11W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Request12` reader - Request12"]
pub type Request12R = crate::BitReader;
#[doc = "Field `Request12` writer - Request12"]
pub type Request12W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Request13` reader - Request13"]
pub type Request13R = crate::BitReader;
#[doc = "Field `Request13` writer - Request13"]
pub type Request13W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Request14` reader - Request14"]
pub type Request14R = crate::BitReader;
#[doc = "Field `Request14` writer - Request14"]
pub type Request14W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Request15` reader - Request15"]
pub type Request15R = crate::BitReader;
#[doc = "Field `Request15` writer - Request15"]
pub type Request15W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - Request0"]
#[inline(always)]
pub fn request0(&self) -> Request0R {
Request0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Request1"]
#[inline(always)]
pub fn request1(&self) -> Request1R {
Request1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Request2"]
#[inline(always)]
pub fn request2(&self) -> Request2R {
Request2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Request3"]
#[inline(always)]
pub fn request3(&self) -> Request3R {
Request3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Request4"]
#[inline(always)]
pub fn request4(&self) -> Request4R {
Request4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Request5"]
#[inline(always)]
pub fn request5(&self) -> Request5R {
Request5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Request6"]
#[inline(always)]
pub fn request6(&self) -> Request6R {
Request6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Request7"]
#[inline(always)]
pub fn request7(&self) -> Request7R {
Request7R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - Request8"]
#[inline(always)]
pub fn request8(&self) -> Request8R {
Request8R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - Request9"]
#[inline(always)]
pub fn request9(&self) -> Request9R {
Request9R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - Request10"]
#[inline(always)]
pub fn request10(&self) -> Request10R {
Request10R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - Request11"]
#[inline(always)]
pub fn request11(&self) -> Request11R {
Request11R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12 - Request12"]
#[inline(always)]
pub fn request12(&self) -> Request12R {
Request12R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13 - Request13"]
#[inline(always)]
pub fn request13(&self) -> Request13R {
Request13R::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - Request14"]
#[inline(always)]
pub fn request14(&self) -> Request14R {
Request14R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15 - Request15"]
#[inline(always)]
pub fn request15(&self) -> Request15R {
Request15R::new(((self.bits >> 15) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Request0"]
#[inline(always)]
pub fn request0(&mut self) -> Request0W<SyncSpec> {
Request0W::new(self, 0)
}
#[doc = "Bit 1 - Request1"]
#[inline(always)]
pub fn request1(&mut self) -> Request1W<SyncSpec> {
Request1W::new(self, 1)
}
#[doc = "Bit 2 - Request2"]
#[inline(always)]
pub fn request2(&mut self) -> Request2W<SyncSpec> {
Request2W::new(self, 2)
}
#[doc = "Bit 3 - Request3"]
#[inline(always)]
pub fn request3(&mut self) -> Request3W<SyncSpec> {
Request3W::new(self, 3)
}
#[doc = "Bit 4 - Request4"]
#[inline(always)]
pub fn request4(&mut self) -> Request4W<SyncSpec> {
Request4W::new(self, 4)
}
#[doc = "Bit 5 - Request5"]
#[inline(always)]
pub fn request5(&mut self) -> Request5W<SyncSpec> {
Request5W::new(self, 5)
}
#[doc = "Bit 6 - Request6"]
#[inline(always)]
pub fn request6(&mut self) -> Request6W<SyncSpec> {
Request6W::new(self, 6)
}
#[doc = "Bit 7 - Request7"]
#[inline(always)]
pub fn request7(&mut self) -> Request7W<SyncSpec> {
Request7W::new(self, 7)
}
#[doc = "Bit 8 - Request8"]
#[inline(always)]
pub fn request8(&mut self) -> Request8W<SyncSpec> {
Request8W::new(self, 8)
}
#[doc = "Bit 9 - Request9"]
#[inline(always)]
pub fn request9(&mut self) -> Request9W<SyncSpec> {
Request9W::new(self, 9)
}
#[doc = "Bit 10 - Request10"]
#[inline(always)]
pub fn request10(&mut self) -> Request10W<SyncSpec> {
Request10W::new(self, 10)
}
#[doc = "Bit 11 - Request11"]
#[inline(always)]
pub fn request11(&mut self) -> Request11W<SyncSpec> {
Request11W::new(self, 11)
}
#[doc = "Bit 12 - Request12"]
#[inline(always)]
pub fn request12(&mut self) -> Request12W<SyncSpec> {
Request12W::new(self, 12)
}
#[doc = "Bit 13 - Request13"]
#[inline(always)]
pub fn request13(&mut self) -> Request13W<SyncSpec> {
Request13W::new(self, 13)
}
#[doc = "Bit 14 - Request14"]
#[inline(always)]
pub fn request14(&mut self) -> Request14W<SyncSpec> {
Request14W::new(self, 14)
}
#[doc = "Bit 15 - Request15"]
#[inline(always)]
pub fn request15(&mut self) -> Request15W<SyncSpec> {
Request15W::new(self, 15)
}
}
#[doc = "Synchronization Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sync::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sync::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SyncSpec;
impl crate::RegisterSpec for SyncSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`sync::R`](R) reader structure"]
impl crate::Readable for SyncSpec {}
#[doc = "`write(|w| ..)` method takes [`sync::W`](W) writer structure"]
impl crate::Writable for SyncSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets Sync to value 0"]
impl crate::Resettable for SyncSpec {}
}
}
#[doc = "USB registers"]
pub type Usb0 = crate::Periph<usb0::RegisterBlock, 0x4100_1000>;
impl core::fmt::Debug for Usb0 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Usb0").finish()
}
}
#[doc = "USB registers"]
pub mod usb0 {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
_reserved0: [u8; 0x80],
gptimer0ld: Gptimer0ld,
gptimer0ctrl: Gptimer0ctrl,
gptimer1ld: Gptimer1ld,
gptimer1ctrl: Gptimer1ctrl,
_reserved4: [u8; 0x70],
ehcicap: Ehcicap,
hcsparams: Hcsparams,
hccparams: Hccparams,
_reserved7: [u8; 0x34],
usbcmd: Usbcmd,
usbsts: Usbsts,
usbintr: Usbintr,
frindex: Frindex,
_reserved11: [u8; 0x04],
_reserved_11_deviceaddr: [u8; 0x04],
asynclistaddr: Asynclistaddr,
_reserved13: [u8; 0x04],
burstsize: Burstsize,
txfilltuning: Txfilltuning,
_reserved15: [u8; 0x10],
endptnak: Endptnak,
endptnaken: Endptnaken,
_reserved17: [u8; 0x04],
portsc: Portsc,
_reserved18: [u8; 0x1c],
otgsc: Otgsc,
usbmode: Usbmode,
endptsetupstat: Endptsetupstat,
endptprime: Endptprime,
endptflush: Endptflush,
endptstatus: Endptstatus,
endptcomplete: Endptcomplete,
endptctrl0: Endptctrl0,
endptctrl1: Endptctrl1,
endptctrl2: Endptctrl2,
endptctrl3: Endptctrl3,
}
impl RegisterBlock {
#[doc = "0x80 - General Purpose Timer #0 Load Register"]
#[inline(always)]
pub const fn gptimer0ld(&self) -> &Gptimer0ld {
&self.gptimer0ld
}
#[doc = "0x84 - General Purpose Timer #0 Control Register"]
#[inline(always)]
pub const fn gptimer0ctrl(&self) -> &Gptimer0ctrl {
&self.gptimer0ctrl
}
#[doc = "0x88 - General Purpose Timer #1 Load Register"]
#[inline(always)]
pub const fn gptimer1ld(&self) -> &Gptimer1ld {
&self.gptimer1ld
}
#[doc = "0x8c - General Purpose Timer #1 Control Register"]
#[inline(always)]
pub const fn gptimer1ctrl(&self) -> &Gptimer1ctrl {
&self.gptimer1ctrl
}
#[doc = "0x100 - ECHI Capability register"]
#[inline(always)]
pub const fn ehcicap(&self) -> &Ehcicap {
&self.ehcicap
}
#[doc = "0x104 - Host Controller Structural Parameters"]
#[inline(always)]
pub const fn hcsparams(&self) -> &Hcsparams {
&self.hcsparams
}
#[doc = "0x108 - Host Controller Capability Parameters"]
#[inline(always)]
pub const fn hccparams(&self) -> &Hccparams {
&self.hccparams
}
#[doc = "0x140 - USB Command"]
#[inline(always)]
pub const fn usbcmd(&self) -> &Usbcmd {
&self.usbcmd
}
#[doc = "0x144 - USB Status"]
#[inline(always)]
pub const fn usbsts(&self) -> &Usbsts {
&self.usbsts
}
#[doc = "0x148 - USB Interrupt Enable"]
#[inline(always)]
pub const fn usbintr(&self) -> &Usbintr {
&self.usbintr
}
#[doc = "0x14c - USB Frame Index"]
#[inline(always)]
pub const fn frindex(&self) -> &Frindex {
&self.frindex
}
#[doc = "0x154 - Device Address"]
#[inline(always)]
pub const fn deviceaddr(&self) -> &Deviceaddr {
unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(340).cast() }
}
#[doc = "0x154 - Frame List Base Address"]
#[inline(always)]
pub const fn periodiclistbase(&self) -> &Periodiclistbase {
unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(340).cast() }
}
#[doc = "0x158 - Asynchronous List Address / Endpoint List Address"]
#[inline(always)]
pub const fn asynclistaddr(&self) -> &Asynclistaddr {
&self.asynclistaddr
}
#[doc = "0x160 - Programmable Burst Size"]
#[inline(always)]
pub const fn burstsize(&self) -> &Burstsize {
&self.burstsize
}
#[doc = "0x164 - Host Transmit Pre-Buffer Packet Tuning"]
#[inline(always)]
pub const fn txfilltuning(&self) -> &Txfilltuning {
&self.txfilltuning
}
#[doc = "0x178 - Endpoint NAK"]
#[inline(always)]
pub const fn endptnak(&self) -> &Endptnak {
&self.endptnak
}
#[doc = "0x17c - Endpoint NAK Enable"]
#[inline(always)]
pub const fn endptnaken(&self) -> &Endptnaken {
&self.endptnaken
}
#[doc = "0x184 - Port Status/Control"]
#[inline(always)]
pub const fn portsc(&self) -> &Portsc {
&self.portsc
}
#[doc = "0x1a4 - OTG Status and Control"]
#[inline(always)]
pub const fn otgsc(&self) -> &Otgsc {
&self.otgsc
}
#[doc = "0x1a8 - USB Device Mode"]
#[inline(always)]
pub const fn usbmode(&self) -> &Usbmode {
&self.usbmode
}
#[doc = "0x1ac - Endpoint Setup Status"]
#[inline(always)]
pub const fn endptsetupstat(&self) -> &Endptsetupstat {
&self.endptsetupstat
}
#[doc = "0x1b0 - Endpoint Initialization"]
#[inline(always)]
pub const fn endptprime(&self) -> &Endptprime {
&self.endptprime
}
#[doc = "0x1b4 - Endpoint De-Initialize"]
#[inline(always)]
pub const fn endptflush(&self) -> &Endptflush {
&self.endptflush
}
#[doc = "0x1b8 - Endpoint Status"]
#[inline(always)]
pub const fn endptstatus(&self) -> &Endptstatus {
&self.endptstatus
}
#[doc = "0x1bc - Endpoint Complete"]
#[inline(always)]
pub const fn endptcomplete(&self) -> &Endptcomplete {
&self.endptcomplete
}
#[doc = "0x1c0 - Endpoint 0 Control"]
#[inline(always)]
pub const fn endptctrl0(&self) -> &Endptctrl0 {
&self.endptctrl0
}
#[doc = "0x1c4 - Endpoint 1 Control"]
#[inline(always)]
pub const fn endptctrl1(&self) -> &Endptctrl1 {
&self.endptctrl1
}
#[doc = "0x1c8 - Endpoint 2 Control"]
#[inline(always)]
pub const fn endptctrl2(&self) -> &Endptctrl2 {
&self.endptctrl2
}
#[doc = "0x1cc - Endpoint 3 Control"]
#[inline(always)]
pub const fn endptctrl3(&self) -> &Endptctrl3 {
&self.endptctrl3
}
}
#[doc = "GPTIMER0LD (rw) register accessor: General Purpose Timer #0 Load Register\n\nYou can [`read`](crate::Reg::read) this register and get [`gptimer0ld::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gptimer0ld::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gptimer0ld`] module"]
#[doc(alias = "GPTIMER0LD")]
pub type Gptimer0ld = crate::Reg<gptimer0ld::Gptimer0ldSpec>;
#[doc = "General Purpose Timer #0 Load Register"]
pub mod gptimer0ld {
#[doc = "Register `GPTIMER0LD` reader"]
pub type R = crate::R<Gptimer0ldSpec>;
#[doc = "Register `GPTIMER0LD` writer"]
pub type W = crate::W<Gptimer0ldSpec>;
#[doc = "Field `GPTIMER0LD` reader - General Purpose Timer #0 Load Register"]
pub type Gptimer0ldR = crate::FieldReader<u32>;
#[doc = "Field `GPTIMER0LD` writer - General Purpose Timer #0 Load Register"]
pub type Gptimer0ldW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
impl R {
#[doc = "Bits 0:23 - General Purpose Timer #0 Load Register"]
#[inline(always)]
pub fn gptimer0ld(&self) -> Gptimer0ldR {
Gptimer0ldR::new(self.bits & 0x00ff_ffff)
}
}
impl W {
#[doc = "Bits 0:23 - General Purpose Timer #0 Load Register"]
#[inline(always)]
pub fn gptimer0ld(&mut self) -> Gptimer0ldW<Gptimer0ldSpec> {
Gptimer0ldW::new(self, 0)
}
}
#[doc = "General Purpose Timer #0 Load Register\n\nYou can [`read`](crate::Reg::read) this register and get [`gptimer0ld::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gptimer0ld::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Gptimer0ldSpec;
impl crate::RegisterSpec for Gptimer0ldSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`gptimer0ld::R`](R) reader structure"]
impl crate::Readable for Gptimer0ldSpec {}
#[doc = "`write(|w| ..)` method takes [`gptimer0ld::W`](W) writer structure"]
impl crate::Writable for Gptimer0ldSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets GPTIMER0LD to value 0"]
impl crate::Resettable for Gptimer0ldSpec {}
}
#[doc = "GPTIMER0CTRL (rw) register accessor: General Purpose Timer #0 Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`gptimer0ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gptimer0ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gptimer0ctrl`] module"]
#[doc(alias = "GPTIMER0CTRL")]
pub type Gptimer0ctrl = crate::Reg<gptimer0ctrl::Gptimer0ctrlSpec>;
#[doc = "General Purpose Timer #0 Control Register"]
pub mod gptimer0ctrl {
#[doc = "Register `GPTIMER0CTRL` reader"]
pub type R = crate::R<Gptimer0ctrlSpec>;
#[doc = "Register `GPTIMER0CTRL` writer"]
pub type W = crate::W<Gptimer0ctrlSpec>;
#[doc = "Field `GPTCNT` reader - Timer Counter"]
pub type GptcntR = crate::FieldReader<u32>;
#[doc = "Timer Mode\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Gptmode {
#[doc = "0: One shot"]
Oneshot = 0,
#[doc = "1: Repeat"]
Repeat = 1,
}
impl From<Gptmode> for bool {
#[inline(always)]
fn from(variant: Gptmode) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `GPTMODE` reader - Timer Mode"]
pub type GptmodeR = crate::BitReader<Gptmode>;
impl GptmodeR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Gptmode {
match self.bits {
false => Gptmode::Oneshot,
true => Gptmode::Repeat,
}
}
#[doc = "One shot"]
#[inline(always)]
pub fn is_oneshot(&self) -> bool {
*self == Gptmode::Oneshot
}
#[doc = "Repeat"]
#[inline(always)]
pub fn is_repeat(&self) -> bool {
*self == Gptmode::Repeat
}
}
#[doc = "Field `GPTMODE` writer - Timer Mode"]
pub type GptmodeW<'a, REG> = crate::BitWriter<'a, REG, Gptmode>;
impl<'a, REG> GptmodeW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "One shot"]
#[inline(always)]
pub fn oneshot(self) -> &'a mut crate::W<REG> {
self.variant(Gptmode::Oneshot)
}
#[doc = "Repeat"]
#[inline(always)]
pub fn repeat(self) -> &'a mut crate::W<REG> {
self.variant(Gptmode::Repeat)
}
}
#[doc = "Field `GPTRST` reader - Timer Reset"]
pub type GptrstR = crate::BitReader;
#[doc = "Field `GPTRST` writer - Timer Reset"]
pub type GptrstW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `GPTRUN` reader - Timer Run"]
pub type GptrunR = crate::BitReader;
#[doc = "Field `GPTRUN` writer - Timer Run"]
pub type GptrunW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:23 - Timer Counter"]
#[inline(always)]
pub fn gptcnt(&self) -> GptcntR {
GptcntR::new(self.bits & 0x00ff_ffff)
}
#[doc = "Bit 24 - Timer Mode"]
#[inline(always)]
pub fn gptmode(&self) -> GptmodeR {
GptmodeR::new(((self.bits >> 24) & 1) != 0)
}
#[doc = "Bit 30 - Timer Reset"]
#[inline(always)]
pub fn gptrst(&self) -> GptrstR {
GptrstR::new(((self.bits >> 30) & 1) != 0)
}
#[doc = "Bit 31 - Timer Run"]
#[inline(always)]
pub fn gptrun(&self) -> GptrunR {
GptrunR::new(((self.bits >> 31) & 1) != 0)
}
}
impl W {
#[doc = "Bit 24 - Timer Mode"]
#[inline(always)]
pub fn gptmode(&mut self) -> GptmodeW<Gptimer0ctrlSpec> {
GptmodeW::new(self, 24)
}
#[doc = "Bit 30 - Timer Reset"]
#[inline(always)]
pub fn gptrst(&mut self) -> GptrstW<Gptimer0ctrlSpec> {
GptrstW::new(self, 30)
}
#[doc = "Bit 31 - Timer Run"]
#[inline(always)]
pub fn gptrun(&mut self) -> GptrunW<Gptimer0ctrlSpec> {
GptrunW::new(self, 31)
}
}
#[doc = "General Purpose Timer #0 Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`gptimer0ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gptimer0ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Gptimer0ctrlSpec;
impl crate::RegisterSpec for Gptimer0ctrlSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`gptimer0ctrl::R`](R) reader structure"]
impl crate::Readable for Gptimer0ctrlSpec {}
#[doc = "`write(|w| ..)` method takes [`gptimer0ctrl::W`](W) writer structure"]
impl crate::Writable for Gptimer0ctrlSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets GPTIMER0CTRL to value 0"]
impl crate::Resettable for Gptimer0ctrlSpec {}
}
#[doc = "GPTIMER1LD (rw) register accessor: General Purpose Timer #1 Load Register\n\nYou can [`read`](crate::Reg::read) this register and get [`gptimer1ld::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gptimer1ld::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gptimer1ld`] module"]
#[doc(alias = "GPTIMER1LD")]
pub type Gptimer1ld = crate::Reg<gptimer1ld::Gptimer1ldSpec>;
#[doc = "General Purpose Timer #1 Load Register"]
pub mod gptimer1ld {
#[doc = "Register `GPTIMER1LD` reader"]
pub type R = crate::R<Gptimer1ldSpec>;
#[doc = "Register `GPTIMER1LD` writer"]
pub type W = crate::W<Gptimer1ldSpec>;
#[doc = "Field `GPTIMER1LD` reader - General Purpose Timer #1 Load Register"]
pub type Gptimer1ldR = crate::FieldReader<u32>;
#[doc = "Field `GPTIMER1LD` writer - General Purpose Timer #1 Load Register"]
pub type Gptimer1ldW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
impl R {
#[doc = "Bits 0:23 - General Purpose Timer #1 Load Register"]
#[inline(always)]
pub fn gptimer1ld(&self) -> Gptimer1ldR {
Gptimer1ldR::new(self.bits & 0x00ff_ffff)
}
}
impl W {
#[doc = "Bits 0:23 - General Purpose Timer #1 Load Register"]
#[inline(always)]
pub fn gptimer1ld(&mut self) -> Gptimer1ldW<Gptimer1ldSpec> {
Gptimer1ldW::new(self, 0)
}
}
#[doc = "General Purpose Timer #1 Load Register\n\nYou can [`read`](crate::Reg::read) this register and get [`gptimer1ld::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gptimer1ld::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Gptimer1ldSpec;
impl crate::RegisterSpec for Gptimer1ldSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`gptimer1ld::R`](R) reader structure"]
impl crate::Readable for Gptimer1ldSpec {}
#[doc = "`write(|w| ..)` method takes [`gptimer1ld::W`](W) writer structure"]
impl crate::Writable for Gptimer1ldSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets GPTIMER1LD to value 0"]
impl crate::Resettable for Gptimer1ldSpec {}
}
#[doc = "GPTIMER1CTRL (rw) register accessor: General Purpose Timer #1 Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`gptimer1ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gptimer1ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gptimer1ctrl`] module"]
#[doc(alias = "GPTIMER1CTRL")]
pub type Gptimer1ctrl = crate::Reg<gptimer1ctrl::Gptimer1ctrlSpec>;
#[doc = "General Purpose Timer #1 Control Register"]
pub mod gptimer1ctrl {
#[doc = "Register `GPTIMER1CTRL` reader"]
pub type R = crate::R<Gptimer1ctrlSpec>;
#[doc = "Register `GPTIMER1CTRL` writer"]
pub type W = crate::W<Gptimer1ctrlSpec>;
#[doc = "Field `GPTCNT` reader - Timer Counter"]
pub type GptcntR = crate::FieldReader<u32>;
#[doc = "Timer Mode\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Gptmode {
#[doc = "0: One shot"]
Oneshot = 0,
#[doc = "1: Repeat"]
Repeat = 1,
}
impl From<Gptmode> for bool {
#[inline(always)]
fn from(variant: Gptmode) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `GPTMODE` reader - Timer Mode"]
pub type GptmodeR = crate::BitReader<Gptmode>;
impl GptmodeR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Gptmode {
match self.bits {
false => Gptmode::Oneshot,
true => Gptmode::Repeat,
}
}
#[doc = "One shot"]
#[inline(always)]
pub fn is_oneshot(&self) -> bool {
*self == Gptmode::Oneshot
}
#[doc = "Repeat"]
#[inline(always)]
pub fn is_repeat(&self) -> bool {
*self == Gptmode::Repeat
}
}
#[doc = "Field `GPTMODE` writer - Timer Mode"]
pub type GptmodeW<'a, REG> = crate::BitWriter<'a, REG, Gptmode>;
impl<'a, REG> GptmodeW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "One shot"]
#[inline(always)]
pub fn oneshot(self) -> &'a mut crate::W<REG> {
self.variant(Gptmode::Oneshot)
}
#[doc = "Repeat"]
#[inline(always)]
pub fn repeat(self) -> &'a mut crate::W<REG> {
self.variant(Gptmode::Repeat)
}
}
#[doc = "Field `GPTRST` reader - Timer Reset"]
pub type GptrstR = crate::BitReader;
#[doc = "Field `GPTRST` writer - Timer Reset"]
pub type GptrstW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `GPTRUN` reader - Timer Run"]
pub type GptrunR = crate::BitReader;
#[doc = "Field `GPTRUN` writer - Timer Run"]
pub type GptrunW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:23 - Timer Counter"]
#[inline(always)]
pub fn gptcnt(&self) -> GptcntR {
GptcntR::new(self.bits & 0x00ff_ffff)
}
#[doc = "Bit 24 - Timer Mode"]
#[inline(always)]
pub fn gptmode(&self) -> GptmodeR {
GptmodeR::new(((self.bits >> 24) & 1) != 0)
}
#[doc = "Bit 30 - Timer Reset"]
#[inline(always)]
pub fn gptrst(&self) -> GptrstR {
GptrstR::new(((self.bits >> 30) & 1) != 0)
}
#[doc = "Bit 31 - Timer Run"]
#[inline(always)]
pub fn gptrun(&self) -> GptrunR {
GptrunR::new(((self.bits >> 31) & 1) != 0)
}
}
impl W {
#[doc = "Bit 24 - Timer Mode"]
#[inline(always)]
pub fn gptmode(&mut self) -> GptmodeW<Gptimer1ctrlSpec> {
GptmodeW::new(self, 24)
}
#[doc = "Bit 30 - Timer Reset"]
#[inline(always)]
pub fn gptrst(&mut self) -> GptrstW<Gptimer1ctrlSpec> {
GptrstW::new(self, 30)
}
#[doc = "Bit 31 - Timer Run"]
#[inline(always)]
pub fn gptrun(&mut self) -> GptrunW<Gptimer1ctrlSpec> {
GptrunW::new(self, 31)
}
}
#[doc = "General Purpose Timer #1 Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`gptimer1ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gptimer1ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Gptimer1ctrlSpec;
impl crate::RegisterSpec for Gptimer1ctrlSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`gptimer1ctrl::R`](R) reader structure"]
impl crate::Readable for Gptimer1ctrlSpec {}
#[doc = "`write(|w| ..)` method takes [`gptimer1ctrl::W`](W) writer structure"]
impl crate::Writable for Gptimer1ctrlSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets GPTIMER1CTRL to value 0"]
impl crate::Resettable for Gptimer1ctrlSpec {}
}
#[doc = "EHCICAP (r) register accessor: ECHI Capability register\n\nYou can [`read`](crate::Reg::read) this register and get [`ehcicap::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ehcicap`] module"]
#[doc(alias = "EHCICAP")]
pub type Ehcicap = crate::Reg<ehcicap::EhcicapSpec>;
#[doc = "ECHI Capability register"]
pub mod ehcicap {
#[doc = "Register `EHCICAP` reader"]
pub type R = crate::R<EhcicapSpec>;
#[doc = "Field `CAPLENGTH` reader - Capability Register Length"]
pub type CaplengthR = crate::FieldReader;
#[doc = "Field `HCIVERSION` reader - Host Interface Version Number"]
pub type HciversionR = crate::FieldReader<u16>;
impl R {
#[doc = "Bits 0:7 - Capability Register Length"]
#[inline(always)]
pub fn caplength(&self) -> CaplengthR {
CaplengthR::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 16:31 - Host Interface Version Number"]
#[inline(always)]
pub fn hciversion(&self) -> HciversionR {
HciversionR::new(((self.bits >> 16) & 0xffff) as u16)
}
}
#[doc = "ECHI Capability register\n\nYou can [`read`](crate::Reg::read) this register and get [`ehcicap::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EhcicapSpec;
impl crate::RegisterSpec for EhcicapSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ehcicap::R`](R) reader structure"]
impl crate::Readable for EhcicapSpec {}
#[doc = "`reset()` method sets EHCICAP to value 0"]
impl crate::Resettable for EhcicapSpec {}
}
#[doc = "HCSPARAMS (r) register accessor: Host Controller Structural Parameters\n\nYou can [`read`](crate::Reg::read) this register and get [`hcsparams::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hcsparams`] module"]
#[doc(alias = "HCSPARAMS")]
pub type Hcsparams = crate::Reg<hcsparams::HcsparamsSpec>;
#[doc = "Host Controller Structural Parameters"]
pub mod hcsparams {
#[doc = "Register `HCSPARAMS` reader"]
pub type R = crate::R<HcsparamsSpec>;
#[doc = "Field `HCSPARAMS` reader - Host Controller Structural Parameters"]
pub type HcsparamsR = crate::FieldReader<u32>;
impl R {
#[doc = "Bits 0:31 - Host Controller Structural Parameters"]
#[inline(always)]
pub fn hcsparams(&self) -> HcsparamsR {
HcsparamsR::new(self.bits)
}
}
#[doc = "Host Controller Structural Parameters\n\nYou can [`read`](crate::Reg::read) this register and get [`hcsparams::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HcsparamsSpec;
impl crate::RegisterSpec for HcsparamsSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`hcsparams::R`](R) reader structure"]
impl crate::Readable for HcsparamsSpec {}
#[doc = "`reset()` method sets HCSPARAMS to value 0"]
impl crate::Resettable for HcsparamsSpec {}
}
#[doc = "HCCPARAMS (r) register accessor: Host Controller Capability Parameters\n\nYou can [`read`](crate::Reg::read) this register and get [`hccparams::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hccparams`] module"]
#[doc(alias = "HCCPARAMS")]
pub type Hccparams = crate::Reg<hccparams::HccparamsSpec>;
#[doc = "Host Controller Capability Parameters"]
pub mod hccparams {
#[doc = "Register `HCCPARAMS` reader"]
pub type R = crate::R<HccparamsSpec>;
#[doc = "Field `HCCPARAMS` reader - Host Controller Capability Parameters"]
pub type HccparamsR = crate::FieldReader<u32>;
impl R {
#[doc = "Bits 0:31 - Host Controller Capability Parameters"]
#[inline(always)]
pub fn hccparams(&self) -> HccparamsR {
HccparamsR::new(self.bits)
}
}
#[doc = "Host Controller Capability Parameters\n\nYou can [`read`](crate::Reg::read) this register and get [`hccparams::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HccparamsSpec;
impl crate::RegisterSpec for HccparamsSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`hccparams::R`](R) reader structure"]
impl crate::Readable for HccparamsSpec {}
#[doc = "`reset()` method sets HCCPARAMS to value 0"]
impl crate::Resettable for HccparamsSpec {}
}
#[doc = "USBCMD (rw) register accessor: USB Command\n\nYou can [`read`](crate::Reg::read) this register and get [`usbcmd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usbcmd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@usbcmd`] module"]
#[doc(alias = "USBCMD")]
pub type Usbcmd = crate::Reg<usbcmd::UsbcmdSpec>;
#[doc = "USB Command"]
pub mod usbcmd {
#[doc = "Register `USBCMD` reader"]
pub type R = crate::R<UsbcmdSpec>;
#[doc = "Register `USBCMD` writer"]
pub type W = crate::W<UsbcmdSpec>;
#[doc = "Field `RS` reader - Run/Stop"]
pub type RsR = crate::BitReader;
#[doc = "Field `RS` writer - Run/Stop"]
pub type RsW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RST` reader - Controller Reset"]
pub type RstR = crate::BitReader;
#[doc = "Field `RST` writer - Controller Reset"]
pub type RstW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `FS0` reader - Frame List Size Bit 0"]
pub type Fs0R = crate::BitReader;
#[doc = "Field `FS0` writer - Frame List Size Bit 0"]
pub type Fs0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `FS1` reader - Frame List Size Bit 1"]
pub type Fs1R = crate::BitReader;
#[doc = "Field `FS1` writer - Frame List Size Bit 1"]
pub type Fs1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PSE` reader - Periodic Schedule Enable"]
pub type PseR = crate::BitReader;
#[doc = "Field `PSE` writer - Periodic Schedule Enable"]
pub type PseW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ASE` reader - Asynchronous Schedule Enable"]
pub type AseR = crate::BitReader;
#[doc = "Field `ASE` writer - Asynchronous Schedule Enable"]
pub type AseW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IAA` reader - Interrupt on Async Advance Doorbell"]
pub type IaaR = crate::BitReader;
#[doc = "Field `IAA` writer - Interrupt on Async Advance Doorbell"]
pub type IaaW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ASP` reader - Asynchronous Schedule Park Mode Count"]
pub type AspR = crate::FieldReader;
#[doc = "Field `ASP` writer - Asynchronous Schedule Park Mode Count"]
pub type AspW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `ASPE` reader - Asynchronous Schedule Park Mode Enable"]
pub type AspeR = crate::BitReader;
#[doc = "Field `ASPE` writer - Asynchronous Schedule Park Mode Enable"]
pub type AspeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SUTW` reader - Setup TripWire"]
pub type SutwR = crate::BitReader;
#[doc = "Field `SUTW` writer - Setup TripWire"]
pub type SutwW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ATDTW` reader - Add dTD TripWire"]
pub type AtdtwR = crate::BitReader;
#[doc = "Field `ATDTW` writer - Add dTD TripWire"]
pub type AtdtwW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `FS2` reader - Frame List Size Bit 2"]
pub type Fs2R = crate::BitReader;
#[doc = "Field `FS2` writer - Frame List Size Bit 2"]
pub type Fs2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ITC` reader - Interrupt Threshold Control"]
pub type ItcR = crate::FieldReader;
#[doc = "Field `ITC` writer - Interrupt Threshold Control"]
pub type ItcW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bit 0 - Run/Stop"]
#[inline(always)]
pub fn rs(&self) -> RsR {
RsR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Controller Reset"]
#[inline(always)]
pub fn rst(&self) -> RstR {
RstR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Frame List Size Bit 0"]
#[inline(always)]
pub fn fs0(&self) -> Fs0R {
Fs0R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Frame List Size Bit 1"]
#[inline(always)]
pub fn fs1(&self) -> Fs1R {
Fs1R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Periodic Schedule Enable"]
#[inline(always)]
pub fn pse(&self) -> PseR {
PseR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Asynchronous Schedule Enable"]
#[inline(always)]
pub fn ase(&self) -> AseR {
AseR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Interrupt on Async Advance Doorbell"]
#[inline(always)]
pub fn iaa(&self) -> IaaR {
IaaR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bits 8:9 - Asynchronous Schedule Park Mode Count"]
#[inline(always)]
pub fn asp(&self) -> AspR {
AspR::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bit 11 - Asynchronous Schedule Park Mode Enable"]
#[inline(always)]
pub fn aspe(&self) -> AspeR {
AspeR::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 13 - Setup TripWire"]
#[inline(always)]
pub fn sutw(&self) -> SutwR {
SutwR::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - Add dTD TripWire"]
#[inline(always)]
pub fn atdtw(&self) -> AtdtwR {
AtdtwR::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15 - Frame List Size Bit 2"]
#[inline(always)]
pub fn fs2(&self) -> Fs2R {
Fs2R::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bits 16:23 - Interrupt Threshold Control"]
#[inline(always)]
pub fn itc(&self) -> ItcR {
ItcR::new(((self.bits >> 16) & 0xff) as u8)
}
}
impl W {
#[doc = "Bit 0 - Run/Stop"]
#[inline(always)]
pub fn rs(&mut self) -> RsW<UsbcmdSpec> {
RsW::new(self, 0)
}
#[doc = "Bit 1 - Controller Reset"]
#[inline(always)]
pub fn rst(&mut self) -> RstW<UsbcmdSpec> {
RstW::new(self, 1)
}
#[doc = "Bit 2 - Frame List Size Bit 0"]
#[inline(always)]
pub fn fs0(&mut self) -> Fs0W<UsbcmdSpec> {
Fs0W::new(self, 2)
}
#[doc = "Bit 3 - Frame List Size Bit 1"]
#[inline(always)]
pub fn fs1(&mut self) -> Fs1W<UsbcmdSpec> {
Fs1W::new(self, 3)
}
#[doc = "Bit 4 - Periodic Schedule Enable"]
#[inline(always)]
pub fn pse(&mut self) -> PseW<UsbcmdSpec> {
PseW::new(self, 4)
}
#[doc = "Bit 5 - Asynchronous Schedule Enable"]
#[inline(always)]
pub fn ase(&mut self) -> AseW<UsbcmdSpec> {
AseW::new(self, 5)
}
#[doc = "Bit 6 - Interrupt on Async Advance Doorbell"]
#[inline(always)]
pub fn iaa(&mut self) -> IaaW<UsbcmdSpec> {
IaaW::new(self, 6)
}
#[doc = "Bits 8:9 - Asynchronous Schedule Park Mode Count"]
#[inline(always)]
pub fn asp(&mut self) -> AspW<UsbcmdSpec> {
AspW::new(self, 8)
}
#[doc = "Bit 11 - Asynchronous Schedule Park Mode Enable"]
#[inline(always)]
pub fn aspe(&mut self) -> AspeW<UsbcmdSpec> {
AspeW::new(self, 11)
}
#[doc = "Bit 13 - Setup TripWire"]
#[inline(always)]
pub fn sutw(&mut self) -> SutwW<UsbcmdSpec> {
SutwW::new(self, 13)
}
#[doc = "Bit 14 - Add dTD TripWire"]
#[inline(always)]
pub fn atdtw(&mut self) -> AtdtwW<UsbcmdSpec> {
AtdtwW::new(self, 14)
}
#[doc = "Bit 15 - Frame List Size Bit 2"]
#[inline(always)]
pub fn fs2(&mut self) -> Fs2W<UsbcmdSpec> {
Fs2W::new(self, 15)
}
#[doc = "Bits 16:23 - Interrupt Threshold Control"]
#[inline(always)]
pub fn itc(&mut self) -> ItcW<UsbcmdSpec> {
ItcW::new(self, 16)
}
}
#[doc = "USB Command\n\nYou can [`read`](crate::Reg::read) this register and get [`usbcmd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usbcmd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct UsbcmdSpec;
impl crate::RegisterSpec for UsbcmdSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`usbcmd::R`](R) reader structure"]
impl crate::Readable for UsbcmdSpec {}
#[doc = "`write(|w| ..)` method takes [`usbcmd::W`](W) writer structure"]
impl crate::Writable for UsbcmdSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets USBCMD to value 0"]
impl crate::Resettable for UsbcmdSpec {}
}
#[doc = "USBSTS (rw) register accessor: USB Status\n\nYou can [`read`](crate::Reg::read) this register and get [`usbsts::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usbsts::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@usbsts`] module"]
#[doc(alias = "USBSTS")]
pub type Usbsts = crate::Reg<usbsts::UsbstsSpec>;
#[doc = "USB Status"]
pub mod usbsts {
#[doc = "Register `USBSTS` reader"]
pub type R = crate::R<UsbstsSpec>;
#[doc = "Register `USBSTS` writer"]
pub type W = crate::W<UsbstsSpec>;
#[doc = "Field `UI` reader - USB Interrupt"]
pub type UiR = crate::BitReader;
#[doc = "Field `UI` writer - USB Interrupt"]
pub type UiW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UEI` reader - USB Error Interrupt"]
pub type UeiR = crate::BitReader;
#[doc = "Field `UEI` writer - USB Error Interrupt"]
pub type UeiW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PCI` reader - Port Change Detect"]
pub type PciR = crate::BitReader;
#[doc = "Field `PCI` writer - Port Change Detect"]
pub type PciW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `FRI` reader - Frame List Rollover"]
pub type FriR = crate::BitReader;
#[doc = "Field `FRI` writer - Frame List Rollover"]
pub type FriW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SEI` reader - System Error (from AHB)"]
pub type SeiR = crate::BitReader;
#[doc = "Field `SEI` writer - System Error (from AHB)"]
pub type SeiW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `AAI` reader - Interrupt on Async Advance"]
pub type AaiR = crate::BitReader;
#[doc = "Field `AAI` writer - Interrupt on Async Advance"]
pub type AaiW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `URI` reader - USB Reset Received"]
pub type UriR = crate::BitReader;
#[doc = "Field `URI` writer - USB Reset Received"]
pub type UriW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SRI` reader - SOF Received"]
pub type SriR = crate::BitReader;
#[doc = "Field `SRI` writer - SOF Received"]
pub type SriW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SLI` reader - DCSuspend"]
pub type SliR = crate::BitReader;
#[doc = "Field `SLI` writer - DCSuspend"]
pub type SliW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `HCH` reader - HCHalted"]
pub type HchR = crate::BitReader;
#[doc = "Field `RCL` reader - Reclamation"]
pub type RclR = crate::BitReader;
#[doc = "Field `PS` reader - Periodic Schedule Status"]
pub type PsR = crate::BitReader;
#[doc = "Field `AS` reader - Asynchronous Schedule Status"]
pub type AsR = crate::BitReader;
#[doc = "Field `NAKI` reader - NAK Interrupt"]
pub type NakiR = crate::BitReader;
#[doc = "Field `UAI` reader - USB Host Asynchronous Interrupt"]
pub type UaiR = crate::BitReader;
#[doc = "Field `UAI` writer - USB Host Asynchronous Interrupt"]
pub type UaiW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UPI` reader - USB Host Periodic Interrupt"]
pub type UpiR = crate::BitReader;
#[doc = "Field `UPI` writer - USB Host Periodic Interrupt"]
pub type UpiW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TI0` reader - General Purpose Timer Interrupt 0"]
pub type Ti0R = crate::BitReader;
#[doc = "Field `TI0` writer - General Purpose Timer Interrupt 0"]
pub type Ti0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TI1` reader - General Purpose Timer Interrupt 1"]
pub type Ti1R = crate::BitReader;
#[doc = "Field `TI1` writer - General Purpose Timer Interrupt 1"]
pub type Ti1W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - USB Interrupt"]
#[inline(always)]
pub fn ui(&self) -> UiR {
UiR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - USB Error Interrupt"]
#[inline(always)]
pub fn uei(&self) -> UeiR {
UeiR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Port Change Detect"]
#[inline(always)]
pub fn pci(&self) -> PciR {
PciR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Frame List Rollover"]
#[inline(always)]
pub fn fri(&self) -> FriR {
FriR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - System Error (from AHB)"]
#[inline(always)]
pub fn sei(&self) -> SeiR {
SeiR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Interrupt on Async Advance"]
#[inline(always)]
pub fn aai(&self) -> AaiR {
AaiR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - USB Reset Received"]
#[inline(always)]
pub fn uri(&self) -> UriR {
UriR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - SOF Received"]
#[inline(always)]
pub fn sri(&self) -> SriR {
SriR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - DCSuspend"]
#[inline(always)]
pub fn sli(&self) -> SliR {
SliR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 12 - HCHalted"]
#[inline(always)]
pub fn hch(&self) -> HchR {
HchR::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13 - Reclamation"]
#[inline(always)]
pub fn rcl(&self) -> RclR {
RclR::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - Periodic Schedule Status"]
#[inline(always)]
pub fn ps(&self) -> PsR {
PsR::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15 - Asynchronous Schedule Status"]
#[inline(always)]
pub fn as_(&self) -> AsR {
AsR::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bit 16 - NAK Interrupt"]
#[inline(always)]
pub fn naki(&self) -> NakiR {
NakiR::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 18 - USB Host Asynchronous Interrupt"]
#[inline(always)]
pub fn uai(&self) -> UaiR {
UaiR::new(((self.bits >> 18) & 1) != 0)
}
#[doc = "Bit 19 - USB Host Periodic Interrupt"]
#[inline(always)]
pub fn upi(&self) -> UpiR {
UpiR::new(((self.bits >> 19) & 1) != 0)
}
#[doc = "Bit 24 - General Purpose Timer Interrupt 0"]
#[inline(always)]
pub fn ti0(&self) -> Ti0R {
Ti0R::new(((self.bits >> 24) & 1) != 0)
}
#[doc = "Bit 25 - General Purpose Timer Interrupt 1"]
#[inline(always)]
pub fn ti1(&self) -> Ti1R {
Ti1R::new(((self.bits >> 25) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - USB Interrupt"]
#[inline(always)]
pub fn ui(&mut self) -> UiW<UsbstsSpec> {
UiW::new(self, 0)
}
#[doc = "Bit 1 - USB Error Interrupt"]
#[inline(always)]
pub fn uei(&mut self) -> UeiW<UsbstsSpec> {
UeiW::new(self, 1)
}
#[doc = "Bit 2 - Port Change Detect"]
#[inline(always)]
pub fn pci(&mut self) -> PciW<UsbstsSpec> {
PciW::new(self, 2)
}
#[doc = "Bit 3 - Frame List Rollover"]
#[inline(always)]
pub fn fri(&mut self) -> FriW<UsbstsSpec> {
FriW::new(self, 3)
}
#[doc = "Bit 4 - System Error (from AHB)"]
#[inline(always)]
pub fn sei(&mut self) -> SeiW<UsbstsSpec> {
SeiW::new(self, 4)
}
#[doc = "Bit 5 - Interrupt on Async Advance"]
#[inline(always)]
pub fn aai(&mut self) -> AaiW<UsbstsSpec> {
AaiW::new(self, 5)
}
#[doc = "Bit 6 - USB Reset Received"]
#[inline(always)]
pub fn uri(&mut self) -> UriW<UsbstsSpec> {
UriW::new(self, 6)
}
#[doc = "Bit 7 - SOF Received"]
#[inline(always)]
pub fn sri(&mut self) -> SriW<UsbstsSpec> {
SriW::new(self, 7)
}
#[doc = "Bit 8 - DCSuspend"]
#[inline(always)]
pub fn sli(&mut self) -> SliW<UsbstsSpec> {
SliW::new(self, 8)
}
#[doc = "Bit 18 - USB Host Asynchronous Interrupt"]
#[inline(always)]
pub fn uai(&mut self) -> UaiW<UsbstsSpec> {
UaiW::new(self, 18)
}
#[doc = "Bit 19 - USB Host Periodic Interrupt"]
#[inline(always)]
pub fn upi(&mut self) -> UpiW<UsbstsSpec> {
UpiW::new(self, 19)
}
#[doc = "Bit 24 - General Purpose Timer Interrupt 0"]
#[inline(always)]
pub fn ti0(&mut self) -> Ti0W<UsbstsSpec> {
Ti0W::new(self, 24)
}
#[doc = "Bit 25 - General Purpose Timer Interrupt 1"]
#[inline(always)]
pub fn ti1(&mut self) -> Ti1W<UsbstsSpec> {
Ti1W::new(self, 25)
}
}
#[doc = "USB Status\n\nYou can [`read`](crate::Reg::read) this register and get [`usbsts::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usbsts::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct UsbstsSpec;
impl crate::RegisterSpec for UsbstsSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`usbsts::R`](R) reader structure"]
impl crate::Readable for UsbstsSpec {}
#[doc = "`write(|w| ..)` method takes [`usbsts::W`](W) writer structure"]
impl crate::Writable for UsbstsSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets USBSTS to value 0"]
impl crate::Resettable for UsbstsSpec {}
}
#[doc = "USBINTR (rw) register accessor: USB Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`usbintr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usbintr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@usbintr`] module"]
#[doc(alias = "USBINTR")]
pub type Usbintr = crate::Reg<usbintr::UsbintrSpec>;
#[doc = "USB Interrupt Enable"]
pub mod usbintr {
#[doc = "Register `USBINTR` reader"]
pub type R = crate::R<UsbintrSpec>;
#[doc = "Register `USBINTR` writer"]
pub type W = crate::W<UsbintrSpec>;
#[doc = "Field `UE` reader - USB Interrupt Enable"]
pub type UeR = crate::BitReader;
#[doc = "Field `UE` writer - USB Interrupt Enable"]
pub type UeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UEE` reader - USB Error Interrupt Enable"]
pub type UeeR = crate::BitReader;
#[doc = "Field `UEE` writer - USB Error Interrupt Enable"]
pub type UeeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PCE` reader - Port Change Detect Interrupt Enable"]
pub type PceR = crate::BitReader;
#[doc = "Field `PCE` writer - Port Change Detect Interrupt Enable"]
pub type PceW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `FRE` reader - Frame List Rollover Interrupt Enable"]
pub type FreR = crate::BitReader;
#[doc = "Field `FRE` writer - Frame List Rollover Interrupt Enable"]
pub type FreW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SEE` reader - System Error (from AHB) Interrupt Enable"]
pub type SeeR = crate::BitReader;
#[doc = "Field `SEE` writer - System Error (from AHB) Interrupt Enable"]
pub type SeeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `AAE` reader - Interrupt on Async Advance Enable"]
pub type AaeR = crate::BitReader;
#[doc = "Field `AAE` writer - Interrupt on Async Advance Enable"]
pub type AaeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `URE` reader - USB Reset Received Interrupt Enable"]
pub type UreR = crate::BitReader;
#[doc = "Field `URE` writer - USB Reset Received Interrupt Enable"]
pub type UreW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SRE` reader - SOF Received Interrupt Enable"]
pub type SreR = crate::BitReader;
#[doc = "Field `SRE` writer - SOF Received Interrupt Enable"]
pub type SreW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SLE` reader - DCSuspend Interrupt Enable"]
pub type SleR = crate::BitReader;
#[doc = "Field `SLE` writer - DCSuspend Interrupt Enable"]
pub type SleW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `NAKE` reader - NAK Interrupt Enable"]
pub type NakeR = crate::BitReader;
#[doc = "Field `UAIE` reader - USB Host Asynchronous Interrupt Enable"]
pub type UaieR = crate::BitReader;
#[doc = "Field `UAIE` writer - USB Host Asynchronous Interrupt Enable"]
pub type UaieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UPIE` reader - USB Host Periodic Interrupt Enable"]
pub type UpieR = crate::BitReader;
#[doc = "Field `UPIE` writer - USB Host Periodic Interrupt Enable"]
pub type UpieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TIE0` reader - General Purpose Timer Interrupt Enable 0"]
pub type Tie0R = crate::BitReader;
#[doc = "Field `TIE0` writer - General Purpose Timer Interrupt Enable 0"]
pub type Tie0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TIE1` reader - General Purpose Timer Interrupt Enable 1"]
pub type Tie1R = crate::BitReader;
#[doc = "Field `TIE1` writer - General Purpose Timer Interrupt Enable 1"]
pub type Tie1W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - USB Interrupt Enable"]
#[inline(always)]
pub fn ue(&self) -> UeR {
UeR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - USB Error Interrupt Enable"]
#[inline(always)]
pub fn uee(&self) -> UeeR {
UeeR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Port Change Detect Interrupt Enable"]
#[inline(always)]
pub fn pce(&self) -> PceR {
PceR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Frame List Rollover Interrupt Enable"]
#[inline(always)]
pub fn fre(&self) -> FreR {
FreR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - System Error (from AHB) Interrupt Enable"]
#[inline(always)]
pub fn see(&self) -> SeeR {
SeeR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Interrupt on Async Advance Enable"]
#[inline(always)]
pub fn aae(&self) -> AaeR {
AaeR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - USB Reset Received Interrupt Enable"]
#[inline(always)]
pub fn ure(&self) -> UreR {
UreR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - SOF Received Interrupt Enable"]
#[inline(always)]
pub fn sre(&self) -> SreR {
SreR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - DCSuspend Interrupt Enable"]
#[inline(always)]
pub fn sle(&self) -> SleR {
SleR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 16 - NAK Interrupt Enable"]
#[inline(always)]
pub fn nake(&self) -> NakeR {
NakeR::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 18 - USB Host Asynchronous Interrupt Enable"]
#[inline(always)]
pub fn uaie(&self) -> UaieR {
UaieR::new(((self.bits >> 18) & 1) != 0)
}
#[doc = "Bit 19 - USB Host Periodic Interrupt Enable"]
#[inline(always)]
pub fn upie(&self) -> UpieR {
UpieR::new(((self.bits >> 19) & 1) != 0)
}
#[doc = "Bit 24 - General Purpose Timer Interrupt Enable 0"]
#[inline(always)]
pub fn tie0(&self) -> Tie0R {
Tie0R::new(((self.bits >> 24) & 1) != 0)
}
#[doc = "Bit 25 - General Purpose Timer Interrupt Enable 1"]
#[inline(always)]
pub fn tie1(&self) -> Tie1R {
Tie1R::new(((self.bits >> 25) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - USB Interrupt Enable"]
#[inline(always)]
pub fn ue(&mut self) -> UeW<UsbintrSpec> {
UeW::new(self, 0)
}
#[doc = "Bit 1 - USB Error Interrupt Enable"]
#[inline(always)]
pub fn uee(&mut self) -> UeeW<UsbintrSpec> {
UeeW::new(self, 1)
}
#[doc = "Bit 2 - Port Change Detect Interrupt Enable"]
#[inline(always)]
pub fn pce(&mut self) -> PceW<UsbintrSpec> {
PceW::new(self, 2)
}
#[doc = "Bit 3 - Frame List Rollover Interrupt Enable"]
#[inline(always)]
pub fn fre(&mut self) -> FreW<UsbintrSpec> {
FreW::new(self, 3)
}
#[doc = "Bit 4 - System Error (from AHB) Interrupt Enable"]
#[inline(always)]
pub fn see(&mut self) -> SeeW<UsbintrSpec> {
SeeW::new(self, 4)
}
#[doc = "Bit 5 - Interrupt on Async Advance Enable"]
#[inline(always)]
pub fn aae(&mut self) -> AaeW<UsbintrSpec> {
AaeW::new(self, 5)
}
#[doc = "Bit 6 - USB Reset Received Interrupt Enable"]
#[inline(always)]
pub fn ure(&mut self) -> UreW<UsbintrSpec> {
UreW::new(self, 6)
}
#[doc = "Bit 7 - SOF Received Interrupt Enable"]
#[inline(always)]
pub fn sre(&mut self) -> SreW<UsbintrSpec> {
SreW::new(self, 7)
}
#[doc = "Bit 8 - DCSuspend Interrupt Enable"]
#[inline(always)]
pub fn sle(&mut self) -> SleW<UsbintrSpec> {
SleW::new(self, 8)
}
#[doc = "Bit 18 - USB Host Asynchronous Interrupt Enable"]
#[inline(always)]
pub fn uaie(&mut self) -> UaieW<UsbintrSpec> {
UaieW::new(self, 18)
}
#[doc = "Bit 19 - USB Host Periodic Interrupt Enable"]
#[inline(always)]
pub fn upie(&mut self) -> UpieW<UsbintrSpec> {
UpieW::new(self, 19)
}
#[doc = "Bit 24 - General Purpose Timer Interrupt Enable 0"]
#[inline(always)]
pub fn tie0(&mut self) -> Tie0W<UsbintrSpec> {
Tie0W::new(self, 24)
}
#[doc = "Bit 25 - General Purpose Timer Interrupt Enable 1"]
#[inline(always)]
pub fn tie1(&mut self) -> Tie1W<UsbintrSpec> {
Tie1W::new(self, 25)
}
}
#[doc = "USB Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`usbintr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usbintr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct UsbintrSpec;
impl crate::RegisterSpec for UsbintrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`usbintr::R`](R) reader structure"]
impl crate::Readable for UsbintrSpec {}
#[doc = "`write(|w| ..)` method takes [`usbintr::W`](W) writer structure"]
impl crate::Writable for UsbintrSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets USBINTR to value 0"]
impl crate::Resettable for UsbintrSpec {}
}
#[doc = "FRINDEX (rw) register accessor: USB Frame Index\n\nYou can [`read`](crate::Reg::read) this register and get [`frindex::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`frindex::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@frindex`] module"]
#[doc(alias = "FRINDEX")]
pub type Frindex = crate::Reg<frindex::FrindexSpec>;
#[doc = "USB Frame Index"]
pub mod frindex {
#[doc = "Register `FRINDEX` reader"]
pub type R = crate::R<FrindexSpec>;
#[doc = "Register `FRINDEX` writer"]
pub type W = crate::W<FrindexSpec>;
#[doc = "Field `FRINDEX` reader - USB Frame Index"]
pub type FrindexR = crate::FieldReader<u16>;
#[doc = "Field `FRINDEX` writer - USB Frame Index"]
pub type FrindexW<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>;
impl R {
#[doc = "Bits 0:13 - USB Frame Index"]
#[inline(always)]
pub fn frindex(&self) -> FrindexR {
FrindexR::new((self.bits & 0x3fff) as u16)
}
}
impl W {
#[doc = "Bits 0:13 - USB Frame Index"]
#[inline(always)]
pub fn frindex(&mut self) -> FrindexW<FrindexSpec> {
FrindexW::new(self, 0)
}
}
#[doc = "USB Frame Index\n\nYou can [`read`](crate::Reg::read) this register and get [`frindex::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`frindex::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FrindexSpec;
impl crate::RegisterSpec for FrindexSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`frindex::R`](R) reader structure"]
impl crate::Readable for FrindexSpec {}
#[doc = "`write(|w| ..)` method takes [`frindex::W`](W) writer structure"]
impl crate::Writable for FrindexSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets FRINDEX to value 0"]
impl crate::Resettable for FrindexSpec {}
}
#[doc = "PERIODICLISTBASE (rw) register accessor: Frame List Base Address\n\nYou can [`read`](crate::Reg::read) this register and get [`periodiclistbase::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`periodiclistbase::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@periodiclistbase`] module"]
#[doc(alias = "PERIODICLISTBASE")]
pub type Periodiclistbase = crate::Reg<periodiclistbase::PeriodiclistbaseSpec>;
#[doc = "Frame List Base Address"]
pub mod periodiclistbase {
#[doc = "Register `PERIODICLISTBASE` reader"]
pub type R = crate::R<PeriodiclistbaseSpec>;
#[doc = "Register `PERIODICLISTBASE` writer"]
pub type W = crate::W<PeriodiclistbaseSpec>;
#[doc = "Field `PERIODICLISTBASE` reader - Frame List Base Address"]
pub type PeriodiclistbaseR = crate::FieldReader<u32>;
#[doc = "Field `PERIODICLISTBASE` writer - Frame List Base Address"]
pub type PeriodiclistbaseW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - Frame List Base Address"]
#[inline(always)]
pub fn periodiclistbase(&self) -> PeriodiclistbaseR {
PeriodiclistbaseR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - Frame List Base Address"]
#[inline(always)]
pub fn periodiclistbase(&mut self) -> PeriodiclistbaseW<PeriodiclistbaseSpec> {
PeriodiclistbaseW::new(self, 0)
}
}
#[doc = "Frame List Base Address\n\nYou can [`read`](crate::Reg::read) this register and get [`periodiclistbase::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`periodiclistbase::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PeriodiclistbaseSpec;
impl crate::RegisterSpec for PeriodiclistbaseSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`periodiclistbase::R`](R) reader structure"]
impl crate::Readable for PeriodiclistbaseSpec {}
#[doc = "`write(|w| ..)` method takes [`periodiclistbase::W`](W) writer structure"]
impl crate::Writable for PeriodiclistbaseSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets PERIODICLISTBASE to value 0"]
impl crate::Resettable for PeriodiclistbaseSpec {}
}
#[doc = "DEVICEADDR (rw) register accessor: Device Address\n\nYou can [`read`](crate::Reg::read) this register and get [`deviceaddr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`deviceaddr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@deviceaddr`] module"]
#[doc(alias = "DEVICEADDR")]
pub type Deviceaddr = crate::Reg<deviceaddr::DeviceaddrSpec>;
#[doc = "Device Address"]
pub mod deviceaddr {
#[doc = "Register `DEVICEADDR` reader"]
pub type R = crate::R<DeviceaddrSpec>;
#[doc = "Register `DEVICEADDR` writer"]
pub type W = crate::W<DeviceaddrSpec>;
#[doc = "Field `USBADRA` reader - Device address advance"]
pub type UsbadraR = crate::BitReader;
#[doc = "Field `USBADRA` writer - Device address advance"]
pub type UsbadraW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `USBADR` reader - USB Device address"]
pub type UsbadrR = crate::FieldReader;
#[doc = "Field `USBADR` writer - USB Device address"]
pub type UsbadrW<'a, REG> = crate::FieldWriter<'a, REG, 7>;
impl R {
#[doc = "Bit 24 - Device address advance"]
#[inline(always)]
pub fn usbadra(&self) -> UsbadraR {
UsbadraR::new(((self.bits >> 24) & 1) != 0)
}
#[doc = "Bits 25:31 - USB Device address"]
#[inline(always)]
pub fn usbadr(&self) -> UsbadrR {
UsbadrR::new(((self.bits >> 25) & 0x7f) as u8)
}
}
impl W {
#[doc = "Bit 24 - Device address advance"]
#[inline(always)]
pub fn usbadra(&mut self) -> UsbadraW<DeviceaddrSpec> {
UsbadraW::new(self, 24)
}
#[doc = "Bits 25:31 - USB Device address"]
#[inline(always)]
pub fn usbadr(&mut self) -> UsbadrW<DeviceaddrSpec> {
UsbadrW::new(self, 25)
}
}
#[doc = "Device Address\n\nYou can [`read`](crate::Reg::read) this register and get [`deviceaddr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`deviceaddr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DeviceaddrSpec;
impl crate::RegisterSpec for DeviceaddrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`deviceaddr::R`](R) reader structure"]
impl crate::Readable for DeviceaddrSpec {}
#[doc = "`write(|w| ..)` method takes [`deviceaddr::W`](W) writer structure"]
impl crate::Writable for DeviceaddrSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets DEVICEADDR to value 0"]
impl crate::Resettable for DeviceaddrSpec {}
}
#[doc = "ASYNCLISTADDR (rw) register accessor: Asynchronous List Address / Endpoint List Address\n\nYou can [`read`](crate::Reg::read) this register and get [`asynclistaddr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`asynclistaddr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@asynclistaddr`] module"]
#[doc(alias = "ASYNCLISTADDR")]
pub type Asynclistaddr = crate::Reg<asynclistaddr::AsynclistaddrSpec>;
#[doc = "Asynchronous List Address / Endpoint List Address"]
pub mod asynclistaddr {
#[doc = "Register `ASYNCLISTADDR` reader"]
pub type R = crate::R<AsynclistaddrSpec>;
#[doc = "Register `ASYNCLISTADDR` writer"]
pub type W = crate::W<AsynclistaddrSpec>;
#[doc = "Field `ASYNCLISTADDR` reader - Asynchronous List Address / Endpoint List Address"]
pub type AsynclistaddrR = crate::FieldReader<u32>;
#[doc = "Field `ASYNCLISTADDR` writer - Asynchronous List Address / Endpoint List Address"]
pub type AsynclistaddrW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - Asynchronous List Address / Endpoint List Address"]
#[inline(always)]
pub fn asynclistaddr(&self) -> AsynclistaddrR {
AsynclistaddrR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - Asynchronous List Address / Endpoint List Address"]
#[inline(always)]
pub fn asynclistaddr(&mut self) -> AsynclistaddrW<AsynclistaddrSpec> {
AsynclistaddrW::new(self, 0)
}
}
#[doc = "Asynchronous List Address / Endpoint List Address\n\nYou can [`read`](crate::Reg::read) this register and get [`asynclistaddr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`asynclistaddr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AsynclistaddrSpec;
impl crate::RegisterSpec for AsynclistaddrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`asynclistaddr::R`](R) reader structure"]
impl crate::Readable for AsynclistaddrSpec {}
#[doc = "`write(|w| ..)` method takes [`asynclistaddr::W`](W) writer structure"]
impl crate::Writable for AsynclistaddrSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ASYNCLISTADDR to value 0"]
impl crate::Resettable for AsynclistaddrSpec {}
}
#[doc = "BURSTSIZE (rw) register accessor: Programmable Burst Size\n\nYou can [`read`](crate::Reg::read) this register and get [`burstsize::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`burstsize::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@burstsize`] module"]
#[doc(alias = "BURSTSIZE")]
pub type Burstsize = crate::Reg<burstsize::BurstsizeSpec>;
#[doc = "Programmable Burst Size"]
pub mod burstsize {
#[doc = "Register `BURSTSIZE` reader"]
pub type R = crate::R<BurstsizeSpec>;
#[doc = "Register `BURSTSIZE` writer"]
pub type W = crate::W<BurstsizeSpec>;
#[doc = "Field `RXPBURST` reader - Programmable RX Burst Length"]
pub type RxpburstR = crate::FieldReader;
#[doc = "Field `RXPBURST` writer - Programmable RX Burst Length"]
pub type RxpburstW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `TXPBURST` reader - Programmable TX Burst Length"]
pub type TxpburstR = crate::FieldReader;
#[doc = "Field `TXPBURST` writer - Programmable TX Burst Length"]
pub type TxpburstW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:7 - Programmable RX Burst Length"]
#[inline(always)]
pub fn rxpburst(&self) -> RxpburstR {
RxpburstR::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:15 - Programmable TX Burst Length"]
#[inline(always)]
pub fn txpburst(&self) -> TxpburstR {
TxpburstR::new(((self.bits >> 8) & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:7 - Programmable RX Burst Length"]
#[inline(always)]
pub fn rxpburst(&mut self) -> RxpburstW<BurstsizeSpec> {
RxpburstW::new(self, 0)
}
#[doc = "Bits 8:15 - Programmable TX Burst Length"]
#[inline(always)]
pub fn txpburst(&mut self) -> TxpburstW<BurstsizeSpec> {
TxpburstW::new(self, 8)
}
}
#[doc = "Programmable Burst Size\n\nYou can [`read`](crate::Reg::read) this register and get [`burstsize::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`burstsize::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct BurstsizeSpec;
impl crate::RegisterSpec for BurstsizeSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`burstsize::R`](R) reader structure"]
impl crate::Readable for BurstsizeSpec {}
#[doc = "`write(|w| ..)` method takes [`burstsize::W`](W) writer structure"]
impl crate::Writable for BurstsizeSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets BURSTSIZE to value 0"]
impl crate::Resettable for BurstsizeSpec {}
}
#[doc = "TXFILLTUNING (rw) register accessor: Host Transmit Pre-Buffer Packet Tuning\n\nYou can [`read`](crate::Reg::read) this register and get [`txfilltuning::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txfilltuning::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txfilltuning`] module"]
#[doc(alias = "TXFILLTUNING")]
pub type Txfilltuning = crate::Reg<txfilltuning::TxfilltuningSpec>;
#[doc = "Host Transmit Pre-Buffer Packet Tuning"]
pub mod txfilltuning {
#[doc = "Register `TXFILLTUNING` reader"]
pub type R = crate::R<TxfilltuningSpec>;
#[doc = "Register `TXFILLTUNING` writer"]
pub type W = crate::W<TxfilltuningSpec>;
#[doc = "Field `TXSCHOH` reader - Scheduler Overhead"]
pub type TxschohR = crate::FieldReader;
#[doc = "Field `TXSCHOH` writer - Scheduler Overhead"]
pub type TxschohW<'a, REG> = crate::FieldWriter<'a, REG, 7>;
#[doc = "Field `TXSCHHEALTH` reader - Scheduler Health Counter"]
pub type TxschhealthR = crate::FieldReader;
#[doc = "Field `TXSCHHEALTH` writer - Scheduler Health Counter"]
pub type TxschhealthW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
#[doc = "Field `TXFIFOTHRES` reader - FIFO Burst Threshold"]
pub type TxfifothresR = crate::FieldReader;
#[doc = "Field `TXFIFOTHRES` writer - FIFO Burst Threshold"]
pub type TxfifothresW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
impl R {
#[doc = "Bits 0:6 - Scheduler Overhead"]
#[inline(always)]
pub fn txschoh(&self) -> TxschohR {
TxschohR::new((self.bits & 0x7f) as u8)
}
#[doc = "Bits 8:12 - Scheduler Health Counter"]
#[inline(always)]
pub fn txschhealth(&self) -> TxschhealthR {
TxschhealthR::new(((self.bits >> 8) & 0x1f) as u8)
}
#[doc = "Bits 16:21 - FIFO Burst Threshold"]
#[inline(always)]
pub fn txfifothres(&self) -> TxfifothresR {
TxfifothresR::new(((self.bits >> 16) & 0x3f) as u8)
}
}
impl W {
#[doc = "Bits 0:6 - Scheduler Overhead"]
#[inline(always)]
pub fn txschoh(&mut self) -> TxschohW<TxfilltuningSpec> {
TxschohW::new(self, 0)
}
#[doc = "Bits 8:12 - Scheduler Health Counter"]
#[inline(always)]
pub fn txschhealth(&mut self) -> TxschhealthW<TxfilltuningSpec> {
TxschhealthW::new(self, 8)
}
#[doc = "Bits 16:21 - FIFO Burst Threshold"]
#[inline(always)]
pub fn txfifothres(&mut self) -> TxfifothresW<TxfilltuningSpec> {
TxfifothresW::new(self, 16)
}
}
#[doc = "Host Transmit Pre-Buffer Packet Tuning\n\nYou can [`read`](crate::Reg::read) this register and get [`txfilltuning::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txfilltuning::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TxfilltuningSpec;
impl crate::RegisterSpec for TxfilltuningSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`txfilltuning::R`](R) reader structure"]
impl crate::Readable for TxfilltuningSpec {}
#[doc = "`write(|w| ..)` method takes [`txfilltuning::W`](W) writer structure"]
impl crate::Writable for TxfilltuningSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets TXFILLTUNING to value 0"]
impl crate::Resettable for TxfilltuningSpec {}
}
#[doc = "ENDPTNAK (rw) register accessor: Endpoint NAK\n\nYou can [`read`](crate::Reg::read) this register and get [`endptnak::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`endptnak::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@endptnak`] module"]
#[doc(alias = "ENDPTNAK")]
pub type Endptnak = crate::Reg<endptnak::EndptnakSpec>;
#[doc = "Endpoint NAK"]
pub mod endptnak {
#[doc = "Register `ENDPTNAK` reader"]
pub type R = crate::R<EndptnakSpec>;
#[doc = "Register `ENDPTNAK` writer"]
pub type W = crate::W<EndptnakSpec>;
#[doc = "Field `EPRN0` reader - Endpoing 0 RX NAK"]
pub type Eprn0R = crate::BitReader;
#[doc = "Field `EPRN0` writer - Endpoing 0 RX NAK"]
pub type Eprn0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EPRN1` reader - Endpoing 1 RX NAK"]
pub type Eprn1R = crate::BitReader;
#[doc = "Field `EPRN1` writer - Endpoing 1 RX NAK"]
pub type Eprn1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EPRN2` reader - Endpoing 2 RX NAK"]
pub type Eprn2R = crate::BitReader;
#[doc = "Field `EPRN2` writer - Endpoing 2 RX NAK"]
pub type Eprn2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EPRN3` reader - Endpoing 3 RX NAK"]
pub type Eprn3R = crate::BitReader;
#[doc = "Field `EPRN3` writer - Endpoing 3 RX NAK"]
pub type Eprn3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EPTN0` reader - Endpoing 0 TX NAK"]
pub type Eptn0R = crate::BitReader;
#[doc = "Field `EPTN0` writer - Endpoing 0 TX NAK"]
pub type Eptn0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EPTN1` reader - Endpoing 1 TX NAK"]
pub type Eptn1R = crate::BitReader;
#[doc = "Field `EPTN1` writer - Endpoing 1 TX NAK"]
pub type Eptn1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EPTN2` reader - Endpoing 2 TX NAK"]
pub type Eptn2R = crate::BitReader;
#[doc = "Field `EPTN2` writer - Endpoing 2 TX NAK"]
pub type Eptn2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EPTN3` reader - Endpoing 3 TX NAK"]
pub type Eptn3R = crate::BitReader;
#[doc = "Field `EPTN3` writer - Endpoing 3 TX NAK"]
pub type Eptn3W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - Endpoing 0 RX NAK"]
#[inline(always)]
pub fn eprn0(&self) -> Eprn0R {
Eprn0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Endpoing 1 RX NAK"]
#[inline(always)]
pub fn eprn1(&self) -> Eprn1R {
Eprn1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Endpoing 2 RX NAK"]
#[inline(always)]
pub fn eprn2(&self) -> Eprn2R {
Eprn2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Endpoing 3 RX NAK"]
#[inline(always)]
pub fn eprn3(&self) -> Eprn3R {
Eprn3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 16 - Endpoing 0 TX NAK"]
#[inline(always)]
pub fn eptn0(&self) -> Eptn0R {
Eptn0R::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 17 - Endpoing 1 TX NAK"]
#[inline(always)]
pub fn eptn1(&self) -> Eptn1R {
Eptn1R::new(((self.bits >> 17) & 1) != 0)
}
#[doc = "Bit 18 - Endpoing 2 TX NAK"]
#[inline(always)]
pub fn eptn2(&self) -> Eptn2R {
Eptn2R::new(((self.bits >> 18) & 1) != 0)
}
#[doc = "Bit 19 - Endpoing 3 TX NAK"]
#[inline(always)]
pub fn eptn3(&self) -> Eptn3R {
Eptn3R::new(((self.bits >> 19) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Endpoing 0 RX NAK"]
#[inline(always)]
pub fn eprn0(&mut self) -> Eprn0W<EndptnakSpec> {
Eprn0W::new(self, 0)
}
#[doc = "Bit 1 - Endpoing 1 RX NAK"]
#[inline(always)]
pub fn eprn1(&mut self) -> Eprn1W<EndptnakSpec> {
Eprn1W::new(self, 1)
}
#[doc = "Bit 2 - Endpoing 2 RX NAK"]
#[inline(always)]
pub fn eprn2(&mut self) -> Eprn2W<EndptnakSpec> {
Eprn2W::new(self, 2)
}
#[doc = "Bit 3 - Endpoing 3 RX NAK"]
#[inline(always)]
pub fn eprn3(&mut self) -> Eprn3W<EndptnakSpec> {
Eprn3W::new(self, 3)
}
#[doc = "Bit 16 - Endpoing 0 TX NAK"]
#[inline(always)]
pub fn eptn0(&mut self) -> Eptn0W<EndptnakSpec> {
Eptn0W::new(self, 16)
}
#[doc = "Bit 17 - Endpoing 1 TX NAK"]
#[inline(always)]
pub fn eptn1(&mut self) -> Eptn1W<EndptnakSpec> {
Eptn1W::new(self, 17)
}
#[doc = "Bit 18 - Endpoing 2 TX NAK"]
#[inline(always)]
pub fn eptn2(&mut self) -> Eptn2W<EndptnakSpec> {
Eptn2W::new(self, 18)
}
#[doc = "Bit 19 - Endpoing 3 TX NAK"]
#[inline(always)]
pub fn eptn3(&mut self) -> Eptn3W<EndptnakSpec> {
Eptn3W::new(self, 19)
}
}
#[doc = "Endpoint NAK\n\nYou can [`read`](crate::Reg::read) this register and get [`endptnak::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`endptnak::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EndptnakSpec;
impl crate::RegisterSpec for EndptnakSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`endptnak::R`](R) reader structure"]
impl crate::Readable for EndptnakSpec {}
#[doc = "`write(|w| ..)` method takes [`endptnak::W`](W) writer structure"]
impl crate::Writable for EndptnakSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ENDPTNAK to value 0"]
impl crate::Resettable for EndptnakSpec {}
}
#[doc = "ENDPTNAKEN (rw) register accessor: Endpoint NAK Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`endptnaken::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`endptnaken::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@endptnaken`] module"]
#[doc(alias = "ENDPTNAKEN")]
pub type Endptnaken = crate::Reg<endptnaken::EndptnakenSpec>;
#[doc = "Endpoint NAK Enable"]
pub mod endptnaken {
#[doc = "Register `ENDPTNAKEN` reader"]
pub type R = crate::R<EndptnakenSpec>;
#[doc = "Register `ENDPTNAKEN` writer"]
pub type W = crate::W<EndptnakenSpec>;
#[doc = "Field `EPRNE0` reader - RX Endpoint 0 NAK Interrupt Enable"]
pub type Eprne0R = crate::BitReader;
#[doc = "Field `EPRNE0` writer - RX Endpoint 0 NAK Interrupt Enable"]
pub type Eprne0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EPRNE1` reader - RX Endpoint 1 NAK Interrupt Enable"]
pub type Eprne1R = crate::BitReader;
#[doc = "Field `EPRNE1` writer - RX Endpoint 1 NAK Interrupt Enable"]
pub type Eprne1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EPRNE2` reader - RX Endpoint 2 NAK Interrupt Enable"]
pub type Eprne2R = crate::BitReader;
#[doc = "Field `EPRNE2` writer - RX Endpoint 2 NAK Interrupt Enable"]
pub type Eprne2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EPRNE3` reader - RX Endpoint 3 NAK Interrupt Enable"]
pub type Eprne3R = crate::BitReader;
#[doc = "Field `EPRNE3` writer - RX Endpoint 3 NAK Interrupt Enable"]
pub type Eprne3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EPTNE0` reader - TX Endpoint 0 NAK Interrupt Enable"]
pub type Eptne0R = crate::BitReader;
#[doc = "Field `EPTNE0` writer - TX Endpoint 0 NAK Interrupt Enable"]
pub type Eptne0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EPTNE1` reader - TX Endpoint 1 NAK Interrupt Enable"]
pub type Eptne1R = crate::BitReader;
#[doc = "Field `EPTNE1` writer - TX Endpoint 1 NAK Interrupt Enable"]
pub type Eptne1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EPTNE2` reader - TX Endpoint 2 NAK Interrupt Enable"]
pub type Eptne2R = crate::BitReader;
#[doc = "Field `EPTNE2` writer - TX Endpoint 2 NAK Interrupt Enable"]
pub type Eptne2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EPTNE3` reader - TX Endpoint 3 NAK Interrupt Enable"]
pub type Eptne3R = crate::BitReader;
#[doc = "Field `EPTNE3` writer - TX Endpoint 3 NAK Interrupt Enable"]
pub type Eptne3W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - RX Endpoint 0 NAK Interrupt Enable"]
#[inline(always)]
pub fn eprne0(&self) -> Eprne0R {
Eprne0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - RX Endpoint 1 NAK Interrupt Enable"]
#[inline(always)]
pub fn eprne1(&self) -> Eprne1R {
Eprne1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - RX Endpoint 2 NAK Interrupt Enable"]
#[inline(always)]
pub fn eprne2(&self) -> Eprne2R {
Eprne2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - RX Endpoint 3 NAK Interrupt Enable"]
#[inline(always)]
pub fn eprne3(&self) -> Eprne3R {
Eprne3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 16 - TX Endpoint 0 NAK Interrupt Enable"]
#[inline(always)]
pub fn eptne0(&self) -> Eptne0R {
Eptne0R::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 17 - TX Endpoint 1 NAK Interrupt Enable"]
#[inline(always)]
pub fn eptne1(&self) -> Eptne1R {
Eptne1R::new(((self.bits >> 17) & 1) != 0)
}
#[doc = "Bit 18 - TX Endpoint 2 NAK Interrupt Enable"]
#[inline(always)]
pub fn eptne2(&self) -> Eptne2R {
Eptne2R::new(((self.bits >> 18) & 1) != 0)
}
#[doc = "Bit 19 - TX Endpoint 3 NAK Interrupt Enable"]
#[inline(always)]
pub fn eptne3(&self) -> Eptne3R {
Eptne3R::new(((self.bits >> 19) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - RX Endpoint 0 NAK Interrupt Enable"]
#[inline(always)]
pub fn eprne0(&mut self) -> Eprne0W<EndptnakenSpec> {
Eprne0W::new(self, 0)
}
#[doc = "Bit 1 - RX Endpoint 1 NAK Interrupt Enable"]
#[inline(always)]
pub fn eprne1(&mut self) -> Eprne1W<EndptnakenSpec> {
Eprne1W::new(self, 1)
}
#[doc = "Bit 2 - RX Endpoint 2 NAK Interrupt Enable"]
#[inline(always)]
pub fn eprne2(&mut self) -> Eprne2W<EndptnakenSpec> {
Eprne2W::new(self, 2)
}
#[doc = "Bit 3 - RX Endpoint 3 NAK Interrupt Enable"]
#[inline(always)]
pub fn eprne3(&mut self) -> Eprne3W<EndptnakenSpec> {
Eprne3W::new(self, 3)
}
#[doc = "Bit 16 - TX Endpoint 0 NAK Interrupt Enable"]
#[inline(always)]
pub fn eptne0(&mut self) -> Eptne0W<EndptnakenSpec> {
Eptne0W::new(self, 16)
}
#[doc = "Bit 17 - TX Endpoint 1 NAK Interrupt Enable"]
#[inline(always)]
pub fn eptne1(&mut self) -> Eptne1W<EndptnakenSpec> {
Eptne1W::new(self, 17)
}
#[doc = "Bit 18 - TX Endpoint 2 NAK Interrupt Enable"]
#[inline(always)]
pub fn eptne2(&mut self) -> Eptne2W<EndptnakenSpec> {
Eptne2W::new(self, 18)
}
#[doc = "Bit 19 - TX Endpoint 3 NAK Interrupt Enable"]
#[inline(always)]
pub fn eptne3(&mut self) -> Eptne3W<EndptnakenSpec> {
Eptne3W::new(self, 19)
}
}
#[doc = "Endpoint NAK Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`endptnaken::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`endptnaken::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EndptnakenSpec;
impl crate::RegisterSpec for EndptnakenSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`endptnaken::R`](R) reader structure"]
impl crate::Readable for EndptnakenSpec {}
#[doc = "`write(|w| ..)` method takes [`endptnaken::W`](W) writer structure"]
impl crate::Writable for EndptnakenSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ENDPTNAKEN to value 0"]
impl crate::Resettable for EndptnakenSpec {}
}
#[doc = "PORTSC (rw) register accessor: Port Status/Control\n\nYou can [`read`](crate::Reg::read) this register and get [`portsc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`portsc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@portsc`] module"]
#[doc(alias = "PORTSC")]
pub type Portsc = crate::Reg<portsc::PortscSpec>;
#[doc = "Port Status/Control"]
pub mod portsc {
#[doc = "Register `PORTSC` reader"]
pub type R = crate::R<PortscSpec>;
#[doc = "Register `PORTSC` writer"]
pub type W = crate::W<PortscSpec>;
#[doc = "Current Connect Status\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Ccs {
#[doc = "0: No Device"]
NoDevice = 0,
#[doc = "1: Device Attached"]
DeviceAttached = 1,
}
impl From<Ccs> for bool {
#[inline(always)]
fn from(variant: Ccs) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `CCS` reader - Current Connect Status"]
pub type CcsR = crate::BitReader<Ccs>;
impl CcsR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Ccs {
match self.bits {
false => Ccs::NoDevice,
true => Ccs::DeviceAttached,
}
}
#[doc = "No Device"]
#[inline(always)]
pub fn is_no_device(&self) -> bool {
*self == Ccs::NoDevice
}
#[doc = "Device Attached"]
#[inline(always)]
pub fn is_device_attached(&self) -> bool {
*self == Ccs::DeviceAttached
}
}
#[doc = "Field `CSC` reader - Connect Status Change"]
pub type CscR = crate::BitReader;
#[doc = "Field `CSC` writer - Connect Status Change"]
pub type CscW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PE` reader - Port Enabled"]
pub type PeR = crate::BitReader;
#[doc = "Field `PE` writer - Port Enabled"]
pub type PeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PEC` reader - Port Enabled Change"]
pub type PecR = crate::BitReader;
#[doc = "Field `PEC` writer - Port Enabled Change"]
pub type PecW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OCA` reader - Over-current Active"]
pub type OcaR = crate::BitReader;
#[doc = "Field `OCC` reader - Over-current Change"]
pub type OccR = crate::BitReader;
#[doc = "Field `OCC` writer - Over-current Change"]
pub type OccW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `FPR` reader - Force Port Resume"]
pub type FprR = crate::BitReader;
#[doc = "Field `FPR` writer - Force Port Resume"]
pub type FprW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SUSP` reader - Suspend"]
pub type SuspR = crate::BitReader;
#[doc = "Field `SUSP` writer - Suspend"]
pub type SuspW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PR` reader - Port Reset"]
pub type PrR = crate::BitReader;
#[doc = "Field `PR` writer - Port Reset"]
pub type PrW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `HSP` reader - High-Speed Port"]
pub type HspR = crate::BitReader;
#[doc = "Line Status\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Ls {
#[doc = "0: SE0"]
Se0 = 0,
#[doc = "1: J-state"]
Jstate = 1,
#[doc = "2: K-state"]
Kstate = 2,
}
impl From<Ls> for u8 {
#[inline(always)]
fn from(variant: Ls) -> Self {
variant as _
}
}
impl crate::FieldSpec for Ls {
type Ux = u8;
}
impl crate::IsEnum for Ls {}
#[doc = "Field `LS` reader - Line Status"]
pub type LsR = crate::FieldReader<Ls>;
impl LsR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<Ls> {
match self.bits {
0 => Some(Ls::Se0),
1 => Some(Ls::Jstate),
2 => Some(Ls::Kstate),
_ => None,
}
}
#[doc = "SE0"]
#[inline(always)]
pub fn is_se0(&self) -> bool {
*self == Ls::Se0
}
#[doc = "J-state"]
#[inline(always)]
pub fn is_jstate(&self) -> bool {
*self == Ls::Jstate
}
#[doc = "K-state"]
#[inline(always)]
pub fn is_kstate(&self) -> bool {
*self == Ls::Kstate
}
}
#[doc = "Field `PP` reader - Port Power"]
pub type PpR = crate::BitReader;
#[doc = "Field `PP` writer - Port Power"]
pub type PpW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PO` reader - Port Owner"]
pub type PoR = crate::BitReader;
#[doc = "Field `PIC` reader - Port Indicator Control"]
pub type PicR = crate::FieldReader;
#[doc = "Field `PIC` writer - Port Indicator Control"]
pub type PicW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `PTC` reader - Port Test Control"]
pub type PtcR = crate::FieldReader;
#[doc = "Field `PTC` writer - Port Test Control"]
pub type PtcW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `WKCN` reader - Wake on Connect Enable"]
pub type WkcnR = crate::BitReader;
#[doc = "Field `WKCN` writer - Wake on Connect Enable"]
pub type WkcnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `WKDS` reader - Wake on Disconnect Enable"]
pub type WkdsR = crate::BitReader;
#[doc = "Field `WKDS` writer - Wake on Disconnect Enable"]
pub type WkdsW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `WKOC` reader - Wake on Over-current Enable"]
pub type WkocR = crate::BitReader;
#[doc = "Field `WKOC` writer - Wake on Over-current Enable"]
pub type WkocW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PHCD` reader - PHY Low Power Clock Disable"]
pub type PhcdR = crate::BitReader;
#[doc = "Field `PHCD` writer - PHY Low Power Clock Disable"]
pub type PhcdW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Port Speed\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Pspd {
#[doc = "0: Full Speed"]
FullSpeed = 0,
#[doc = "1: Low Speed"]
LowSpeed = 1,
#[doc = "2: High Speed"]
HighSpeed = 2,
#[doc = "3: Not Connected"]
NotConnected = 3,
}
impl From<Pspd> for u8 {
#[inline(always)]
fn from(variant: Pspd) -> Self {
variant as _
}
}
impl crate::FieldSpec for Pspd {
type Ux = u8;
}
impl crate::IsEnum for Pspd {}
#[doc = "Field `PSPD` reader - Port Speed"]
pub type PspdR = crate::FieldReader<Pspd>;
impl PspdR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Pspd {
match self.bits {
0 => Pspd::FullSpeed,
1 => Pspd::LowSpeed,
2 => Pspd::HighSpeed,
3 => Pspd::NotConnected,
_ => unreachable!(),
}
}
#[doc = "Full Speed"]
#[inline(always)]
pub fn is_full_speed(&self) -> bool {
*self == Pspd::FullSpeed
}
#[doc = "Low Speed"]
#[inline(always)]
pub fn is_low_speed(&self) -> bool {
*self == Pspd::LowSpeed
}
#[doc = "High Speed"]
#[inline(always)]
pub fn is_high_speed(&self) -> bool {
*self == Pspd::HighSpeed
}
#[doc = "Not Connected"]
#[inline(always)]
pub fn is_not_connected(&self) -> bool {
*self == Pspd::NotConnected
}
}
#[doc = "Field `PSPD` writer - Port Speed"]
pub type PspdW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pspd, crate::Safe>;
impl<'a, REG> PspdW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Full Speed"]
#[inline(always)]
pub fn full_speed(self) -> &'a mut crate::W<REG> {
self.variant(Pspd::FullSpeed)
}
#[doc = "Low Speed"]
#[inline(always)]
pub fn low_speed(self) -> &'a mut crate::W<REG> {
self.variant(Pspd::LowSpeed)
}
#[doc = "High Speed"]
#[inline(always)]
pub fn high_speed(self) -> &'a mut crate::W<REG> {
self.variant(Pspd::HighSpeed)
}
#[doc = "Not Connected"]
#[inline(always)]
pub fn not_connected(self) -> &'a mut crate::W<REG> {
self.variant(Pspd::NotConnected)
}
}
impl R {
#[doc = "Bit 0 - Current Connect Status"]
#[inline(always)]
pub fn ccs(&self) -> CcsR {
CcsR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Connect Status Change"]
#[inline(always)]
pub fn csc(&self) -> CscR {
CscR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Port Enabled"]
#[inline(always)]
pub fn pe(&self) -> PeR {
PeR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Port Enabled Change"]
#[inline(always)]
pub fn pec(&self) -> PecR {
PecR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Over-current Active"]
#[inline(always)]
pub fn oca(&self) -> OcaR {
OcaR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Over-current Change"]
#[inline(always)]
pub fn occ(&self) -> OccR {
OccR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Force Port Resume"]
#[inline(always)]
pub fn fpr(&self) -> FprR {
FprR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Suspend"]
#[inline(always)]
pub fn susp(&self) -> SuspR {
SuspR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - Port Reset"]
#[inline(always)]
pub fn pr(&self) -> PrR {
PrR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - High-Speed Port"]
#[inline(always)]
pub fn hsp(&self) -> HspR {
HspR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bits 10:11 - Line Status"]
#[inline(always)]
pub fn ls(&self) -> LsR {
LsR::new(((self.bits >> 10) & 3) as u8)
}
#[doc = "Bit 12 - Port Power"]
#[inline(always)]
pub fn pp(&self) -> PpR {
PpR::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13 - Port Owner"]
#[inline(always)]
pub fn po(&self) -> PoR {
PoR::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bits 14:15 - Port Indicator Control"]
#[inline(always)]
pub fn pic(&self) -> PicR {
PicR::new(((self.bits >> 14) & 3) as u8)
}
#[doc = "Bits 16:19 - Port Test Control"]
#[inline(always)]
pub fn ptc(&self) -> PtcR {
PtcR::new(((self.bits >> 16) & 0x0f) as u8)
}
#[doc = "Bit 20 - Wake on Connect Enable"]
#[inline(always)]
pub fn wkcn(&self) -> WkcnR {
WkcnR::new(((self.bits >> 20) & 1) != 0)
}
#[doc = "Bit 21 - Wake on Disconnect Enable"]
#[inline(always)]
pub fn wkds(&self) -> WkdsR {
WkdsR::new(((self.bits >> 21) & 1) != 0)
}
#[doc = "Bit 22 - Wake on Over-current Enable"]
#[inline(always)]
pub fn wkoc(&self) -> WkocR {
WkocR::new(((self.bits >> 22) & 1) != 0)
}
#[doc = "Bit 23 - PHY Low Power Clock Disable"]
#[inline(always)]
pub fn phcd(&self) -> PhcdR {
PhcdR::new(((self.bits >> 23) & 1) != 0)
}
#[doc = "Bits 26:27 - Port Speed"]
#[inline(always)]
pub fn pspd(&self) -> PspdR {
PspdR::new(((self.bits >> 26) & 3) as u8)
}
}
impl W {
#[doc = "Bit 1 - Connect Status Change"]
#[inline(always)]
pub fn csc(&mut self) -> CscW<PortscSpec> {
CscW::new(self, 1)
}
#[doc = "Bit 2 - Port Enabled"]
#[inline(always)]
pub fn pe(&mut self) -> PeW<PortscSpec> {
PeW::new(self, 2)
}
#[doc = "Bit 3 - Port Enabled Change"]
#[inline(always)]
pub fn pec(&mut self) -> PecW<PortscSpec> {
PecW::new(self, 3)
}
#[doc = "Bit 5 - Over-current Change"]
#[inline(always)]
pub fn occ(&mut self) -> OccW<PortscSpec> {
OccW::new(self, 5)
}
#[doc = "Bit 6 - Force Port Resume"]
#[inline(always)]
pub fn fpr(&mut self) -> FprW<PortscSpec> {
FprW::new(self, 6)
}
#[doc = "Bit 7 - Suspend"]
#[inline(always)]
pub fn susp(&mut self) -> SuspW<PortscSpec> {
SuspW::new(self, 7)
}
#[doc = "Bit 8 - Port Reset"]
#[inline(always)]
pub fn pr(&mut self) -> PrW<PortscSpec> {
PrW::new(self, 8)
}
#[doc = "Bit 12 - Port Power"]
#[inline(always)]
pub fn pp(&mut self) -> PpW<PortscSpec> {
PpW::new(self, 12)
}
#[doc = "Bits 14:15 - Port Indicator Control"]
#[inline(always)]
pub fn pic(&mut self) -> PicW<PortscSpec> {
PicW::new(self, 14)
}
#[doc = "Bits 16:19 - Port Test Control"]
#[inline(always)]
pub fn ptc(&mut self) -> PtcW<PortscSpec> {
PtcW::new(self, 16)
}
#[doc = "Bit 20 - Wake on Connect Enable"]
#[inline(always)]
pub fn wkcn(&mut self) -> WkcnW<PortscSpec> {
WkcnW::new(self, 20)
}
#[doc = "Bit 21 - Wake on Disconnect Enable"]
#[inline(always)]
pub fn wkds(&mut self) -> WkdsW<PortscSpec> {
WkdsW::new(self, 21)
}
#[doc = "Bit 22 - Wake on Over-current Enable"]
#[inline(always)]
pub fn wkoc(&mut self) -> WkocW<PortscSpec> {
WkocW::new(self, 22)
}
#[doc = "Bit 23 - PHY Low Power Clock Disable"]
#[inline(always)]
pub fn phcd(&mut self) -> PhcdW<PortscSpec> {
PhcdW::new(self, 23)
}
#[doc = "Bits 26:27 - Port Speed"]
#[inline(always)]
pub fn pspd(&mut self) -> PspdW<PortscSpec> {
PspdW::new(self, 26)
}
}
#[doc = "Port Status/Control\n\nYou can [`read`](crate::Reg::read) this register and get [`portsc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`portsc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PortscSpec;
impl crate::RegisterSpec for PortscSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`portsc::R`](R) reader structure"]
impl crate::Readable for PortscSpec {}
#[doc = "`write(|w| ..)` method takes [`portsc::W`](W) writer structure"]
impl crate::Writable for PortscSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets PORTSC to value 0"]
impl crate::Resettable for PortscSpec {}
}
#[doc = "OTGSC (rw) register accessor: OTG Status and Control\n\nYou can [`read`](crate::Reg::read) this register and get [`otgsc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`otgsc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@otgsc`] module"]
#[doc(alias = "OTGSC")]
pub type Otgsc = crate::Reg<otgsc::OtgscSpec>;
#[doc = "OTG Status and Control"]
pub mod otgsc {
#[doc = "Register `OTGSC` reader"]
pub type R = crate::R<OtgscSpec>;
#[doc = "Register `OTGSC` writer"]
pub type W = crate::W<OtgscSpec>;
#[doc = "Field `HAAR` reader - Hardware Assist Auto-Reset"]
pub type HaarR = crate::BitReader;
#[doc = "Field `HAAR` writer - Hardware Assist Auto-Reset"]
pub type HaarW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DP` reader - Data Pulsing"]
pub type DpR = crate::BitReader;
#[doc = "Field `DP` writer - Data Pulsing"]
pub type DpW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `HADP` reader - Hardware Assist Data-Pulse"]
pub type HadpR = crate::BitReader;
#[doc = "Field `HADP` writer - Hardware Assist Data-Pulse"]
pub type HadpW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "USB ID\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Id {
#[doc = "0: A-device"]
Adevice = 0,
#[doc = "1: B-device"]
Bdevice = 1,
}
impl From<Id> for bool {
#[inline(always)]
fn from(variant: Id) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `ID` reader - USB ID"]
pub type IdR = crate::BitReader<Id>;
impl IdR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Id {
match self.bits {
false => Id::Adevice,
true => Id::Bdevice,
}
}
#[doc = "A-device"]
#[inline(always)]
pub fn is_adevice(&self) -> bool {
*self == Id::Adevice
}
#[doc = "B-device"]
#[inline(always)]
pub fn is_bdevice(&self) -> bool {
*self == Id::Bdevice
}
}
#[doc = "Field `AVV` reader - A VBus Valid"]
pub type AvvR = crate::BitReader;
#[doc = "Field `ASV` reader - A Session Valid"]
pub type AsvR = crate::BitReader;
#[doc = "Field `BSV` reader - B Session Valid"]
pub type BsvR = crate::BitReader;
#[doc = "Field `BSE` reader - B Session End"]
pub type BseR = crate::BitReader;
#[doc = "Field `1msT` reader - 1 millisecond timer toggle"]
pub type _1msTR = crate::BitReader;
#[doc = "Field `DPS` reader - Data Bus Pulsing Status"]
pub type DpsR = crate::BitReader;
#[doc = "Field `IDIS` reader - USB ID Interrupt Status"]
pub type IdisR = crate::BitReader;
#[doc = "Field `IDIS` writer - USB ID Interrupt Status"]
pub type IdisW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `1msS` reader - 1 millisecond timer Interrupt Status"]
pub type _1msSR = crate::BitReader;
#[doc = "Field `1msS` writer - 1 millisecond timer Interrupt Status"]
pub type _1msSW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DPIS` reader - Data Pulse Interrupt Status"]
pub type DpisR = crate::BitReader;
#[doc = "Field `DPIS` writer - Data Pulse Interrupt Status"]
pub type DpisW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IDIE` reader - USB ID Interrupt Enable"]
pub type IdieR = crate::BitReader;
#[doc = "Field `IDIE` writer - USB ID Interrupt Enable"]
pub type IdieW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `1msE` reader - 1 millisecond timer Interrupt Enable"]
pub type _1msER = crate::BitReader;
#[doc = "Field `1msE` writer - 1 millisecond timer Interrupt Enable"]
pub type _1msEW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DPIE` reader - Data Pulse Interrupt Enable"]
pub type DpieR = crate::BitReader;
#[doc = "Field `DPIE` writer - Data Pulse Interrupt Enable"]
pub type DpieW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 2 - Hardware Assist Auto-Reset"]
#[inline(always)]
pub fn haar(&self) -> HaarR {
HaarR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 4 - Data Pulsing"]
#[inline(always)]
pub fn dp(&self) -> DpR {
DpR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 6 - Hardware Assist Data-Pulse"]
#[inline(always)]
pub fn hadp(&self) -> HadpR {
HadpR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 8 - USB ID"]
#[inline(always)]
pub fn id(&self) -> IdR {
IdR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - A VBus Valid"]
#[inline(always)]
pub fn avv(&self) -> AvvR {
AvvR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - A Session Valid"]
#[inline(always)]
pub fn asv(&self) -> AsvR {
AsvR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - B Session Valid"]
#[inline(always)]
pub fn bsv(&self) -> BsvR {
BsvR::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 12 - B Session End"]
#[inline(always)]
pub fn bse(&self) -> BseR {
BseR::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13 - 1 millisecond timer toggle"]
#[inline(always)]
pub fn _1ms_t(&self) -> _1msTR {
_1msTR::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - Data Bus Pulsing Status"]
#[inline(always)]
pub fn dps(&self) -> DpsR {
DpsR::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 16 - USB ID Interrupt Status"]
#[inline(always)]
pub fn idis(&self) -> IdisR {
IdisR::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 21 - 1 millisecond timer Interrupt Status"]
#[inline(always)]
pub fn _1ms_s(&self) -> _1msSR {
_1msSR::new(((self.bits >> 21) & 1) != 0)
}
#[doc = "Bit 22 - Data Pulse Interrupt Status"]
#[inline(always)]
pub fn dpis(&self) -> DpisR {
DpisR::new(((self.bits >> 22) & 1) != 0)
}
#[doc = "Bit 24 - USB ID Interrupt Enable"]
#[inline(always)]
pub fn idie(&self) -> IdieR {
IdieR::new(((self.bits >> 24) & 1) != 0)
}
#[doc = "Bit 29 - 1 millisecond timer Interrupt Enable"]
#[inline(always)]
pub fn _1ms_e(&self) -> _1msER {
_1msER::new(((self.bits >> 29) & 1) != 0)
}
#[doc = "Bit 30 - Data Pulse Interrupt Enable"]
#[inline(always)]
pub fn dpie(&self) -> DpieR {
DpieR::new(((self.bits >> 30) & 1) != 0)
}
}
impl W {
#[doc = "Bit 2 - Hardware Assist Auto-Reset"]
#[inline(always)]
pub fn haar(&mut self) -> HaarW<OtgscSpec> {
HaarW::new(self, 2)
}
#[doc = "Bit 4 - Data Pulsing"]
#[inline(always)]
pub fn dp(&mut self) -> DpW<OtgscSpec> {
DpW::new(self, 4)
}
#[doc = "Bit 6 - Hardware Assist Data-Pulse"]
#[inline(always)]
pub fn hadp(&mut self) -> HadpW<OtgscSpec> {
HadpW::new(self, 6)
}
#[doc = "Bit 16 - USB ID Interrupt Status"]
#[inline(always)]
pub fn idis(&mut self) -> IdisW<OtgscSpec> {
IdisW::new(self, 16)
}
#[doc = "Bit 21 - 1 millisecond timer Interrupt Status"]
#[inline(always)]
pub fn _1ms_s(&mut self) -> _1msSW<OtgscSpec> {
_1msSW::new(self, 21)
}
#[doc = "Bit 22 - Data Pulse Interrupt Status"]
#[inline(always)]
pub fn dpis(&mut self) -> DpisW<OtgscSpec> {
DpisW::new(self, 22)
}
#[doc = "Bit 24 - USB ID Interrupt Enable"]
#[inline(always)]
pub fn idie(&mut self) -> IdieW<OtgscSpec> {
IdieW::new(self, 24)
}
#[doc = "Bit 29 - 1 millisecond timer Interrupt Enable"]
#[inline(always)]
pub fn _1ms_e(&mut self) -> _1msEW<OtgscSpec> {
_1msEW::new(self, 29)
}
#[doc = "Bit 30 - Data Pulse Interrupt Enable"]
#[inline(always)]
pub fn dpie(&mut self) -> DpieW<OtgscSpec> {
DpieW::new(self, 30)
}
}
#[doc = "OTG Status and Control\n\nYou can [`read`](crate::Reg::read) this register and get [`otgsc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`otgsc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OtgscSpec;
impl crate::RegisterSpec for OtgscSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`otgsc::R`](R) reader structure"]
impl crate::Readable for OtgscSpec {}
#[doc = "`write(|w| ..)` method takes [`otgsc::W`](W) writer structure"]
impl crate::Writable for OtgscSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets OTGSC to value 0"]
impl crate::Resettable for OtgscSpec {}
}
#[doc = "USBMODE (rw) register accessor: USB Device Mode\n\nYou can [`read`](crate::Reg::read) this register and get [`usbmode::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usbmode::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@usbmode`] module"]
#[doc(alias = "USBMODE")]
pub type Usbmode = crate::Reg<usbmode::UsbmodeSpec>;
#[doc = "USB Device Mode"]
pub mod usbmode {
#[doc = "Register `USBMODE` reader"]
pub type R = crate::R<UsbmodeSpec>;
#[doc = "Register `USBMODE` writer"]
pub type W = crate::W<UsbmodeSpec>;
#[doc = "Controller Mode\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Cm {
#[doc = "0: Idle"]
Idle = 0,
#[doc = "2: Device Mode"]
DeviceMode = 2,
#[doc = "3: Host Mode"]
HostMode = 3,
}
impl From<Cm> for u8 {
#[inline(always)]
fn from(variant: Cm) -> Self {
variant as _
}
}
impl crate::FieldSpec for Cm {
type Ux = u8;
}
impl crate::IsEnum for Cm {}
#[doc = "Field `CM` reader - Controller Mode"]
pub type CmR = crate::FieldReader<Cm>;
impl CmR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<Cm> {
match self.bits {
0 => Some(Cm::Idle),
2 => Some(Cm::DeviceMode),
3 => Some(Cm::HostMode),
_ => None,
}
}
#[doc = "Idle"]
#[inline(always)]
pub fn is_idle(&self) -> bool {
*self == Cm::Idle
}
#[doc = "Device Mode"]
#[inline(always)]
pub fn is_device_mode(&self) -> bool {
*self == Cm::DeviceMode
}
#[doc = "Host Mode"]
#[inline(always)]
pub fn is_host_mode(&self) -> bool {
*self == Cm::HostMode
}
}
#[doc = "Field `CM` writer - Controller Mode"]
pub type CmW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cm>;
impl<'a, REG> CmW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Idle"]
#[inline(always)]
pub fn idle(self) -> &'a mut crate::W<REG> {
self.variant(Cm::Idle)
}
#[doc = "Device Mode"]
#[inline(always)]
pub fn device_mode(self) -> &'a mut crate::W<REG> {
self.variant(Cm::DeviceMode)
}
#[doc = "Host Mode"]
#[inline(always)]
pub fn host_mode(self) -> &'a mut crate::W<REG> {
self.variant(Cm::HostMode)
}
}
#[doc = "Endian Select\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Es {
#[doc = "0: LE"]
Le = 0,
#[doc = "1: BE"]
Be = 1,
}
impl From<Es> for bool {
#[inline(always)]
fn from(variant: Es) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `ES` reader - Endian Select"]
pub type EsR = crate::BitReader<Es>;
impl EsR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Es {
match self.bits {
false => Es::Le,
true => Es::Be,
}
}
#[doc = "LE"]
#[inline(always)]
pub fn is_le(&self) -> bool {
*self == Es::Le
}
#[doc = "BE"]
#[inline(always)]
pub fn is_be(&self) -> bool {
*self == Es::Be
}
}
#[doc = "Field `ES` writer - Endian Select"]
pub type EsW<'a, REG> = crate::BitWriter<'a, REG, Es>;
impl<'a, REG> EsW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "LE"]
#[inline(always)]
pub fn le(self) -> &'a mut crate::W<REG> {
self.variant(Es::Le)
}
#[doc = "BE"]
#[inline(always)]
pub fn be(self) -> &'a mut crate::W<REG> {
self.variant(Es::Be)
}
}
#[doc = "Setup Lockout Mode\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Slom {
#[doc = "0: ON"]
On = 0,
#[doc = "1: OFF"]
Off = 1,
}
impl From<Slom> for bool {
#[inline(always)]
fn from(variant: Slom) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `SLOM` reader - Setup Lockout Mode"]
pub type SlomR = crate::BitReader<Slom>;
impl SlomR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Slom {
match self.bits {
false => Slom::On,
true => Slom::Off,
}
}
#[doc = "ON"]
#[inline(always)]
pub fn is_on(&self) -> bool {
*self == Slom::On
}
#[doc = "OFF"]
#[inline(always)]
pub fn is_off(&self) -> bool {
*self == Slom::Off
}
}
#[doc = "Field `SLOM` writer - Setup Lockout Mode"]
pub type SlomW<'a, REG> = crate::BitWriter<'a, REG, Slom>;
impl<'a, REG> SlomW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "ON"]
#[inline(always)]
pub fn on(self) -> &'a mut crate::W<REG> {
self.variant(Slom::On)
}
#[doc = "OFF"]
#[inline(always)]
pub fn off(self) -> &'a mut crate::W<REG> {
self.variant(Slom::Off)
}
}
impl R {
#[doc = "Bits 0:1 - Controller Mode"]
#[inline(always)]
pub fn cm(&self) -> CmR {
CmR::new((self.bits & 3) as u8)
}
#[doc = "Bit 2 - Endian Select"]
#[inline(always)]
pub fn es(&self) -> EsR {
EsR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Setup Lockout Mode"]
#[inline(always)]
pub fn slom(&self) -> SlomR {
SlomR::new(((self.bits >> 3) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:1 - Controller Mode"]
#[inline(always)]
pub fn cm(&mut self) -> CmW<UsbmodeSpec> {
CmW::new(self, 0)
}
#[doc = "Bit 2 - Endian Select"]
#[inline(always)]
pub fn es(&mut self) -> EsW<UsbmodeSpec> {
EsW::new(self, 2)
}
#[doc = "Bit 3 - Setup Lockout Mode"]
#[inline(always)]
pub fn slom(&mut self) -> SlomW<UsbmodeSpec> {
SlomW::new(self, 3)
}
}
#[doc = "USB Device Mode\n\nYou can [`read`](crate::Reg::read) this register and get [`usbmode::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usbmode::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct UsbmodeSpec;
impl crate::RegisterSpec for UsbmodeSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`usbmode::R`](R) reader structure"]
impl crate::Readable for UsbmodeSpec {}
#[doc = "`write(|w| ..)` method takes [`usbmode::W`](W) writer structure"]
impl crate::Writable for UsbmodeSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets USBMODE to value 0"]
impl crate::Resettable for UsbmodeSpec {}
}
#[doc = "ENDPTSETUPSTAT (rw) register accessor: Endpoint Setup Status\n\nYou can [`read`](crate::Reg::read) this register and get [`endptsetupstat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`endptsetupstat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@endptsetupstat`] module"]
#[doc(alias = "ENDPTSETUPSTAT")]
pub type Endptsetupstat = crate::Reg<endptsetupstat::EndptsetupstatSpec>;
#[doc = "Endpoint Setup Status"]
pub mod endptsetupstat {
#[doc = "Register `ENDPTSETUPSTAT` reader"]
pub type R = crate::R<EndptsetupstatSpec>;
#[doc = "Register `ENDPTSETUPSTAT` writer"]
pub type W = crate::W<EndptsetupstatSpec>;
#[doc = "Field `ENDPTSETUPSTAT0` reader - Endpoing 0 Setup Status"]
pub type Endptsetupstat0R = crate::BitReader;
#[doc = "Field `ENDPTSETUPSTAT0` writer - Endpoing 0 Setup Status"]
pub type Endptsetupstat0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ENDPTSETUPSTAT1` reader - Endpoing 1 Setup Status"]
pub type Endptsetupstat1R = crate::BitReader;
#[doc = "Field `ENDPTSETUPSTAT1` writer - Endpoing 1 Setup Status"]
pub type Endptsetupstat1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ENDPTSETUPSTAT2` reader - Endpoing 2 Setup Status"]
pub type Endptsetupstat2R = crate::BitReader;
#[doc = "Field `ENDPTSETUPSTAT2` writer - Endpoing 2 Setup Status"]
pub type Endptsetupstat2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ENDPTSETUPSTAT3` reader - Endpoing 3 Setup Status"]
pub type Endptsetupstat3R = crate::BitReader;
#[doc = "Field `ENDPTSETUPSTAT3` writer - Endpoing 3 Setup Status"]
pub type Endptsetupstat3W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - Endpoing 0 Setup Status"]
#[inline(always)]
pub fn endptsetupstat0(&self) -> Endptsetupstat0R {
Endptsetupstat0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Endpoing 1 Setup Status"]
#[inline(always)]
pub fn endptsetupstat1(&self) -> Endptsetupstat1R {
Endptsetupstat1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Endpoing 2 Setup Status"]
#[inline(always)]
pub fn endptsetupstat2(&self) -> Endptsetupstat2R {
Endptsetupstat2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Endpoing 3 Setup Status"]
#[inline(always)]
pub fn endptsetupstat3(&self) -> Endptsetupstat3R {
Endptsetupstat3R::new(((self.bits >> 3) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Endpoing 0 Setup Status"]
#[inline(always)]
pub fn endptsetupstat0(&mut self) -> Endptsetupstat0W<EndptsetupstatSpec> {
Endptsetupstat0W::new(self, 0)
}
#[doc = "Bit 1 - Endpoing 1 Setup Status"]
#[inline(always)]
pub fn endptsetupstat1(&mut self) -> Endptsetupstat1W<EndptsetupstatSpec> {
Endptsetupstat1W::new(self, 1)
}
#[doc = "Bit 2 - Endpoing 2 Setup Status"]
#[inline(always)]
pub fn endptsetupstat2(&mut self) -> Endptsetupstat2W<EndptsetupstatSpec> {
Endptsetupstat2W::new(self, 2)
}
#[doc = "Bit 3 - Endpoing 3 Setup Status"]
#[inline(always)]
pub fn endptsetupstat3(&mut self) -> Endptsetupstat3W<EndptsetupstatSpec> {
Endptsetupstat3W::new(self, 3)
}
}
#[doc = "Endpoint Setup Status\n\nYou can [`read`](crate::Reg::read) this register and get [`endptsetupstat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`endptsetupstat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EndptsetupstatSpec;
impl crate::RegisterSpec for EndptsetupstatSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`endptsetupstat::R`](R) reader structure"]
impl crate::Readable for EndptsetupstatSpec {}
#[doc = "`write(|w| ..)` method takes [`endptsetupstat::W`](W) writer structure"]
impl crate::Writable for EndptsetupstatSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ENDPTSETUPSTAT to value 0"]
impl crate::Resettable for EndptsetupstatSpec {}
}
#[doc = "ENDPTPRIME (rw) register accessor: Endpoint Initialization\n\nYou can [`read`](crate::Reg::read) this register and get [`endptprime::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`endptprime::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@endptprime`] module"]
#[doc(alias = "ENDPTPRIME")]
pub type Endptprime = crate::Reg<endptprime::EndptprimeSpec>;
#[doc = "Endpoint Initialization"]
pub mod endptprime {
#[doc = "Register `ENDPTPRIME` reader"]
pub type R = crate::R<EndptprimeSpec>;
#[doc = "Register `ENDPTPRIME` writer"]
pub type W = crate::W<EndptprimeSpec>;
#[doc = "Field `PERB0` reader - Prime Endpoint 0 RX Buffer"]
pub type Perb0R = crate::BitReader;
#[doc = "Field `PERB0` writer - Prime Endpoint 0 RX Buffer"]
pub type Perb0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PERB1` reader - Prime Endpoint 1 RX Buffer"]
pub type Perb1R = crate::BitReader;
#[doc = "Field `PERB1` writer - Prime Endpoint 1 RX Buffer"]
pub type Perb1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PERB2` reader - Prime Endpoint 2 RX Buffer"]
pub type Perb2R = crate::BitReader;
#[doc = "Field `PERB2` writer - Prime Endpoint 2 RX Buffer"]
pub type Perb2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PERB3` reader - Prime Endpoint 3 RX Buffer"]
pub type Perb3R = crate::BitReader;
#[doc = "Field `PERB3` writer - Prime Endpoint 3 RX Buffer"]
pub type Perb3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PETB0` reader - Prime Endpoint 0 TX Buffer"]
pub type Petb0R = crate::BitReader;
#[doc = "Field `PETB0` writer - Prime Endpoint 0 TX Buffer"]
pub type Petb0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PETB1` reader - Prime Endpoint 1 TX Buffer"]
pub type Petb1R = crate::BitReader;
#[doc = "Field `PETB1` writer - Prime Endpoint 1 TX Buffer"]
pub type Petb1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PETB2` reader - Prime Endpoint 2 TX Buffer"]
pub type Petb2R = crate::BitReader;
#[doc = "Field `PETB2` writer - Prime Endpoint 2 TX Buffer"]
pub type Petb2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PETB3` reader - Prime Endpoint 3 TX Buffer"]
pub type Petb3R = crate::BitReader;
#[doc = "Field `PETB3` writer - Prime Endpoint 3 TX Buffer"]
pub type Petb3W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - Prime Endpoint 0 RX Buffer"]
#[inline(always)]
pub fn perb0(&self) -> Perb0R {
Perb0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Prime Endpoint 1 RX Buffer"]
#[inline(always)]
pub fn perb1(&self) -> Perb1R {
Perb1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Prime Endpoint 2 RX Buffer"]
#[inline(always)]
pub fn perb2(&self) -> Perb2R {
Perb2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Prime Endpoint 3 RX Buffer"]
#[inline(always)]
pub fn perb3(&self) -> Perb3R {
Perb3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 16 - Prime Endpoint 0 TX Buffer"]
#[inline(always)]
pub fn petb0(&self) -> Petb0R {
Petb0R::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 17 - Prime Endpoint 1 TX Buffer"]
#[inline(always)]
pub fn petb1(&self) -> Petb1R {
Petb1R::new(((self.bits >> 17) & 1) != 0)
}
#[doc = "Bit 18 - Prime Endpoint 2 TX Buffer"]
#[inline(always)]
pub fn petb2(&self) -> Petb2R {
Petb2R::new(((self.bits >> 18) & 1) != 0)
}
#[doc = "Bit 19 - Prime Endpoint 3 TX Buffer"]
#[inline(always)]
pub fn petb3(&self) -> Petb3R {
Petb3R::new(((self.bits >> 19) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Prime Endpoint 0 RX Buffer"]
#[inline(always)]
pub fn perb0(&mut self) -> Perb0W<EndptprimeSpec> {
Perb0W::new(self, 0)
}
#[doc = "Bit 1 - Prime Endpoint 1 RX Buffer"]
#[inline(always)]
pub fn perb1(&mut self) -> Perb1W<EndptprimeSpec> {
Perb1W::new(self, 1)
}
#[doc = "Bit 2 - Prime Endpoint 2 RX Buffer"]
#[inline(always)]
pub fn perb2(&mut self) -> Perb2W<EndptprimeSpec> {
Perb2W::new(self, 2)
}
#[doc = "Bit 3 - Prime Endpoint 3 RX Buffer"]
#[inline(always)]
pub fn perb3(&mut self) -> Perb3W<EndptprimeSpec> {
Perb3W::new(self, 3)
}
#[doc = "Bit 16 - Prime Endpoint 0 TX Buffer"]
#[inline(always)]
pub fn petb0(&mut self) -> Petb0W<EndptprimeSpec> {
Petb0W::new(self, 16)
}
#[doc = "Bit 17 - Prime Endpoint 1 TX Buffer"]
#[inline(always)]
pub fn petb1(&mut self) -> Petb1W<EndptprimeSpec> {
Petb1W::new(self, 17)
}
#[doc = "Bit 18 - Prime Endpoint 2 TX Buffer"]
#[inline(always)]
pub fn petb2(&mut self) -> Petb2W<EndptprimeSpec> {
Petb2W::new(self, 18)
}
#[doc = "Bit 19 - Prime Endpoint 3 TX Buffer"]
#[inline(always)]
pub fn petb3(&mut self) -> Petb3W<EndptprimeSpec> {
Petb3W::new(self, 19)
}
}
#[doc = "Endpoint Initialization\n\nYou can [`read`](crate::Reg::read) this register and get [`endptprime::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`endptprime::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EndptprimeSpec;
impl crate::RegisterSpec for EndptprimeSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`endptprime::R`](R) reader structure"]
impl crate::Readable for EndptprimeSpec {}
#[doc = "`write(|w| ..)` method takes [`endptprime::W`](W) writer structure"]
impl crate::Writable for EndptprimeSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ENDPTPRIME to value 0"]
impl crate::Resettable for EndptprimeSpec {}
}
#[doc = "ENDPTFLUSH (rw) register accessor: Endpoint De-Initialize\n\nYou can [`read`](crate::Reg::read) this register and get [`endptflush::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`endptflush::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@endptflush`] module"]
#[doc(alias = "ENDPTFLUSH")]
pub type Endptflush = crate::Reg<endptflush::EndptflushSpec>;
#[doc = "Endpoint De-Initialize"]
pub mod endptflush {
#[doc = "Register `ENDPTFLUSH` reader"]
pub type R = crate::R<EndptflushSpec>;
#[doc = "Register `ENDPTFLUSH` writer"]
pub type W = crate::W<EndptflushSpec>;
#[doc = "Field `FERB0` reader - Flush Endpoint 0 RX Buffer"]
pub type Ferb0R = crate::BitReader;
#[doc = "Field `FERB0` writer - Flush Endpoint 0 RX Buffer"]
pub type Ferb0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `FERB1` reader - Flush Endpoint 1 RX Buffer"]
pub type Ferb1R = crate::BitReader;
#[doc = "Field `FERB1` writer - Flush Endpoint 1 RX Buffer"]
pub type Ferb1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `FERB2` reader - Flush Endpoint 2 RX Buffer"]
pub type Ferb2R = crate::BitReader;
#[doc = "Field `FERB2` writer - Flush Endpoint 2 RX Buffer"]
pub type Ferb2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `FERB3` reader - Flush Endpoint 3 RX Buffer"]
pub type Ferb3R = crate::BitReader;
#[doc = "Field `FERB3` writer - Flush Endpoint 3 RX Buffer"]
pub type Ferb3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `FETB0` reader - Flush Endpoint 0 TX Buffer"]
pub type Fetb0R = crate::BitReader;
#[doc = "Field `FETB0` writer - Flush Endpoint 0 TX Buffer"]
pub type Fetb0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `FETB1` reader - Flush Endpoint 1 TX Buffer"]
pub type Fetb1R = crate::BitReader;
#[doc = "Field `FETB1` writer - Flush Endpoint 1 TX Buffer"]
pub type Fetb1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `FETB2` reader - Flush Endpoint 2 TX Buffer"]
pub type Fetb2R = crate::BitReader;
#[doc = "Field `FETB2` writer - Flush Endpoint 2 TX Buffer"]
pub type Fetb2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `FETB3` reader - Flush Endpoint 3 TX Buffer"]
pub type Fetb3R = crate::BitReader;
#[doc = "Field `FETB3` writer - Flush Endpoint 3 TX Buffer"]
pub type Fetb3W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - Flush Endpoint 0 RX Buffer"]
#[inline(always)]
pub fn ferb0(&self) -> Ferb0R {
Ferb0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Flush Endpoint 1 RX Buffer"]
#[inline(always)]
pub fn ferb1(&self) -> Ferb1R {
Ferb1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Flush Endpoint 2 RX Buffer"]
#[inline(always)]
pub fn ferb2(&self) -> Ferb2R {
Ferb2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Flush Endpoint 3 RX Buffer"]
#[inline(always)]
pub fn ferb3(&self) -> Ferb3R {
Ferb3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 16 - Flush Endpoint 0 TX Buffer"]
#[inline(always)]
pub fn fetb0(&self) -> Fetb0R {
Fetb0R::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 17 - Flush Endpoint 1 TX Buffer"]
#[inline(always)]
pub fn fetb1(&self) -> Fetb1R {
Fetb1R::new(((self.bits >> 17) & 1) != 0)
}
#[doc = "Bit 18 - Flush Endpoint 2 TX Buffer"]
#[inline(always)]
pub fn fetb2(&self) -> Fetb2R {
Fetb2R::new(((self.bits >> 18) & 1) != 0)
}
#[doc = "Bit 19 - Flush Endpoint 3 TX Buffer"]
#[inline(always)]
pub fn fetb3(&self) -> Fetb3R {
Fetb3R::new(((self.bits >> 19) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Flush Endpoint 0 RX Buffer"]
#[inline(always)]
pub fn ferb0(&mut self) -> Ferb0W<EndptflushSpec> {
Ferb0W::new(self, 0)
}
#[doc = "Bit 1 - Flush Endpoint 1 RX Buffer"]
#[inline(always)]
pub fn ferb1(&mut self) -> Ferb1W<EndptflushSpec> {
Ferb1W::new(self, 1)
}
#[doc = "Bit 2 - Flush Endpoint 2 RX Buffer"]
#[inline(always)]
pub fn ferb2(&mut self) -> Ferb2W<EndptflushSpec> {
Ferb2W::new(self, 2)
}
#[doc = "Bit 3 - Flush Endpoint 3 RX Buffer"]
#[inline(always)]
pub fn ferb3(&mut self) -> Ferb3W<EndptflushSpec> {
Ferb3W::new(self, 3)
}
#[doc = "Bit 16 - Flush Endpoint 0 TX Buffer"]
#[inline(always)]
pub fn fetb0(&mut self) -> Fetb0W<EndptflushSpec> {
Fetb0W::new(self, 16)
}
#[doc = "Bit 17 - Flush Endpoint 1 TX Buffer"]
#[inline(always)]
pub fn fetb1(&mut self) -> Fetb1W<EndptflushSpec> {
Fetb1W::new(self, 17)
}
#[doc = "Bit 18 - Flush Endpoint 2 TX Buffer"]
#[inline(always)]
pub fn fetb2(&mut self) -> Fetb2W<EndptflushSpec> {
Fetb2W::new(self, 18)
}
#[doc = "Bit 19 - Flush Endpoint 3 TX Buffer"]
#[inline(always)]
pub fn fetb3(&mut self) -> Fetb3W<EndptflushSpec> {
Fetb3W::new(self, 19)
}
}
#[doc = "Endpoint De-Initialize\n\nYou can [`read`](crate::Reg::read) this register and get [`endptflush::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`endptflush::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EndptflushSpec;
impl crate::RegisterSpec for EndptflushSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`endptflush::R`](R) reader structure"]
impl crate::Readable for EndptflushSpec {}
#[doc = "`write(|w| ..)` method takes [`endptflush::W`](W) writer structure"]
impl crate::Writable for EndptflushSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ENDPTFLUSH to value 0"]
impl crate::Resettable for EndptflushSpec {}
}
#[doc = "ENDPTSTATUS (rw) register accessor: Endpoint Status\n\nYou can [`read`](crate::Reg::read) this register and get [`endptstatus::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`endptstatus::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@endptstatus`] module"]
#[doc(alias = "ENDPTSTATUS")]
pub type Endptstatus = crate::Reg<endptstatus::EndptstatusSpec>;
#[doc = "Endpoint Status"]
pub mod endptstatus {
#[doc = "Register `ENDPTSTATUS` reader"]
pub type R = crate::R<EndptstatusSpec>;
#[doc = "Register `ENDPTSTATUS` writer"]
pub type W = crate::W<EndptstatusSpec>;
#[doc = "Field `ERBR0` reader - Endpoint 0 RX Buffer Ready"]
pub type Erbr0R = crate::BitReader;
#[doc = "Field `ERBR0` writer - Endpoint 0 RX Buffer Ready"]
pub type Erbr0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ERBR1` reader - Endpoint 1 RX Buffer Ready"]
pub type Erbr1R = crate::BitReader;
#[doc = "Field `ERBR1` writer - Endpoint 1 RX Buffer Ready"]
pub type Erbr1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ERBR2` reader - Endpoint 2 RX Buffer Ready"]
pub type Erbr2R = crate::BitReader;
#[doc = "Field `ERBR2` writer - Endpoint 2 RX Buffer Ready"]
pub type Erbr2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ERBR3` reader - Endpoint 3 RX Buffer Ready"]
pub type Erbr3R = crate::BitReader;
#[doc = "Field `ERBR3` writer - Endpoint 3 RX Buffer Ready"]
pub type Erbr3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ETBR0` reader - Endpoint 0 TX Buffer Ready"]
pub type Etbr0R = crate::BitReader;
#[doc = "Field `ETBR0` writer - Endpoint 0 TX Buffer Ready"]
pub type Etbr0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ETBR1` reader - Endpoint 1 TX Buffer Ready"]
pub type Etbr1R = crate::BitReader;
#[doc = "Field `ETBR1` writer - Endpoint 1 TX Buffer Ready"]
pub type Etbr1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ETBR2` reader - Endpoint 2 TX Buffer Ready"]
pub type Etbr2R = crate::BitReader;
#[doc = "Field `ETBR2` writer - Endpoint 2 TX Buffer Ready"]
pub type Etbr2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ETBR3` reader - Endpoint 3 TX Buffer Ready"]
pub type Etbr3R = crate::BitReader;
#[doc = "Field `ETBR3` writer - Endpoint 3 TX Buffer Ready"]
pub type Etbr3W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - Endpoint 0 RX Buffer Ready"]
#[inline(always)]
pub fn erbr0(&self) -> Erbr0R {
Erbr0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Endpoint 1 RX Buffer Ready"]
#[inline(always)]
pub fn erbr1(&self) -> Erbr1R {
Erbr1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Endpoint 2 RX Buffer Ready"]
#[inline(always)]
pub fn erbr2(&self) -> Erbr2R {
Erbr2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Endpoint 3 RX Buffer Ready"]
#[inline(always)]
pub fn erbr3(&self) -> Erbr3R {
Erbr3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 16 - Endpoint 0 TX Buffer Ready"]
#[inline(always)]
pub fn etbr0(&self) -> Etbr0R {
Etbr0R::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 17 - Endpoint 1 TX Buffer Ready"]
#[inline(always)]
pub fn etbr1(&self) -> Etbr1R {
Etbr1R::new(((self.bits >> 17) & 1) != 0)
}
#[doc = "Bit 18 - Endpoint 2 TX Buffer Ready"]
#[inline(always)]
pub fn etbr2(&self) -> Etbr2R {
Etbr2R::new(((self.bits >> 18) & 1) != 0)
}
#[doc = "Bit 19 - Endpoint 3 TX Buffer Ready"]
#[inline(always)]
pub fn etbr3(&self) -> Etbr3R {
Etbr3R::new(((self.bits >> 19) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Endpoint 0 RX Buffer Ready"]
#[inline(always)]
pub fn erbr0(&mut self) -> Erbr0W<EndptstatusSpec> {
Erbr0W::new(self, 0)
}
#[doc = "Bit 1 - Endpoint 1 RX Buffer Ready"]
#[inline(always)]
pub fn erbr1(&mut self) -> Erbr1W<EndptstatusSpec> {
Erbr1W::new(self, 1)
}
#[doc = "Bit 2 - Endpoint 2 RX Buffer Ready"]
#[inline(always)]
pub fn erbr2(&mut self) -> Erbr2W<EndptstatusSpec> {
Erbr2W::new(self, 2)
}
#[doc = "Bit 3 - Endpoint 3 RX Buffer Ready"]
#[inline(always)]
pub fn erbr3(&mut self) -> Erbr3W<EndptstatusSpec> {
Erbr3W::new(self, 3)
}
#[doc = "Bit 16 - Endpoint 0 TX Buffer Ready"]
#[inline(always)]
pub fn etbr0(&mut self) -> Etbr0W<EndptstatusSpec> {
Etbr0W::new(self, 16)
}
#[doc = "Bit 17 - Endpoint 1 TX Buffer Ready"]
#[inline(always)]
pub fn etbr1(&mut self) -> Etbr1W<EndptstatusSpec> {
Etbr1W::new(self, 17)
}
#[doc = "Bit 18 - Endpoint 2 TX Buffer Ready"]
#[inline(always)]
pub fn etbr2(&mut self) -> Etbr2W<EndptstatusSpec> {
Etbr2W::new(self, 18)
}
#[doc = "Bit 19 - Endpoint 3 TX Buffer Ready"]
#[inline(always)]
pub fn etbr3(&mut self) -> Etbr3W<EndptstatusSpec> {
Etbr3W::new(self, 19)
}
}
#[doc = "Endpoint Status\n\nYou can [`read`](crate::Reg::read) this register and get [`endptstatus::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`endptstatus::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EndptstatusSpec;
impl crate::RegisterSpec for EndptstatusSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`endptstatus::R`](R) reader structure"]
impl crate::Readable for EndptstatusSpec {}
#[doc = "`write(|w| ..)` method takes [`endptstatus::W`](W) writer structure"]
impl crate::Writable for EndptstatusSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ENDPTSTATUS to value 0"]
impl crate::Resettable for EndptstatusSpec {}
}
#[doc = "ENDPTCOMPLETE (rw) register accessor: Endpoint Complete\n\nYou can [`read`](crate::Reg::read) this register and get [`endptcomplete::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`endptcomplete::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@endptcomplete`] module"]
#[doc(alias = "ENDPTCOMPLETE")]
pub type Endptcomplete = crate::Reg<endptcomplete::EndptcompleteSpec>;
#[doc = "Endpoint Complete"]
pub mod endptcomplete {
#[doc = "Register `ENDPTCOMPLETE` reader"]
pub type R = crate::R<EndptcompleteSpec>;
#[doc = "Register `ENDPTCOMPLETE` writer"]
pub type W = crate::W<EndptcompleteSpec>;
#[doc = "Field `ERCE0` reader - Endpoint 0 RX Complete Event"]
pub type Erce0R = crate::BitReader;
#[doc = "Field `ERCE0` writer - Endpoint 0 RX Complete Event"]
pub type Erce0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ERCE1` reader - Endpoint 1 RX Complete Event"]
pub type Erce1R = crate::BitReader;
#[doc = "Field `ERCE1` writer - Endpoint 1 RX Complete Event"]
pub type Erce1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ERCE2` reader - Endpoint 2 RX Complete Event"]
pub type Erce2R = crate::BitReader;
#[doc = "Field `ERCE2` writer - Endpoint 2 RX Complete Event"]
pub type Erce2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ERCE3` reader - Endpoint 3 RX Complete Event"]
pub type Erce3R = crate::BitReader;
#[doc = "Field `ERCE3` writer - Endpoint 3 RX Complete Event"]
pub type Erce3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ETCE0` reader - Endpoint 0 TX Complete Event"]
pub type Etce0R = crate::BitReader;
#[doc = "Field `ETCE0` writer - Endpoint 0 TX Complete Event"]
pub type Etce0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ETCE1` reader - Endpoint 1 TX Complete Event"]
pub type Etce1R = crate::BitReader;
#[doc = "Field `ETCE1` writer - Endpoint 1 TX Complete Event"]
pub type Etce1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ETCE2` reader - Endpoint 2 TX Complete Event"]
pub type Etce2R = crate::BitReader;
#[doc = "Field `ETCE2` writer - Endpoint 2 TX Complete Event"]
pub type Etce2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ETCE3` reader - Endpoint 3 TX Complete Event"]
pub type Etce3R = crate::BitReader;
#[doc = "Field `ETCE3` writer - Endpoint 3 TX Complete Event"]
pub type Etce3W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - Endpoint 0 RX Complete Event"]
#[inline(always)]
pub fn erce0(&self) -> Erce0R {
Erce0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Endpoint 1 RX Complete Event"]
#[inline(always)]
pub fn erce1(&self) -> Erce1R {
Erce1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Endpoint 2 RX Complete Event"]
#[inline(always)]
pub fn erce2(&self) -> Erce2R {
Erce2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Endpoint 3 RX Complete Event"]
#[inline(always)]
pub fn erce3(&self) -> Erce3R {
Erce3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 16 - Endpoint 0 TX Complete Event"]
#[inline(always)]
pub fn etce0(&self) -> Etce0R {
Etce0R::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 17 - Endpoint 1 TX Complete Event"]
#[inline(always)]
pub fn etce1(&self) -> Etce1R {
Etce1R::new(((self.bits >> 17) & 1) != 0)
}
#[doc = "Bit 18 - Endpoint 2 TX Complete Event"]
#[inline(always)]
pub fn etce2(&self) -> Etce2R {
Etce2R::new(((self.bits >> 18) & 1) != 0)
}
#[doc = "Bit 19 - Endpoint 3 TX Complete Event"]
#[inline(always)]
pub fn etce3(&self) -> Etce3R {
Etce3R::new(((self.bits >> 19) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Endpoint 0 RX Complete Event"]
#[inline(always)]
pub fn erce0(&mut self) -> Erce0W<EndptcompleteSpec> {
Erce0W::new(self, 0)
}
#[doc = "Bit 1 - Endpoint 1 RX Complete Event"]
#[inline(always)]
pub fn erce1(&mut self) -> Erce1W<EndptcompleteSpec> {
Erce1W::new(self, 1)
}
#[doc = "Bit 2 - Endpoint 2 RX Complete Event"]
#[inline(always)]
pub fn erce2(&mut self) -> Erce2W<EndptcompleteSpec> {
Erce2W::new(self, 2)
}
#[doc = "Bit 3 - Endpoint 3 RX Complete Event"]
#[inline(always)]
pub fn erce3(&mut self) -> Erce3W<EndptcompleteSpec> {
Erce3W::new(self, 3)
}
#[doc = "Bit 16 - Endpoint 0 TX Complete Event"]
#[inline(always)]
pub fn etce0(&mut self) -> Etce0W<EndptcompleteSpec> {
Etce0W::new(self, 16)
}
#[doc = "Bit 17 - Endpoint 1 TX Complete Event"]
#[inline(always)]
pub fn etce1(&mut self) -> Etce1W<EndptcompleteSpec> {
Etce1W::new(self, 17)
}
#[doc = "Bit 18 - Endpoint 2 TX Complete Event"]
#[inline(always)]
pub fn etce2(&mut self) -> Etce2W<EndptcompleteSpec> {
Etce2W::new(self, 18)
}
#[doc = "Bit 19 - Endpoint 3 TX Complete Event"]
#[inline(always)]
pub fn etce3(&mut self) -> Etce3W<EndptcompleteSpec> {
Etce3W::new(self, 19)
}
}
#[doc = "Endpoint Complete\n\nYou can [`read`](crate::Reg::read) this register and get [`endptcomplete::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`endptcomplete::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EndptcompleteSpec;
impl crate::RegisterSpec for EndptcompleteSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`endptcomplete::R`](R) reader structure"]
impl crate::Readable for EndptcompleteSpec {}
#[doc = "`write(|w| ..)` method takes [`endptcomplete::W`](W) writer structure"]
impl crate::Writable for EndptcompleteSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ENDPTCOMPLETE to value 0"]
impl crate::Resettable for EndptcompleteSpec {}
}
#[doc = "ENDPTCTRL0 (rw) register accessor: Endpoint 0 Control\n\nYou can [`read`](crate::Reg::read) this register and get [`endptctrl0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`endptctrl0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@endptctrl0`] module"]
#[doc(alias = "ENDPTCTRL0")]
pub type Endptctrl0 = crate::Reg<endptctrl0::Endptctrl0Spec>;
#[doc = "Endpoint 0 Control"]
pub mod endptctrl0 {
#[doc = "Register `ENDPTCTRL0` reader"]
pub type R = crate::R<Endptctrl0Spec>;
#[doc = "Register `ENDPTCTRL0` writer"]
pub type W = crate::W<Endptctrl0Spec>;
#[doc = "Field `RXS` reader - RX Endpoint Stall"]
pub type RxsR = crate::BitReader;
#[doc = "Field `RXS` writer - RX Endpoint Stall"]
pub type RxsW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "RX Endpoint Type\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Rxt {
#[doc = "0: Control"]
Control = 0,
#[doc = "1: Isochronous"]
Isochronous = 1,
#[doc = "2: Bulk"]
Bulk = 2,
#[doc = "3: Interrupt"]
Interrupt = 3,
}
impl From<Rxt> for u8 {
#[inline(always)]
fn from(variant: Rxt) -> Self {
variant as _
}
}
impl crate::FieldSpec for Rxt {
type Ux = u8;
}
impl crate::IsEnum for Rxt {}
#[doc = "Field `RXT` reader - RX Endpoint Type"]
pub type RxtR = crate::FieldReader<Rxt>;
impl RxtR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Rxt {
match self.bits {
0 => Rxt::Control,
1 => Rxt::Isochronous,
2 => Rxt::Bulk,
3 => Rxt::Interrupt,
_ => unreachable!(),
}
}
#[doc = "Control"]
#[inline(always)]
pub fn is_control(&self) -> bool {
*self == Rxt::Control
}
#[doc = "Isochronous"]
#[inline(always)]
pub fn is_isochronous(&self) -> bool {
*self == Rxt::Isochronous
}
#[doc = "Bulk"]
#[inline(always)]
pub fn is_bulk(&self) -> bool {
*self == Rxt::Bulk
}
#[doc = "Interrupt"]
#[inline(always)]
pub fn is_interrupt(&self) -> bool {
*self == Rxt::Interrupt
}
}
#[doc = "Field `RXT` writer - RX Endpoint Type"]
pub type RxtW<'a, REG> = crate::FieldWriter<'a, REG, 2, Rxt, crate::Safe>;
impl<'a, REG> RxtW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Control"]
#[inline(always)]
pub fn control(self) -> &'a mut crate::W<REG> {
self.variant(Rxt::Control)
}
#[doc = "Isochronous"]
#[inline(always)]
pub fn isochronous(self) -> &'a mut crate::W<REG> {
self.variant(Rxt::Isochronous)
}
#[doc = "Bulk"]
#[inline(always)]
pub fn bulk(self) -> &'a mut crate::W<REG> {
self.variant(Rxt::Bulk)
}
#[doc = "Interrupt"]
#[inline(always)]
pub fn interrupt(self) -> &'a mut crate::W<REG> {
self.variant(Rxt::Interrupt)
}
}
#[doc = "Field `RXI` reader - RX Data Toggle Inhibit"]
pub type RxiR = crate::BitReader;
#[doc = "Field `RXI` writer - RX Data Toggle Inhibit"]
pub type RxiW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RXR` reader - RX Data Toggle Reset"]
pub type RxrR = crate::BitReader;
#[doc = "Field `RXR` writer - RX Data Toggle Reset"]
pub type RxrW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RXE` reader - RX Endpoint Enable"]
pub type RxeR = crate::BitReader;
#[doc = "Field `RXE` writer - RX Endpoint Enable"]
pub type RxeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TXS` reader - TX Endpoint Stall"]
pub type TxsR = crate::BitReader;
#[doc = "Field `TXS` writer - TX Endpoint Stall"]
pub type TxsW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "TX Endpoint Type\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Txt {
#[doc = "0: Control"]
Control = 0,
#[doc = "1: Isochronous"]
Isochronous = 1,
#[doc = "2: Bulk"]
Bulk = 2,
#[doc = "3: Interrupt"]
Interrupt = 3,
}
impl From<Txt> for u8 {
#[inline(always)]
fn from(variant: Txt) -> Self {
variant as _
}
}
impl crate::FieldSpec for Txt {
type Ux = u8;
}
impl crate::IsEnum for Txt {}
#[doc = "Field `TXT` reader - TX Endpoint Type"]
pub type TxtR = crate::FieldReader<Txt>;
impl TxtR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Txt {
match self.bits {
0 => Txt::Control,
1 => Txt::Isochronous,
2 => Txt::Bulk,
3 => Txt::Interrupt,
_ => unreachable!(),
}
}
#[doc = "Control"]
#[inline(always)]
pub fn is_control(&self) -> bool {
*self == Txt::Control
}
#[doc = "Isochronous"]
#[inline(always)]
pub fn is_isochronous(&self) -> bool {
*self == Txt::Isochronous
}
#[doc = "Bulk"]
#[inline(always)]
pub fn is_bulk(&self) -> bool {
*self == Txt::Bulk
}
#[doc = "Interrupt"]
#[inline(always)]
pub fn is_interrupt(&self) -> bool {
*self == Txt::Interrupt
}
}
#[doc = "Field `TXT` writer - TX Endpoint Type"]
pub type TxtW<'a, REG> = crate::FieldWriter<'a, REG, 2, Txt, crate::Safe>;
impl<'a, REG> TxtW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Control"]
#[inline(always)]
pub fn control(self) -> &'a mut crate::W<REG> {
self.variant(Txt::Control)
}
#[doc = "Isochronous"]
#[inline(always)]
pub fn isochronous(self) -> &'a mut crate::W<REG> {
self.variant(Txt::Isochronous)
}
#[doc = "Bulk"]
#[inline(always)]
pub fn bulk(self) -> &'a mut crate::W<REG> {
self.variant(Txt::Bulk)
}
#[doc = "Interrupt"]
#[inline(always)]
pub fn interrupt(self) -> &'a mut crate::W<REG> {
self.variant(Txt::Interrupt)
}
}
#[doc = "Field `TXI` reader - TX Data Toggle Inhibit"]
pub type TxiR = crate::BitReader;
#[doc = "Field `TXI` writer - TX Data Toggle Inhibit"]
pub type TxiW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TXR` reader - TX Data Toggle Reset"]
pub type TxrR = crate::BitReader;
#[doc = "Field `TXR` writer - TX Data Toggle Reset"]
pub type TxrW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TXE` reader - TX Endpoint Enable"]
pub type TxeR = crate::BitReader;
#[doc = "Field `TXE` writer - TX Endpoint Enable"]
pub type TxeW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - RX Endpoint Stall"]
#[inline(always)]
pub fn rxs(&self) -> RxsR {
RxsR::new((self.bits & 1) != 0)
}
#[doc = "Bits 2:3 - RX Endpoint Type"]
#[inline(always)]
pub fn rxt(&self) -> RxtR {
RxtR::new(((self.bits >> 2) & 3) as u8)
}
#[doc = "Bit 5 - RX Data Toggle Inhibit"]
#[inline(always)]
pub fn rxi(&self) -> RxiR {
RxiR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - RX Data Toggle Reset"]
#[inline(always)]
pub fn rxr(&self) -> RxrR {
RxrR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - RX Endpoint Enable"]
#[inline(always)]
pub fn rxe(&self) -> RxeR {
RxeR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 16 - TX Endpoint Stall"]
#[inline(always)]
pub fn txs(&self) -> TxsR {
TxsR::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bits 18:19 - TX Endpoint Type"]
#[inline(always)]
pub fn txt(&self) -> TxtR {
TxtR::new(((self.bits >> 18) & 3) as u8)
}
#[doc = "Bit 21 - TX Data Toggle Inhibit"]
#[inline(always)]
pub fn txi(&self) -> TxiR {
TxiR::new(((self.bits >> 21) & 1) != 0)
}
#[doc = "Bit 22 - TX Data Toggle Reset"]
#[inline(always)]
pub fn txr(&self) -> TxrR {
TxrR::new(((self.bits >> 22) & 1) != 0)
}
#[doc = "Bit 23 - TX Endpoint Enable"]
#[inline(always)]
pub fn txe(&self) -> TxeR {
TxeR::new(((self.bits >> 23) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - RX Endpoint Stall"]
#[inline(always)]
pub fn rxs(&mut self) -> RxsW<Endptctrl0Spec> {
RxsW::new(self, 0)
}
#[doc = "Bits 2:3 - RX Endpoint Type"]
#[inline(always)]
pub fn rxt(&mut self) -> RxtW<Endptctrl0Spec> {
RxtW::new(self, 2)
}
#[doc = "Bit 5 - RX Data Toggle Inhibit"]
#[inline(always)]
pub fn rxi(&mut self) -> RxiW<Endptctrl0Spec> {
RxiW::new(self, 5)
}
#[doc = "Bit 6 - RX Data Toggle Reset"]
#[inline(always)]
pub fn rxr(&mut self) -> RxrW<Endptctrl0Spec> {
RxrW::new(self, 6)
}
#[doc = "Bit 7 - RX Endpoint Enable"]
#[inline(always)]
pub fn rxe(&mut self) -> RxeW<Endptctrl0Spec> {
RxeW::new(self, 7)
}
#[doc = "Bit 16 - TX Endpoint Stall"]
#[inline(always)]
pub fn txs(&mut self) -> TxsW<Endptctrl0Spec> {
TxsW::new(self, 16)
}
#[doc = "Bits 18:19 - TX Endpoint Type"]
#[inline(always)]
pub fn txt(&mut self) -> TxtW<Endptctrl0Spec> {
TxtW::new(self, 18)
}
#[doc = "Bit 21 - TX Data Toggle Inhibit"]
#[inline(always)]
pub fn txi(&mut self) -> TxiW<Endptctrl0Spec> {
TxiW::new(self, 21)
}
#[doc = "Bit 22 - TX Data Toggle Reset"]
#[inline(always)]
pub fn txr(&mut self) -> TxrW<Endptctrl0Spec> {
TxrW::new(self, 22)
}
#[doc = "Bit 23 - TX Endpoint Enable"]
#[inline(always)]
pub fn txe(&mut self) -> TxeW<Endptctrl0Spec> {
TxeW::new(self, 23)
}
}
#[doc = "Endpoint 0 Control\n\nYou can [`read`](crate::Reg::read) this register and get [`endptctrl0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`endptctrl0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Endptctrl0Spec;
impl crate::RegisterSpec for Endptctrl0Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`endptctrl0::R`](R) reader structure"]
impl crate::Readable for Endptctrl0Spec {}
#[doc = "`write(|w| ..)` method takes [`endptctrl0::W`](W) writer structure"]
impl crate::Writable for Endptctrl0Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ENDPTCTRL0 to value 0"]
impl crate::Resettable for Endptctrl0Spec {}
}
#[doc = "ENDPTCTRL1 (rw) register accessor: Endpoint 1 Control\n\nYou can [`read`](crate::Reg::read) this register and get [`endptctrl1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`endptctrl1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@endptctrl1`] module"]
#[doc(alias = "ENDPTCTRL1")]
pub type Endptctrl1 = crate::Reg<endptctrl1::Endptctrl1Spec>;
#[doc = "Endpoint 1 Control"]
pub mod endptctrl1 {
#[doc = "Register `ENDPTCTRL1` reader"]
pub type R = crate::R<Endptctrl1Spec>;
#[doc = "Register `ENDPTCTRL1` writer"]
pub type W = crate::W<Endptctrl1Spec>;
#[doc = "Field `RXS` reader - RX Endpoint Stall"]
pub type RxsR = crate::BitReader;
#[doc = "Field `RXS` writer - RX Endpoint Stall"]
pub type RxsW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "RX Endpoint Type\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Rxt {
#[doc = "0: Control"]
Control = 0,
#[doc = "1: Isochronous"]
Isochronous = 1,
#[doc = "2: Bulk"]
Bulk = 2,
#[doc = "3: Interrupt"]
Interrupt = 3,
}
impl From<Rxt> for u8 {
#[inline(always)]
fn from(variant: Rxt) -> Self {
variant as _
}
}
impl crate::FieldSpec for Rxt {
type Ux = u8;
}
impl crate::IsEnum for Rxt {}
#[doc = "Field `RXT` reader - RX Endpoint Type"]
pub type RxtR = crate::FieldReader<Rxt>;
impl RxtR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Rxt {
match self.bits {
0 => Rxt::Control,
1 => Rxt::Isochronous,
2 => Rxt::Bulk,
3 => Rxt::Interrupt,
_ => unreachable!(),
}
}
#[doc = "Control"]
#[inline(always)]
pub fn is_control(&self) -> bool {
*self == Rxt::Control
}
#[doc = "Isochronous"]
#[inline(always)]
pub fn is_isochronous(&self) -> bool {
*self == Rxt::Isochronous
}
#[doc = "Bulk"]
#[inline(always)]
pub fn is_bulk(&self) -> bool {
*self == Rxt::Bulk
}
#[doc = "Interrupt"]
#[inline(always)]
pub fn is_interrupt(&self) -> bool {
*self == Rxt::Interrupt
}
}
#[doc = "Field `RXT` writer - RX Endpoint Type"]
pub type RxtW<'a, REG> = crate::FieldWriter<'a, REG, 2, Rxt, crate::Safe>;
impl<'a, REG> RxtW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Control"]
#[inline(always)]
pub fn control(self) -> &'a mut crate::W<REG> {
self.variant(Rxt::Control)
}
#[doc = "Isochronous"]
#[inline(always)]
pub fn isochronous(self) -> &'a mut crate::W<REG> {
self.variant(Rxt::Isochronous)
}
#[doc = "Bulk"]
#[inline(always)]
pub fn bulk(self) -> &'a mut crate::W<REG> {
self.variant(Rxt::Bulk)
}
#[doc = "Interrupt"]
#[inline(always)]
pub fn interrupt(self) -> &'a mut crate::W<REG> {
self.variant(Rxt::Interrupt)
}
}
#[doc = "Field `RXI` reader - RX Data Toggle Inhibit"]
pub type RxiR = crate::BitReader;
#[doc = "Field `RXI` writer - RX Data Toggle Inhibit"]
pub type RxiW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RXR` reader - RX Data Toggle Reset"]
pub type RxrR = crate::BitReader;
#[doc = "Field `RXR` writer - RX Data Toggle Reset"]
pub type RxrW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RXE` reader - RX Endpoint Enable"]
pub type RxeR = crate::BitReader;
#[doc = "Field `RXE` writer - RX Endpoint Enable"]
pub type RxeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TXS` reader - TX Endpoint Stall"]
pub type TxsR = crate::BitReader;
#[doc = "Field `TXS` writer - TX Endpoint Stall"]
pub type TxsW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "TX Endpoint Type\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Txt {
#[doc = "0: Control"]
Control = 0,
#[doc = "1: Isochronous"]
Isochronous = 1,
#[doc = "2: Bulk"]
Bulk = 2,
#[doc = "3: Interrupt"]
Interrupt = 3,
}
impl From<Txt> for u8 {
#[inline(always)]
fn from(variant: Txt) -> Self {
variant as _
}
}
impl crate::FieldSpec for Txt {
type Ux = u8;
}
impl crate::IsEnum for Txt {}
#[doc = "Field `TXT` reader - TX Endpoint Type"]
pub type TxtR = crate::FieldReader<Txt>;
impl TxtR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Txt {
match self.bits {
0 => Txt::Control,
1 => Txt::Isochronous,
2 => Txt::Bulk,
3 => Txt::Interrupt,
_ => unreachable!(),
}
}
#[doc = "Control"]
#[inline(always)]
pub fn is_control(&self) -> bool {
*self == Txt::Control
}
#[doc = "Isochronous"]
#[inline(always)]
pub fn is_isochronous(&self) -> bool {
*self == Txt::Isochronous
}
#[doc = "Bulk"]
#[inline(always)]
pub fn is_bulk(&self) -> bool {
*self == Txt::Bulk
}
#[doc = "Interrupt"]
#[inline(always)]
pub fn is_interrupt(&self) -> bool {
*self == Txt::Interrupt
}
}
#[doc = "Field `TXT` writer - TX Endpoint Type"]
pub type TxtW<'a, REG> = crate::FieldWriter<'a, REG, 2, Txt, crate::Safe>;
impl<'a, REG> TxtW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Control"]
#[inline(always)]
pub fn control(self) -> &'a mut crate::W<REG> {
self.variant(Txt::Control)
}
#[doc = "Isochronous"]
#[inline(always)]
pub fn isochronous(self) -> &'a mut crate::W<REG> {
self.variant(Txt::Isochronous)
}
#[doc = "Bulk"]
#[inline(always)]
pub fn bulk(self) -> &'a mut crate::W<REG> {
self.variant(Txt::Bulk)
}
#[doc = "Interrupt"]
#[inline(always)]
pub fn interrupt(self) -> &'a mut crate::W<REG> {
self.variant(Txt::Interrupt)
}
}
#[doc = "Field `TXI` reader - TX Data Toggle Inhibit"]
pub type TxiR = crate::BitReader;
#[doc = "Field `TXI` writer - TX Data Toggle Inhibit"]
pub type TxiW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TXR` reader - TX Data Toggle Reset"]
pub type TxrR = crate::BitReader;
#[doc = "Field `TXR` writer - TX Data Toggle Reset"]
pub type TxrW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TXE` reader - TX Endpoint Enable"]
pub type TxeR = crate::BitReader;
#[doc = "Field `TXE` writer - TX Endpoint Enable"]
pub type TxeW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - RX Endpoint Stall"]
#[inline(always)]
pub fn rxs(&self) -> RxsR {
RxsR::new((self.bits & 1) != 0)
}
#[doc = "Bits 2:3 - RX Endpoint Type"]
#[inline(always)]
pub fn rxt(&self) -> RxtR {
RxtR::new(((self.bits >> 2) & 3) as u8)
}
#[doc = "Bit 5 - RX Data Toggle Inhibit"]
#[inline(always)]
pub fn rxi(&self) -> RxiR {
RxiR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - RX Data Toggle Reset"]
#[inline(always)]
pub fn rxr(&self) -> RxrR {
RxrR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - RX Endpoint Enable"]
#[inline(always)]
pub fn rxe(&self) -> RxeR {
RxeR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 16 - TX Endpoint Stall"]
#[inline(always)]
pub fn txs(&self) -> TxsR {
TxsR::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bits 18:19 - TX Endpoint Type"]
#[inline(always)]
pub fn txt(&self) -> TxtR {
TxtR::new(((self.bits >> 18) & 3) as u8)
}
#[doc = "Bit 21 - TX Data Toggle Inhibit"]
#[inline(always)]
pub fn txi(&self) -> TxiR {
TxiR::new(((self.bits >> 21) & 1) != 0)
}
#[doc = "Bit 22 - TX Data Toggle Reset"]
#[inline(always)]
pub fn txr(&self) -> TxrR {
TxrR::new(((self.bits >> 22) & 1) != 0)
}
#[doc = "Bit 23 - TX Endpoint Enable"]
#[inline(always)]
pub fn txe(&self) -> TxeR {
TxeR::new(((self.bits >> 23) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - RX Endpoint Stall"]
#[inline(always)]
pub fn rxs(&mut self) -> RxsW<Endptctrl1Spec> {
RxsW::new(self, 0)
}
#[doc = "Bits 2:3 - RX Endpoint Type"]
#[inline(always)]
pub fn rxt(&mut self) -> RxtW<Endptctrl1Spec> {
RxtW::new(self, 2)
}
#[doc = "Bit 5 - RX Data Toggle Inhibit"]
#[inline(always)]
pub fn rxi(&mut self) -> RxiW<Endptctrl1Spec> {
RxiW::new(self, 5)
}
#[doc = "Bit 6 - RX Data Toggle Reset"]
#[inline(always)]
pub fn rxr(&mut self) -> RxrW<Endptctrl1Spec> {
RxrW::new(self, 6)
}
#[doc = "Bit 7 - RX Endpoint Enable"]
#[inline(always)]
pub fn rxe(&mut self) -> RxeW<Endptctrl1Spec> {
RxeW::new(self, 7)
}
#[doc = "Bit 16 - TX Endpoint Stall"]
#[inline(always)]
pub fn txs(&mut self) -> TxsW<Endptctrl1Spec> {
TxsW::new(self, 16)
}
#[doc = "Bits 18:19 - TX Endpoint Type"]
#[inline(always)]
pub fn txt(&mut self) -> TxtW<Endptctrl1Spec> {
TxtW::new(self, 18)
}
#[doc = "Bit 21 - TX Data Toggle Inhibit"]
#[inline(always)]
pub fn txi(&mut self) -> TxiW<Endptctrl1Spec> {
TxiW::new(self, 21)
}
#[doc = "Bit 22 - TX Data Toggle Reset"]
#[inline(always)]
pub fn txr(&mut self) -> TxrW<Endptctrl1Spec> {
TxrW::new(self, 22)
}
#[doc = "Bit 23 - TX Endpoint Enable"]
#[inline(always)]
pub fn txe(&mut self) -> TxeW<Endptctrl1Spec> {
TxeW::new(self, 23)
}
}
#[doc = "Endpoint 1 Control\n\nYou can [`read`](crate::Reg::read) this register and get [`endptctrl1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`endptctrl1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Endptctrl1Spec;
impl crate::RegisterSpec for Endptctrl1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`endptctrl1::R`](R) reader structure"]
impl crate::Readable for Endptctrl1Spec {}
#[doc = "`write(|w| ..)` method takes [`endptctrl1::W`](W) writer structure"]
impl crate::Writable for Endptctrl1Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ENDPTCTRL1 to value 0"]
impl crate::Resettable for Endptctrl1Spec {}
}
#[doc = "ENDPTCTRL2 (rw) register accessor: Endpoint 2 Control\n\nYou can [`read`](crate::Reg::read) this register and get [`endptctrl2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`endptctrl2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@endptctrl2`] module"]
#[doc(alias = "ENDPTCTRL2")]
pub type Endptctrl2 = crate::Reg<endptctrl2::Endptctrl2Spec>;
#[doc = "Endpoint 2 Control"]
pub mod endptctrl2 {
#[doc = "Register `ENDPTCTRL2` reader"]
pub type R = crate::R<Endptctrl2Spec>;
#[doc = "Register `ENDPTCTRL2` writer"]
pub type W = crate::W<Endptctrl2Spec>;
#[doc = "Field `RXS` reader - RX Endpoint Stall"]
pub type RxsR = crate::BitReader;
#[doc = "Field `RXS` writer - RX Endpoint Stall"]
pub type RxsW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "RX Endpoint Type\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Rxt {
#[doc = "0: Control"]
Control = 0,
#[doc = "1: Isochronous"]
Isochronous = 1,
#[doc = "2: Bulk"]
Bulk = 2,
#[doc = "3: Interrupt"]
Interrupt = 3,
}
impl From<Rxt> for u8 {
#[inline(always)]
fn from(variant: Rxt) -> Self {
variant as _
}
}
impl crate::FieldSpec for Rxt {
type Ux = u8;
}
impl crate::IsEnum for Rxt {}
#[doc = "Field `RXT` reader - RX Endpoint Type"]
pub type RxtR = crate::FieldReader<Rxt>;
impl RxtR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Rxt {
match self.bits {
0 => Rxt::Control,
1 => Rxt::Isochronous,
2 => Rxt::Bulk,
3 => Rxt::Interrupt,
_ => unreachable!(),
}
}
#[doc = "Control"]
#[inline(always)]
pub fn is_control(&self) -> bool {
*self == Rxt::Control
}
#[doc = "Isochronous"]
#[inline(always)]
pub fn is_isochronous(&self) -> bool {
*self == Rxt::Isochronous
}
#[doc = "Bulk"]
#[inline(always)]
pub fn is_bulk(&self) -> bool {
*self == Rxt::Bulk
}
#[doc = "Interrupt"]
#[inline(always)]
pub fn is_interrupt(&self) -> bool {
*self == Rxt::Interrupt
}
}
#[doc = "Field `RXT` writer - RX Endpoint Type"]
pub type RxtW<'a, REG> = crate::FieldWriter<'a, REG, 2, Rxt, crate::Safe>;
impl<'a, REG> RxtW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Control"]
#[inline(always)]
pub fn control(self) -> &'a mut crate::W<REG> {
self.variant(Rxt::Control)
}
#[doc = "Isochronous"]
#[inline(always)]
pub fn isochronous(self) -> &'a mut crate::W<REG> {
self.variant(Rxt::Isochronous)
}
#[doc = "Bulk"]
#[inline(always)]
pub fn bulk(self) -> &'a mut crate::W<REG> {
self.variant(Rxt::Bulk)
}
#[doc = "Interrupt"]
#[inline(always)]
pub fn interrupt(self) -> &'a mut crate::W<REG> {
self.variant(Rxt::Interrupt)
}
}
#[doc = "Field `RXI` reader - RX Data Toggle Inhibit"]
pub type RxiR = crate::BitReader;
#[doc = "Field `RXI` writer - RX Data Toggle Inhibit"]
pub type RxiW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RXR` reader - RX Data Toggle Reset"]
pub type RxrR = crate::BitReader;
#[doc = "Field `RXR` writer - RX Data Toggle Reset"]
pub type RxrW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RXE` reader - RX Endpoint Enable"]
pub type RxeR = crate::BitReader;
#[doc = "Field `RXE` writer - RX Endpoint Enable"]
pub type RxeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TXS` reader - TX Endpoint Stall"]
pub type TxsR = crate::BitReader;
#[doc = "Field `TXS` writer - TX Endpoint Stall"]
pub type TxsW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "TX Endpoint Type\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Txt {
#[doc = "0: Control"]
Control = 0,
#[doc = "1: Isochronous"]
Isochronous = 1,
#[doc = "2: Bulk"]
Bulk = 2,
#[doc = "3: Interrupt"]
Interrupt = 3,
}
impl From<Txt> for u8 {
#[inline(always)]
fn from(variant: Txt) -> Self {
variant as _
}
}
impl crate::FieldSpec for Txt {
type Ux = u8;
}
impl crate::IsEnum for Txt {}
#[doc = "Field `TXT` reader - TX Endpoint Type"]
pub type TxtR = crate::FieldReader<Txt>;
impl TxtR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Txt {
match self.bits {
0 => Txt::Control,
1 => Txt::Isochronous,
2 => Txt::Bulk,
3 => Txt::Interrupt,
_ => unreachable!(),
}
}
#[doc = "Control"]
#[inline(always)]
pub fn is_control(&self) -> bool {
*self == Txt::Control
}
#[doc = "Isochronous"]
#[inline(always)]
pub fn is_isochronous(&self) -> bool {
*self == Txt::Isochronous
}
#[doc = "Bulk"]
#[inline(always)]
pub fn is_bulk(&self) -> bool {
*self == Txt::Bulk
}
#[doc = "Interrupt"]
#[inline(always)]
pub fn is_interrupt(&self) -> bool {
*self == Txt::Interrupt
}
}
#[doc = "Field `TXT` writer - TX Endpoint Type"]
pub type TxtW<'a, REG> = crate::FieldWriter<'a, REG, 2, Txt, crate::Safe>;
impl<'a, REG> TxtW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Control"]
#[inline(always)]
pub fn control(self) -> &'a mut crate::W<REG> {
self.variant(Txt::Control)
}
#[doc = "Isochronous"]
#[inline(always)]
pub fn isochronous(self) -> &'a mut crate::W<REG> {
self.variant(Txt::Isochronous)
}
#[doc = "Bulk"]
#[inline(always)]
pub fn bulk(self) -> &'a mut crate::W<REG> {
self.variant(Txt::Bulk)
}
#[doc = "Interrupt"]
#[inline(always)]
pub fn interrupt(self) -> &'a mut crate::W<REG> {
self.variant(Txt::Interrupt)
}
}
#[doc = "Field `TXI` reader - TX Data Toggle Inhibit"]
pub type TxiR = crate::BitReader;
#[doc = "Field `TXI` writer - TX Data Toggle Inhibit"]
pub type TxiW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TXR` reader - TX Data Toggle Reset"]
pub type TxrR = crate::BitReader;
#[doc = "Field `TXR` writer - TX Data Toggle Reset"]
pub type TxrW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TXE` reader - TX Endpoint Enable"]
pub type TxeR = crate::BitReader;
#[doc = "Field `TXE` writer - TX Endpoint Enable"]
pub type TxeW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - RX Endpoint Stall"]
#[inline(always)]
pub fn rxs(&self) -> RxsR {
RxsR::new((self.bits & 1) != 0)
}
#[doc = "Bits 2:3 - RX Endpoint Type"]
#[inline(always)]
pub fn rxt(&self) -> RxtR {
RxtR::new(((self.bits >> 2) & 3) as u8)
}
#[doc = "Bit 5 - RX Data Toggle Inhibit"]
#[inline(always)]
pub fn rxi(&self) -> RxiR {
RxiR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - RX Data Toggle Reset"]
#[inline(always)]
pub fn rxr(&self) -> RxrR {
RxrR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - RX Endpoint Enable"]
#[inline(always)]
pub fn rxe(&self) -> RxeR {
RxeR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 16 - TX Endpoint Stall"]
#[inline(always)]
pub fn txs(&self) -> TxsR {
TxsR::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bits 18:19 - TX Endpoint Type"]
#[inline(always)]
pub fn txt(&self) -> TxtR {
TxtR::new(((self.bits >> 18) & 3) as u8)
}
#[doc = "Bit 21 - TX Data Toggle Inhibit"]
#[inline(always)]
pub fn txi(&self) -> TxiR {
TxiR::new(((self.bits >> 21) & 1) != 0)
}
#[doc = "Bit 22 - TX Data Toggle Reset"]
#[inline(always)]
pub fn txr(&self) -> TxrR {
TxrR::new(((self.bits >> 22) & 1) != 0)
}
#[doc = "Bit 23 - TX Endpoint Enable"]
#[inline(always)]
pub fn txe(&self) -> TxeR {
TxeR::new(((self.bits >> 23) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - RX Endpoint Stall"]
#[inline(always)]
pub fn rxs(&mut self) -> RxsW<Endptctrl2Spec> {
RxsW::new(self, 0)
}
#[doc = "Bits 2:3 - RX Endpoint Type"]
#[inline(always)]
pub fn rxt(&mut self) -> RxtW<Endptctrl2Spec> {
RxtW::new(self, 2)
}
#[doc = "Bit 5 - RX Data Toggle Inhibit"]
#[inline(always)]
pub fn rxi(&mut self) -> RxiW<Endptctrl2Spec> {
RxiW::new(self, 5)
}
#[doc = "Bit 6 - RX Data Toggle Reset"]
#[inline(always)]
pub fn rxr(&mut self) -> RxrW<Endptctrl2Spec> {
RxrW::new(self, 6)
}
#[doc = "Bit 7 - RX Endpoint Enable"]
#[inline(always)]
pub fn rxe(&mut self) -> RxeW<Endptctrl2Spec> {
RxeW::new(self, 7)
}
#[doc = "Bit 16 - TX Endpoint Stall"]
#[inline(always)]
pub fn txs(&mut self) -> TxsW<Endptctrl2Spec> {
TxsW::new(self, 16)
}
#[doc = "Bits 18:19 - TX Endpoint Type"]
#[inline(always)]
pub fn txt(&mut self) -> TxtW<Endptctrl2Spec> {
TxtW::new(self, 18)
}
#[doc = "Bit 21 - TX Data Toggle Inhibit"]
#[inline(always)]
pub fn txi(&mut self) -> TxiW<Endptctrl2Spec> {
TxiW::new(self, 21)
}
#[doc = "Bit 22 - TX Data Toggle Reset"]
#[inline(always)]
pub fn txr(&mut self) -> TxrW<Endptctrl2Spec> {
TxrW::new(self, 22)
}
#[doc = "Bit 23 - TX Endpoint Enable"]
#[inline(always)]
pub fn txe(&mut self) -> TxeW<Endptctrl2Spec> {
TxeW::new(self, 23)
}
}
#[doc = "Endpoint 2 Control\n\nYou can [`read`](crate::Reg::read) this register and get [`endptctrl2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`endptctrl2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Endptctrl2Spec;
impl crate::RegisterSpec for Endptctrl2Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`endptctrl2::R`](R) reader structure"]
impl crate::Readable for Endptctrl2Spec {}
#[doc = "`write(|w| ..)` method takes [`endptctrl2::W`](W) writer structure"]
impl crate::Writable for Endptctrl2Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ENDPTCTRL2 to value 0"]
impl crate::Resettable for Endptctrl2Spec {}
}
#[doc = "ENDPTCTRL3 (rw) register accessor: Endpoint 3 Control\n\nYou can [`read`](crate::Reg::read) this register and get [`endptctrl3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`endptctrl3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@endptctrl3`] module"]
#[doc(alias = "ENDPTCTRL3")]
pub type Endptctrl3 = crate::Reg<endptctrl3::Endptctrl3Spec>;
#[doc = "Endpoint 3 Control"]
pub mod endptctrl3 {
#[doc = "Register `ENDPTCTRL3` reader"]
pub type R = crate::R<Endptctrl3Spec>;
#[doc = "Register `ENDPTCTRL3` writer"]
pub type W = crate::W<Endptctrl3Spec>;
#[doc = "Field `RXS` reader - RX Endpoint Stall"]
pub type RxsR = crate::BitReader;
#[doc = "Field `RXS` writer - RX Endpoint Stall"]
pub type RxsW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "RX Endpoint Type\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Rxt {
#[doc = "0: Control"]
Control = 0,
#[doc = "1: Isochronous"]
Isochronous = 1,
#[doc = "2: Bulk"]
Bulk = 2,
#[doc = "3: Interrupt"]
Interrupt = 3,
}
impl From<Rxt> for u8 {
#[inline(always)]
fn from(variant: Rxt) -> Self {
variant as _
}
}
impl crate::FieldSpec for Rxt {
type Ux = u8;
}
impl crate::IsEnum for Rxt {}
#[doc = "Field `RXT` reader - RX Endpoint Type"]
pub type RxtR = crate::FieldReader<Rxt>;
impl RxtR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Rxt {
match self.bits {
0 => Rxt::Control,
1 => Rxt::Isochronous,
2 => Rxt::Bulk,
3 => Rxt::Interrupt,
_ => unreachable!(),
}
}
#[doc = "Control"]
#[inline(always)]
pub fn is_control(&self) -> bool {
*self == Rxt::Control
}
#[doc = "Isochronous"]
#[inline(always)]
pub fn is_isochronous(&self) -> bool {
*self == Rxt::Isochronous
}
#[doc = "Bulk"]
#[inline(always)]
pub fn is_bulk(&self) -> bool {
*self == Rxt::Bulk
}
#[doc = "Interrupt"]
#[inline(always)]
pub fn is_interrupt(&self) -> bool {
*self == Rxt::Interrupt
}
}
#[doc = "Field `RXT` writer - RX Endpoint Type"]
pub type RxtW<'a, REG> = crate::FieldWriter<'a, REG, 2, Rxt, crate::Safe>;
impl<'a, REG> RxtW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Control"]
#[inline(always)]
pub fn control(self) -> &'a mut crate::W<REG> {
self.variant(Rxt::Control)
}
#[doc = "Isochronous"]
#[inline(always)]
pub fn isochronous(self) -> &'a mut crate::W<REG> {
self.variant(Rxt::Isochronous)
}
#[doc = "Bulk"]
#[inline(always)]
pub fn bulk(self) -> &'a mut crate::W<REG> {
self.variant(Rxt::Bulk)
}
#[doc = "Interrupt"]
#[inline(always)]
pub fn interrupt(self) -> &'a mut crate::W<REG> {
self.variant(Rxt::Interrupt)
}
}
#[doc = "Field `RXI` reader - RX Data Toggle Inhibit"]
pub type RxiR = crate::BitReader;
#[doc = "Field `RXI` writer - RX Data Toggle Inhibit"]
pub type RxiW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RXR` reader - RX Data Toggle Reset"]
pub type RxrR = crate::BitReader;
#[doc = "Field `RXR` writer - RX Data Toggle Reset"]
pub type RxrW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RXE` reader - RX Endpoint Enable"]
pub type RxeR = crate::BitReader;
#[doc = "Field `RXE` writer - RX Endpoint Enable"]
pub type RxeW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TXS` reader - TX Endpoint Stall"]
pub type TxsR = crate::BitReader;
#[doc = "Field `TXS` writer - TX Endpoint Stall"]
pub type TxsW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "TX Endpoint Type\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Txt {
#[doc = "0: Control"]
Control = 0,
#[doc = "1: Isochronous"]
Isochronous = 1,
#[doc = "2: Bulk"]
Bulk = 2,
#[doc = "3: Interrupt"]
Interrupt = 3,
}
impl From<Txt> for u8 {
#[inline(always)]
fn from(variant: Txt) -> Self {
variant as _
}
}
impl crate::FieldSpec for Txt {
type Ux = u8;
}
impl crate::IsEnum for Txt {}
#[doc = "Field `TXT` reader - TX Endpoint Type"]
pub type TxtR = crate::FieldReader<Txt>;
impl TxtR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Txt {
match self.bits {
0 => Txt::Control,
1 => Txt::Isochronous,
2 => Txt::Bulk,
3 => Txt::Interrupt,
_ => unreachable!(),
}
}
#[doc = "Control"]
#[inline(always)]
pub fn is_control(&self) -> bool {
*self == Txt::Control
}
#[doc = "Isochronous"]
#[inline(always)]
pub fn is_isochronous(&self) -> bool {
*self == Txt::Isochronous
}
#[doc = "Bulk"]
#[inline(always)]
pub fn is_bulk(&self) -> bool {
*self == Txt::Bulk
}
#[doc = "Interrupt"]
#[inline(always)]
pub fn is_interrupt(&self) -> bool {
*self == Txt::Interrupt
}
}
#[doc = "Field `TXT` writer - TX Endpoint Type"]
pub type TxtW<'a, REG> = crate::FieldWriter<'a, REG, 2, Txt, crate::Safe>;
impl<'a, REG> TxtW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Control"]
#[inline(always)]
pub fn control(self) -> &'a mut crate::W<REG> {
self.variant(Txt::Control)
}
#[doc = "Isochronous"]
#[inline(always)]
pub fn isochronous(self) -> &'a mut crate::W<REG> {
self.variant(Txt::Isochronous)
}
#[doc = "Bulk"]
#[inline(always)]
pub fn bulk(self) -> &'a mut crate::W<REG> {
self.variant(Txt::Bulk)
}
#[doc = "Interrupt"]
#[inline(always)]
pub fn interrupt(self) -> &'a mut crate::W<REG> {
self.variant(Txt::Interrupt)
}
}
#[doc = "Field `TXI` reader - TX Data Toggle Inhibit"]
pub type TxiR = crate::BitReader;
#[doc = "Field `TXI` writer - TX Data Toggle Inhibit"]
pub type TxiW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TXR` reader - TX Data Toggle Reset"]
pub type TxrR = crate::BitReader;
#[doc = "Field `TXR` writer - TX Data Toggle Reset"]
pub type TxrW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TXE` reader - TX Endpoint Enable"]
pub type TxeR = crate::BitReader;
#[doc = "Field `TXE` writer - TX Endpoint Enable"]
pub type TxeW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - RX Endpoint Stall"]
#[inline(always)]
pub fn rxs(&self) -> RxsR {
RxsR::new((self.bits & 1) != 0)
}
#[doc = "Bits 2:3 - RX Endpoint Type"]
#[inline(always)]
pub fn rxt(&self) -> RxtR {
RxtR::new(((self.bits >> 2) & 3) as u8)
}
#[doc = "Bit 5 - RX Data Toggle Inhibit"]
#[inline(always)]
pub fn rxi(&self) -> RxiR {
RxiR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - RX Data Toggle Reset"]
#[inline(always)]
pub fn rxr(&self) -> RxrR {
RxrR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - RX Endpoint Enable"]
#[inline(always)]
pub fn rxe(&self) -> RxeR {
RxeR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 16 - TX Endpoint Stall"]
#[inline(always)]
pub fn txs(&self) -> TxsR {
TxsR::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bits 18:19 - TX Endpoint Type"]
#[inline(always)]
pub fn txt(&self) -> TxtR {
TxtR::new(((self.bits >> 18) & 3) as u8)
}
#[doc = "Bit 21 - TX Data Toggle Inhibit"]
#[inline(always)]
pub fn txi(&self) -> TxiR {
TxiR::new(((self.bits >> 21) & 1) != 0)
}
#[doc = "Bit 22 - TX Data Toggle Reset"]
#[inline(always)]
pub fn txr(&self) -> TxrR {
TxrR::new(((self.bits >> 22) & 1) != 0)
}
#[doc = "Bit 23 - TX Endpoint Enable"]
#[inline(always)]
pub fn txe(&self) -> TxeR {
TxeR::new(((self.bits >> 23) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - RX Endpoint Stall"]
#[inline(always)]
pub fn rxs(&mut self) -> RxsW<Endptctrl3Spec> {
RxsW::new(self, 0)
}
#[doc = "Bits 2:3 - RX Endpoint Type"]
#[inline(always)]
pub fn rxt(&mut self) -> RxtW<Endptctrl3Spec> {
RxtW::new(self, 2)
}
#[doc = "Bit 5 - RX Data Toggle Inhibit"]
#[inline(always)]
pub fn rxi(&mut self) -> RxiW<Endptctrl3Spec> {
RxiW::new(self, 5)
}
#[doc = "Bit 6 - RX Data Toggle Reset"]
#[inline(always)]
pub fn rxr(&mut self) -> RxrW<Endptctrl3Spec> {
RxrW::new(self, 6)
}
#[doc = "Bit 7 - RX Endpoint Enable"]
#[inline(always)]
pub fn rxe(&mut self) -> RxeW<Endptctrl3Spec> {
RxeW::new(self, 7)
}
#[doc = "Bit 16 - TX Endpoint Stall"]
#[inline(always)]
pub fn txs(&mut self) -> TxsW<Endptctrl3Spec> {
TxsW::new(self, 16)
}
#[doc = "Bits 18:19 - TX Endpoint Type"]
#[inline(always)]
pub fn txt(&mut self) -> TxtW<Endptctrl3Spec> {
TxtW::new(self, 18)
}
#[doc = "Bit 21 - TX Data Toggle Inhibit"]
#[inline(always)]
pub fn txi(&mut self) -> TxiW<Endptctrl3Spec> {
TxiW::new(self, 21)
}
#[doc = "Bit 22 - TX Data Toggle Reset"]
#[inline(always)]
pub fn txr(&mut self) -> TxrW<Endptctrl3Spec> {
TxrW::new(self, 22)
}
#[doc = "Bit 23 - TX Endpoint Enable"]
#[inline(always)]
pub fn txe(&mut self) -> TxeW<Endptctrl3Spec> {
TxeW::new(self, 23)
}
}
#[doc = "Endpoint 3 Control\n\nYou can [`read`](crate::Reg::read) this register and get [`endptctrl3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`endptctrl3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Endptctrl3Spec;
impl crate::RegisterSpec for Endptctrl3Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`endptctrl3::R`](R) reader structure"]
impl crate::Readable for Endptctrl3Spec {}
#[doc = "`write(|w| ..)` method takes [`endptctrl3::W`](W) writer structure"]
impl crate::Writable for Endptctrl3Spec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets ENDPTCTRL3 to value 0"]
impl crate::Resettable for Endptctrl3Spec {}
}
}
#[doc = "CRC registers"]
pub type Crc0 = crate::Periph<crc0::RegisterBlock, 0x4100_2000>;
impl core::fmt::Debug for Crc0 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Crc0").finish()
}
}
#[doc = "CRC registers"]
pub mod crc0 {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
dr: Dr,
idr: Idr,
cr: Cr,
_reserved3: [u8; 0x04],
init: Init,
pol: Pol,
}
impl RegisterBlock {
#[doc = "0x00 - CRC Data register"]
#[inline(always)]
pub const fn dr(&self) -> &Dr {
&self.dr
}
#[doc = "0x04 - CRC Independent data register"]
#[inline(always)]
pub const fn idr(&self) -> &Idr {
&self.idr
}
#[doc = "0x08 - CRC Control register"]
#[inline(always)]
pub const fn cr(&self) -> &Cr {
&self.cr
}
#[doc = "0x10 - Initial CRC value register"]
#[inline(always)]
pub const fn init(&self) -> &Init {
&self.init
}
#[doc = "0x14 - CRC polynomial register"]
#[inline(always)]
pub const fn pol(&self) -> &Pol {
&self.pol
}
}
#[doc = "DR (rw) register accessor: CRC Data register\n\nYou can [`read`](crate::Reg::read) this register and get [`dr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dr`] module"]
#[doc(alias = "DR")]
pub type Dr = crate::Reg<dr::DrSpec>;
#[doc = "CRC Data register"]
pub mod dr {
#[doc = "Register `DR` reader"]
pub type R = crate::R<DrSpec>;
#[doc = "Register `DR` writer"]
pub type W = crate::W<DrSpec>;
#[doc = "Field `DR` reader - CRC Data register"]
pub type DrR = crate::FieldReader<u32>;
#[doc = "Field `DR` writer - CRC Data register"]
pub type DrW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - CRC Data register"]
#[inline(always)]
pub fn dr(&self) -> DrR {
DrR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - CRC Data register"]
#[inline(always)]
pub fn dr(&mut self) -> DrW<DrSpec> {
DrW::new(self, 0)
}
}
#[doc = "CRC Data register\n\nYou can [`read`](crate::Reg::read) this register and get [`dr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DrSpec;
impl crate::RegisterSpec for DrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`dr::R`](R) reader structure"]
impl crate::Readable for DrSpec {}
#[doc = "`write(|w| ..)` method takes [`dr::W`](W) writer structure"]
impl crate::Writable for DrSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets DR to value 0"]
impl crate::Resettable for DrSpec {}
}
#[doc = "IDR (rw) register accessor: CRC Independent data register\n\nYou can [`read`](crate::Reg::read) this register and get [`idr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`idr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@idr`] module"]
#[doc(alias = "IDR")]
pub type Idr = crate::Reg<idr::IdrSpec>;
#[doc = "CRC Independent data register"]
pub mod idr {
#[doc = "Register `IDR` reader"]
pub type R = crate::R<IdrSpec>;
#[doc = "Register `IDR` writer"]
pub type W = crate::W<IdrSpec>;
#[doc = "Field `IDR` reader - CRC Independent data register"]
pub type IdrR = crate::FieldReader;
#[doc = "Field `IDR` writer - CRC Independent data register"]
pub type IdrW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:7 - CRC Independent data register"]
#[inline(always)]
pub fn idr(&self) -> IdrR {
IdrR::new((self.bits & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:7 - CRC Independent data register"]
#[inline(always)]
pub fn idr(&mut self) -> IdrW<IdrSpec> {
IdrW::new(self, 0)
}
}
#[doc = "CRC Independent data register\n\nYou can [`read`](crate::Reg::read) this register and get [`idr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`idr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IdrSpec;
impl crate::RegisterSpec for IdrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`idr::R`](R) reader structure"]
impl crate::Readable for IdrSpec {}
#[doc = "`write(|w| ..)` method takes [`idr::W`](W) writer structure"]
impl crate::Writable for IdrSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets IDR to value 0"]
impl crate::Resettable for IdrSpec {}
}
#[doc = "CR (rw) register accessor: CRC Control register\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr`] module"]
#[doc(alias = "CR")]
pub type Cr = crate::Reg<cr::CrSpec>;
#[doc = "CRC Control register"]
pub mod cr {
#[doc = "Register `CR` reader"]
pub type R = crate::R<CrSpec>;
#[doc = "Register `CR` writer"]
pub type W = crate::W<CrSpec>;
#[doc = "Field `RESET` writer - Reset bit"]
pub type ResetW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Polynomial size\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum PolySize {
#[doc = "0: 32 bit"]
_32bit = 0,
#[doc = "1: 16 bit"]
_16bit = 1,
#[doc = "2: 8 bit"]
_8bit = 2,
#[doc = "3: 7 bit"]
_7bit = 3,
}
impl From<PolySize> for u8 {
#[inline(always)]
fn from(variant: PolySize) -> Self {
variant as _
}
}
impl crate::FieldSpec for PolySize {
type Ux = u8;
}
impl crate::IsEnum for PolySize {}
#[doc = "Field `POLY_SIZE` reader - Polynomial size"]
pub type PolySizeR = crate::FieldReader<PolySize>;
impl PolySizeR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> PolySize {
match self.bits {
0 => PolySize::_32bit,
1 => PolySize::_16bit,
2 => PolySize::_8bit,
3 => PolySize::_7bit,
_ => unreachable!(),
}
}
#[doc = "32 bit"]
#[inline(always)]
pub fn is_32bit(&self) -> bool {
*self == PolySize::_32bit
}
#[doc = "16 bit"]
#[inline(always)]
pub fn is_16bit(&self) -> bool {
*self == PolySize::_16bit
}
#[doc = "8 bit"]
#[inline(always)]
pub fn is_8bit(&self) -> bool {
*self == PolySize::_8bit
}
#[doc = "7 bit"]
#[inline(always)]
pub fn is_7bit(&self) -> bool {
*self == PolySize::_7bit
}
}
#[doc = "Field `POLY_SIZE` writer - Polynomial size"]
pub type PolySizeW<'a, REG> = crate::FieldWriter<'a, REG, 2, PolySize, crate::Safe>;
impl<'a, REG> PolySizeW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "32 bit"]
#[inline(always)]
pub fn _32bit(self) -> &'a mut crate::W<REG> {
self.variant(PolySize::_32bit)
}
#[doc = "16 bit"]
#[inline(always)]
pub fn _16bit(self) -> &'a mut crate::W<REG> {
self.variant(PolySize::_16bit)
}
#[doc = "8 bit"]
#[inline(always)]
pub fn _8bit(self) -> &'a mut crate::W<REG> {
self.variant(PolySize::_8bit)
}
#[doc = "7 bit"]
#[inline(always)]
pub fn _7bit(self) -> &'a mut crate::W<REG> {
self.variant(PolySize::_7bit)
}
}
#[doc = "Reverse input data\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum RevIn {
#[doc = "0: None"]
None = 0,
#[doc = "1: By byte"]
Bybyte = 1,
#[doc = "2: By half-word"]
Byhalfword = 2,
#[doc = "3: By word"]
Byword = 3,
}
impl From<RevIn> for u8 {
#[inline(always)]
fn from(variant: RevIn) -> Self {
variant as _
}
}
impl crate::FieldSpec for RevIn {
type Ux = u8;
}
impl crate::IsEnum for RevIn {}
#[doc = "Field `REV_IN` reader - Reverse input data"]
pub type RevInR = crate::FieldReader<RevIn>;
impl RevInR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> RevIn {
match self.bits {
0 => RevIn::None,
1 => RevIn::Bybyte,
2 => RevIn::Byhalfword,
3 => RevIn::Byword,
_ => unreachable!(),
}
}
#[doc = "None"]
#[inline(always)]
pub fn is_none(&self) -> bool {
*self == RevIn::None
}
#[doc = "By byte"]
#[inline(always)]
pub fn is_bybyte(&self) -> bool {
*self == RevIn::Bybyte
}
#[doc = "By half-word"]
#[inline(always)]
pub fn is_byhalfword(&self) -> bool {
*self == RevIn::Byhalfword
}
#[doc = "By word"]
#[inline(always)]
pub fn is_byword(&self) -> bool {
*self == RevIn::Byword
}
}
#[doc = "Field `REV_IN` writer - Reverse input data"]
pub type RevInW<'a, REG> = crate::FieldWriter<'a, REG, 2, RevIn, crate::Safe>;
impl<'a, REG> RevInW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "None"]
#[inline(always)]
pub fn none(self) -> &'a mut crate::W<REG> {
self.variant(RevIn::None)
}
#[doc = "By byte"]
#[inline(always)]
pub fn bybyte(self) -> &'a mut crate::W<REG> {
self.variant(RevIn::Bybyte)
}
#[doc = "By half-word"]
#[inline(always)]
pub fn byhalfword(self) -> &'a mut crate::W<REG> {
self.variant(RevIn::Byhalfword)
}
#[doc = "By word"]
#[inline(always)]
pub fn byword(self) -> &'a mut crate::W<REG> {
self.variant(RevIn::Byword)
}
}
#[doc = "Reverse output data\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum RevOut {
#[doc = "0: None"]
None = 0,
#[doc = "1: Reversed"]
Reversed = 1,
}
impl From<RevOut> for bool {
#[inline(always)]
fn from(variant: RevOut) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `REV_OUT` reader - Reverse output data"]
pub type RevOutR = crate::BitReader<RevOut>;
impl RevOutR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> RevOut {
match self.bits {
false => RevOut::None,
true => RevOut::Reversed,
}
}
#[doc = "None"]
#[inline(always)]
pub fn is_none(&self) -> bool {
*self == RevOut::None
}
#[doc = "Reversed"]
#[inline(always)]
pub fn is_reversed(&self) -> bool {
*self == RevOut::Reversed
}
}
#[doc = "Field `REV_OUT` writer - Reverse output data"]
pub type RevOutW<'a, REG> = crate::BitWriter<'a, REG, RevOut>;
impl<'a, REG> RevOutW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "None"]
#[inline(always)]
pub fn none(self) -> &'a mut crate::W<REG> {
self.variant(RevOut::None)
}
#[doc = "Reversed"]
#[inline(always)]
pub fn reversed(self) -> &'a mut crate::W<REG> {
self.variant(RevOut::Reversed)
}
}
#[doc = "Input Endianness\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Endian {
#[doc = "0: BE"]
Be = 0,
#[doc = "1: LE"]
Le = 1,
}
impl From<Endian> for bool {
#[inline(always)]
fn from(variant: Endian) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `ENDIAN` reader - Input Endianness"]
pub type EndianR = crate::BitReader<Endian>;
impl EndianR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Endian {
match self.bits {
false => Endian::Be,
true => Endian::Le,
}
}
#[doc = "BE"]
#[inline(always)]
pub fn is_be(&self) -> bool {
*self == Endian::Be
}
#[doc = "LE"]
#[inline(always)]
pub fn is_le(&self) -> bool {
*self == Endian::Le
}
}
#[doc = "Field `ENDIAN` writer - Input Endianness"]
pub type EndianW<'a, REG> = crate::BitWriter<'a, REG, Endian>;
impl<'a, REG> EndianW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "BE"]
#[inline(always)]
pub fn be(self) -> &'a mut crate::W<REG> {
self.variant(Endian::Be)
}
#[doc = "LE"]
#[inline(always)]
pub fn le(self) -> &'a mut crate::W<REG> {
self.variant(Endian::Le)
}
}
impl R {
#[doc = "Bits 3:4 - Polynomial size"]
#[inline(always)]
pub fn poly_size(&self) -> PolySizeR {
PolySizeR::new(((self.bits >> 3) & 3) as u8)
}
#[doc = "Bits 5:6 - Reverse input data"]
#[inline(always)]
pub fn rev_in(&self) -> RevInR {
RevInR::new(((self.bits >> 5) & 3) as u8)
}
#[doc = "Bit 7 - Reverse output data"]
#[inline(always)]
pub fn rev_out(&self) -> RevOutR {
RevOutR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - Input Endianness"]
#[inline(always)]
pub fn endian(&self) -> EndianR {
EndianR::new(((self.bits >> 8) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Reset bit"]
#[inline(always)]
pub fn reset(&mut self) -> ResetW<CrSpec> {
ResetW::new(self, 0)
}
#[doc = "Bits 3:4 - Polynomial size"]
#[inline(always)]
pub fn poly_size(&mut self) -> PolySizeW<CrSpec> {
PolySizeW::new(self, 3)
}
#[doc = "Bits 5:6 - Reverse input data"]
#[inline(always)]
pub fn rev_in(&mut self) -> RevInW<CrSpec> {
RevInW::new(self, 5)
}
#[doc = "Bit 7 - Reverse output data"]
#[inline(always)]
pub fn rev_out(&mut self) -> RevOutW<CrSpec> {
RevOutW::new(self, 7)
}
#[doc = "Bit 8 - Input Endianness"]
#[inline(always)]
pub fn endian(&mut self) -> EndianW<CrSpec> {
EndianW::new(self, 8)
}
}
#[doc = "CRC Control register\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CrSpec;
impl crate::RegisterSpec for CrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cr::R`](R) reader structure"]
impl crate::Readable for CrSpec {}
#[doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"]
impl crate::Writable for CrSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets CR to value 0"]
impl crate::Resettable for CrSpec {}
}
#[doc = "INIT (rw) register accessor: Initial CRC value register\n\nYou can [`read`](crate::Reg::read) this register and get [`init::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`init::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@init`] module"]
#[doc(alias = "INIT")]
pub type Init = crate::Reg<init::InitSpec>;
#[doc = "Initial CRC value register"]
pub mod init {
#[doc = "Register `INIT` reader"]
pub type R = crate::R<InitSpec>;
#[doc = "Register `INIT` writer"]
pub type W = crate::W<InitSpec>;
#[doc = "Field `INIT` reader - Initial CRC value register"]
pub type InitR = crate::FieldReader<u32>;
#[doc = "Field `INIT` writer - Initial CRC value register"]
pub type InitW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - Initial CRC value register"]
#[inline(always)]
pub fn init(&self) -> InitR {
InitR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - Initial CRC value register"]
#[inline(always)]
pub fn init(&mut self) -> InitW<InitSpec> {
InitW::new(self, 0)
}
}
#[doc = "Initial CRC value register\n\nYou can [`read`](crate::Reg::read) this register and get [`init::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`init::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct InitSpec;
impl crate::RegisterSpec for InitSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`init::R`](R) reader structure"]
impl crate::Readable for InitSpec {}
#[doc = "`write(|w| ..)` method takes [`init::W`](W) writer structure"]
impl crate::Writable for InitSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets INIT to value 0"]
impl crate::Resettable for InitSpec {}
}
#[doc = "POL (rw) register accessor: CRC polynomial register\n\nYou can [`read`](crate::Reg::read) this register and get [`pol::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pol::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pol`] module"]
#[doc(alias = "POL")]
pub type Pol = crate::Reg<pol::PolSpec>;
#[doc = "CRC polynomial register"]
pub mod pol {
#[doc = "Register `POL` reader"]
pub type R = crate::R<PolSpec>;
#[doc = "Register `POL` writer"]
pub type W = crate::W<PolSpec>;
#[doc = "Field `POL` reader - CRC polynomial register"]
pub type PolR = crate::FieldReader<u32>;
#[doc = "Field `POL` writer - CRC polynomial register"]
pub type PolW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - CRC polynomial register"]
#[inline(always)]
pub fn pol(&self) -> PolR {
PolR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - CRC polynomial register"]
#[inline(always)]
pub fn pol(&mut self) -> PolW<PolSpec> {
PolW::new(self, 0)
}
}
#[doc = "CRC polynomial register\n\nYou can [`read`](crate::Reg::read) this register and get [`pol::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pol::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PolSpec;
impl crate::RegisterSpec for PolSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`pol::R`](R) reader structure"]
impl crate::Readable for PolSpec {}
#[doc = "`write(|w| ..)` method takes [`pol::W`](W) writer structure"]
impl crate::Writable for PolSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets POL to value 0"]
impl crate::Resettable for PolSpec {}
}
}
#[doc = "MAC registers"]
pub type Mac0 = crate::Periph<mac0::RegisterBlock, 0x4104_0000>;
impl core::fmt::Debug for Mac0 {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("Mac0").finish()
}
}
#[doc = "MAC registers"]
pub mod mac0 {
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
ctrl: Ctrl,
stat: Stat,
macmsb: Macmsb,
maclsb: Maclsb,
mdio: Mdio,
txbase: Txbase,
rxbase: Rxbase,
_reserved7: [u8; 0x04],
htmsb: Htmsb,
htlsb: Htlsb,
}
impl RegisterBlock {
#[doc = "0x00 - Control register"]
#[inline(always)]
pub const fn ctrl(&self) -> &Ctrl {
&self.ctrl
}
#[doc = "0x04 - Status register"]
#[inline(always)]
pub const fn stat(&self) -> &Stat {
&self.stat
}
#[doc = "0x08 - Mac address MSB"]
#[inline(always)]
pub const fn macmsb(&self) -> &Macmsb {
&self.macmsb
}
#[doc = "0x0c - Mac address LSB"]
#[inline(always)]
pub const fn maclsb(&self) -> &Maclsb {
&self.maclsb
}
#[doc = "0x10 - MDIO control and status register"]
#[inline(always)]
pub const fn mdio(&self) -> &Mdio {
&self.mdio
}
#[doc = "0x14 - Transmit descriptor table base address"]
#[inline(always)]
pub const fn txbase(&self) -> &Txbase {
&self.txbase
}
#[doc = "0x18 - Receive descriptor table base address"]
#[inline(always)]
pub const fn rxbase(&self) -> &Rxbase {
&self.rxbase
}
#[doc = "0x20 - Hash table MSB"]
#[inline(always)]
pub const fn htmsb(&self) -> &Htmsb {
&self.htmsb
}
#[doc = "0x24 - Hash table LSB"]
#[inline(always)]
pub const fn htlsb(&self) -> &Htlsb {
&self.htlsb
}
}
#[doc = "CTRL (rw) register accessor: Control register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`] module"]
#[doc(alias = "CTRL")]
pub type Ctrl = crate::Reg<ctrl::CtrlSpec>;
#[doc = "Control register"]
pub mod ctrl {
#[doc = "Register `CTRL` reader"]
pub type R = crate::R<CtrlSpec>;
#[doc = "Register `CTRL` writer"]
pub type W = crate::W<CtrlSpec>;
#[doc = "Field `CTRL_TX_EN` reader - Transmit enable"]
pub type CtrlTxEnR = crate::BitReader;
#[doc = "Field `CTRL_TX_EN` writer - Transmit enable"]
pub type CtrlTxEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CTRL_RX_EN` reader - Receive enable"]
pub type CtrlRxEnR = crate::BitReader;
#[doc = "Field `CTRL_RX_EN` writer - Receive enable"]
pub type CtrlRxEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CTRL_TX_INTEN` reader - Transmit interrupt enable"]
pub type CtrlTxIntenR = crate::BitReader;
#[doc = "Field `CTRL_TX_INTEN` writer - Transmit interrupt enable"]
pub type CtrlTxIntenW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CTRL_RX_INTEN` reader - Receive interrupt enable"]
pub type CtrlRxIntenR = crate::BitReader;
#[doc = "Field `CTRL_RX_INTEN` writer - Receive interrupt enable"]
pub type CtrlRxIntenW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Duplex mode\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum CtrlDuplex {
#[doc = "0: Half duplex"]
Halfduplex = 0,
#[doc = "1: Full duplex"]
Fullduplex = 1,
}
impl From<CtrlDuplex> for bool {
#[inline(always)]
fn from(variant: CtrlDuplex) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `CTRL_DUPLEX` reader - Duplex mode"]
pub type CtrlDuplexR = crate::BitReader<CtrlDuplex>;
impl CtrlDuplexR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> CtrlDuplex {
match self.bits {
false => CtrlDuplex::Halfduplex,
true => CtrlDuplex::Fullduplex,
}
}
#[doc = "Half duplex"]
#[inline(always)]
pub fn is_halfduplex(&self) -> bool {
*self == CtrlDuplex::Halfduplex
}
#[doc = "Full duplex"]
#[inline(always)]
pub fn is_fullduplex(&self) -> bool {
*self == CtrlDuplex::Fullduplex
}
}
#[doc = "Field `CTRL_DUPLEX` writer - Duplex mode"]
pub type CtrlDuplexW<'a, REG> = crate::BitWriter<'a, REG, CtrlDuplex>;
impl<'a, REG> CtrlDuplexW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Half duplex"]
#[inline(always)]
pub fn halfduplex(self) -> &'a mut crate::W<REG> {
self.variant(CtrlDuplex::Halfduplex)
}
#[doc = "Full duplex"]
#[inline(always)]
pub fn fullduplex(self) -> &'a mut crate::W<REG> {
self.variant(CtrlDuplex::Fullduplex)
}
}
#[doc = "Field `CTRL_PROM` reader - Promiscuous mode"]
pub type CtrlPromR = crate::BitReader;
#[doc = "Field `CTRL_PROM` writer - Promiscuous mode"]
pub type CtrlPromW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CTRL_RESET` reader - Reset, self clearing"]
pub type CtrlResetR = crate::BitReader;
#[doc = "Field `CTRL_RESET` writer - Reset, self clearing"]
pub type CtrlResetW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Speed\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum CtrlSpeed {
#[doc = "0: 10M"]
_10m = 0,
#[doc = "1: 100M"]
_100m = 1,
}
impl From<CtrlSpeed> for bool {
#[inline(always)]
fn from(variant: CtrlSpeed) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `CTRL_SPEED` reader - Speed"]
pub type CtrlSpeedR = crate::BitReader<CtrlSpeed>;
impl CtrlSpeedR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> CtrlSpeed {
match self.bits {
false => CtrlSpeed::_10m,
true => CtrlSpeed::_100m,
}
}
#[doc = "10M"]
#[inline(always)]
pub fn is_10m(&self) -> bool {
*self == CtrlSpeed::_10m
}
#[doc = "100M"]
#[inline(always)]
pub fn is_100m(&self) -> bool {
*self == CtrlSpeed::_100m
}
}
#[doc = "Field `CTRL_SPEED` writer - Speed"]
pub type CtrlSpeedW<'a, REG> = crate::BitWriter<'a, REG, CtrlSpeed>;
impl<'a, REG> CtrlSpeedW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "10M"]
#[inline(always)]
pub fn _10m(self) -> &'a mut crate::W<REG> {
self.variant(CtrlSpeed::_10m)
}
#[doc = "100M"]
#[inline(always)]
pub fn _100m(self) -> &'a mut crate::W<REG> {
self.variant(CtrlSpeed::_100m)
}
}
#[doc = "Field `CTRL_PHY_INTEN` reader - PHY status change interrupt enable"]
pub type CtrlPhyIntenR = crate::BitReader;
#[doc = "Field `CTRL_PHY_INTEN` writer - PHY status change interrupt enable"]
pub type CtrlPhyIntenW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CTRL_MULTICAST_EN` reader - Multicast enable"]
pub type CtrlMulticastEnR = crate::BitReader;
#[doc = "Field `CTRL_MULTICAST_EN` writer - Multicast enable"]
pub type CtrlMulticastEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "RMII mode\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum CtrlRmiiMode {
#[doc = "0: MII"]
Mii = 0,
#[doc = "1: RMII"]
Rmii = 1,
}
impl From<CtrlRmiiMode> for bool {
#[inline(always)]
fn from(variant: CtrlRmiiMode) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `CTRL_RMII_MODE` reader - RMII mode"]
pub type CtrlRmiiModeR = crate::BitReader<CtrlRmiiMode>;
impl CtrlRmiiModeR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> CtrlRmiiMode {
match self.bits {
false => CtrlRmiiMode::Mii,
true => CtrlRmiiMode::Rmii,
}
}
#[doc = "MII"]
#[inline(always)]
pub fn is_mii(&self) -> bool {
*self == CtrlRmiiMode::Mii
}
#[doc = "RMII"]
#[inline(always)]
pub fn is_rmii(&self) -> bool {
*self == CtrlRmiiMode::Rmii
}
}
#[doc = "Field `CTRL_RMII_MODE` writer - RMII mode"]
pub type CtrlRmiiModeW<'a, REG> = crate::BitWriter<'a, REG, CtrlRmiiMode>;
impl<'a, REG> CtrlRmiiModeW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "MII"]
#[inline(always)]
pub fn mii(self) -> &'a mut crate::W<REG> {
self.variant(CtrlRmiiMode::Mii)
}
#[doc = "RMII"]
#[inline(always)]
pub fn rmii(self) -> &'a mut crate::W<REG> {
self.variant(CtrlRmiiMode::Rmii)
}
}
impl R {
#[doc = "Bit 0 - Transmit enable"]
#[inline(always)]
pub fn ctrl_tx_en(&self) -> CtrlTxEnR {
CtrlTxEnR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Receive enable"]
#[inline(always)]
pub fn ctrl_rx_en(&self) -> CtrlRxEnR {
CtrlRxEnR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Transmit interrupt enable"]
#[inline(always)]
pub fn ctrl_tx_inten(&self) -> CtrlTxIntenR {
CtrlTxIntenR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Receive interrupt enable"]
#[inline(always)]
pub fn ctrl_rx_inten(&self) -> CtrlRxIntenR {
CtrlRxIntenR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Duplex mode"]
#[inline(always)]
pub fn ctrl_duplex(&self) -> CtrlDuplexR {
CtrlDuplexR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Promiscuous mode"]
#[inline(always)]
pub fn ctrl_prom(&self) -> CtrlPromR {
CtrlPromR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Reset, self clearing"]
#[inline(always)]
pub fn ctrl_reset(&self) -> CtrlResetR {
CtrlResetR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Speed"]
#[inline(always)]
pub fn ctrl_speed(&self) -> CtrlSpeedR {
CtrlSpeedR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 10 - PHY status change interrupt enable"]
#[inline(always)]
pub fn ctrl_phy_inten(&self) -> CtrlPhyIntenR {
CtrlPhyIntenR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - Multicast enable"]
#[inline(always)]
pub fn ctrl_multicast_en(&self) -> CtrlMulticastEnR {
CtrlMulticastEnR::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bit 16 - RMII mode"]
#[inline(always)]
pub fn ctrl_rmii_mode(&self) -> CtrlRmiiModeR {
CtrlRmiiModeR::new(((self.bits >> 16) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Transmit enable"]
#[inline(always)]
pub fn ctrl_tx_en(&mut self) -> CtrlTxEnW<CtrlSpec> {
CtrlTxEnW::new(self, 0)
}
#[doc = "Bit 1 - Receive enable"]
#[inline(always)]
pub fn ctrl_rx_en(&mut self) -> CtrlRxEnW<CtrlSpec> {
CtrlRxEnW::new(self, 1)
}
#[doc = "Bit 2 - Transmit interrupt enable"]
#[inline(always)]
pub fn ctrl_tx_inten(&mut self) -> CtrlTxIntenW<CtrlSpec> {
CtrlTxIntenW::new(self, 2)
}
#[doc = "Bit 3 - Receive interrupt enable"]
#[inline(always)]
pub fn ctrl_rx_inten(&mut self) -> CtrlRxIntenW<CtrlSpec> {
CtrlRxIntenW::new(self, 3)
}
#[doc = "Bit 4 - Duplex mode"]
#[inline(always)]
pub fn ctrl_duplex(&mut self) -> CtrlDuplexW<CtrlSpec> {
CtrlDuplexW::new(self, 4)
}
#[doc = "Bit 5 - Promiscuous mode"]
#[inline(always)]
pub fn ctrl_prom(&mut self) -> CtrlPromW<CtrlSpec> {
CtrlPromW::new(self, 5)
}
#[doc = "Bit 6 - Reset, self clearing"]
#[inline(always)]
pub fn ctrl_reset(&mut self) -> CtrlResetW<CtrlSpec> {
CtrlResetW::new(self, 6)
}
#[doc = "Bit 7 - Speed"]
#[inline(always)]
pub fn ctrl_speed(&mut self) -> CtrlSpeedW<CtrlSpec> {
CtrlSpeedW::new(self, 7)
}
#[doc = "Bit 10 - PHY status change interrupt enable"]
#[inline(always)]
pub fn ctrl_phy_inten(&mut self) -> CtrlPhyIntenW<CtrlSpec> {
CtrlPhyIntenW::new(self, 10)
}
#[doc = "Bit 11 - Multicast enable"]
#[inline(always)]
pub fn ctrl_multicast_en(&mut self) -> CtrlMulticastEnW<CtrlSpec> {
CtrlMulticastEnW::new(self, 11)
}
#[doc = "Bit 16 - RMII mode"]
#[inline(always)]
pub fn ctrl_rmii_mode(&mut self) -> CtrlRmiiModeW<CtrlSpec> {
CtrlRmiiModeW::new(self, 16)
}
}
#[doc = "Control register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CtrlSpec;
impl crate::RegisterSpec for CtrlSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"]
impl crate::Readable for CtrlSpec {}
#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"]
impl crate::Writable for CtrlSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets CTRL to value 0"]
impl crate::Resettable for CtrlSpec {}
}
#[doc = "STAT (rw) register accessor: Status register\n\nYou can [`read`](crate::Reg::read) this register and get [`stat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`stat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stat`] module"]
#[doc(alias = "STAT")]
pub type Stat = crate::Reg<stat::StatSpec>;
#[doc = "Status register"]
pub mod stat {
#[doc = "Register `STAT` reader"]
pub type R = crate::R<StatSpec>;
#[doc = "Register `STAT` writer"]
pub type W = crate::W<StatSpec>;
#[doc = "Field `STAT_RX_ERR` reader - Receive error"]
pub type StatRxErrR = crate::BitReader;
#[doc = "Field `STAT_RX_ERR` writer - Receive error"]
pub type StatRxErrW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `STAT_TX_ERR` reader - Transmit error"]
pub type StatTxErrR = crate::BitReader;
#[doc = "Field `STAT_TX_ERR` writer - Transmit error"]
pub type StatTxErrW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `STAT_RX_INT` reader - Receive interrupt"]
pub type StatRxIntR = crate::BitReader;
#[doc = "Field `STAT_RX_INT` writer - Receive interrupt"]
pub type StatRxIntW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `STAT_TX_INT` reader - Transmit interrupt"]
pub type StatTxIntR = crate::BitReader;
#[doc = "Field `STAT_TX_INT` writer - Transmit interrupt"]
pub type StatTxIntW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `STAT_RX_AHBERR` reader - Receive AHB error"]
pub type StatRxAhberrR = crate::BitReader;
#[doc = "Field `STAT_RX_AHBERR` writer - Receive AHB error"]
pub type StatRxAhberrW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `STAT_TX_AHBERR` reader - Transmit AHB error"]
pub type StatTxAhberrR = crate::BitReader;
#[doc = "Field `STAT_TX_AHBERR` writer - Transmit AHB error"]
pub type StatTxAhberrW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `STAT_TOO_SMALL` reader - Too small. Packet received is smaller than minimum size"]
pub type StatTooSmallR = crate::BitReader;
#[doc = "Field `STAT_TOO_SMALL` writer - Too small. Packet received is smaller than minimum size"]
pub type StatTooSmallW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `STAT_INV_ADDR` reader - Invalid address"]
pub type StatInvAddrR = crate::BitReader;
#[doc = "Field `STAT_INV_ADDR` writer - Invalid address"]
pub type StatInvAddrW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `STAT_PHY_STAT` reader - PHY status change"]
pub type StatPhyStatR = crate::BitReader;
#[doc = "Field `STAT_PHY_STAT` writer - PHY status change"]
pub type StatPhyStatW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - Receive error"]
#[inline(always)]
pub fn stat_rx_err(&self) -> StatRxErrR {
StatRxErrR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Transmit error"]
#[inline(always)]
pub fn stat_tx_err(&self) -> StatTxErrR {
StatTxErrR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Receive interrupt"]
#[inline(always)]
pub fn stat_rx_int(&self) -> StatRxIntR {
StatRxIntR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Transmit interrupt"]
#[inline(always)]
pub fn stat_tx_int(&self) -> StatTxIntR {
StatTxIntR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Receive AHB error"]
#[inline(always)]
pub fn stat_rx_ahberr(&self) -> StatRxAhberrR {
StatRxAhberrR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Transmit AHB error"]
#[inline(always)]
pub fn stat_tx_ahberr(&self) -> StatTxAhberrR {
StatTxAhberrR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Too small. Packet received is smaller than minimum size"]
#[inline(always)]
pub fn stat_too_small(&self) -> StatTooSmallR {
StatTooSmallR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Invalid address"]
#[inline(always)]
pub fn stat_inv_addr(&self) -> StatInvAddrR {
StatInvAddrR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - PHY status change"]
#[inline(always)]
pub fn stat_phy_stat(&self) -> StatPhyStatR {
StatPhyStatR::new(((self.bits >> 8) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Receive error"]
#[inline(always)]
pub fn stat_rx_err(&mut self) -> StatRxErrW<StatSpec> {
StatRxErrW::new(self, 0)
}
#[doc = "Bit 1 - Transmit error"]
#[inline(always)]
pub fn stat_tx_err(&mut self) -> StatTxErrW<StatSpec> {
StatTxErrW::new(self, 1)
}
#[doc = "Bit 2 - Receive interrupt"]
#[inline(always)]
pub fn stat_rx_int(&mut self) -> StatRxIntW<StatSpec> {
StatRxIntW::new(self, 2)
}
#[doc = "Bit 3 - Transmit interrupt"]
#[inline(always)]
pub fn stat_tx_int(&mut self) -> StatTxIntW<StatSpec> {
StatTxIntW::new(self, 3)
}
#[doc = "Bit 4 - Receive AHB error"]
#[inline(always)]
pub fn stat_rx_ahberr(&mut self) -> StatRxAhberrW<StatSpec> {
StatRxAhberrW::new(self, 4)
}
#[doc = "Bit 5 - Transmit AHB error"]
#[inline(always)]
pub fn stat_tx_ahberr(&mut self) -> StatTxAhberrW<StatSpec> {
StatTxAhberrW::new(self, 5)
}
#[doc = "Bit 6 - Too small. Packet received is smaller than minimum size"]
#[inline(always)]
pub fn stat_too_small(&mut self) -> StatTooSmallW<StatSpec> {
StatTooSmallW::new(self, 6)
}
#[doc = "Bit 7 - Invalid address"]
#[inline(always)]
pub fn stat_inv_addr(&mut self) -> StatInvAddrW<StatSpec> {
StatInvAddrW::new(self, 7)
}
#[doc = "Bit 8 - PHY status change"]
#[inline(always)]
pub fn stat_phy_stat(&mut self) -> StatPhyStatW<StatSpec> {
StatPhyStatW::new(self, 8)
}
}
#[doc = "Status register\n\nYou can [`read`](crate::Reg::read) this register and get [`stat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`stat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct StatSpec;
impl crate::RegisterSpec for StatSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`stat::R`](R) reader structure"]
impl crate::Readable for StatSpec {}
#[doc = "`write(|w| ..)` method takes [`stat::W`](W) writer structure"]
impl crate::Writable for StatSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets STAT to value 0"]
impl crate::Resettable for StatSpec {}
}
#[doc = "MACMSB (rw) register accessor: Mac address MSB\n\nYou can [`read`](crate::Reg::read) this register and get [`macmsb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`macmsb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@macmsb`] module"]
#[doc(alias = "MACMSB")]
pub type Macmsb = crate::Reg<macmsb::MacmsbSpec>;
#[doc = "Mac address MSB"]
pub mod macmsb {
#[doc = "Register `MACMSB` reader"]
pub type R = crate::R<MacmsbSpec>;
#[doc = "Register `MACMSB` writer"]
pub type W = crate::W<MacmsbSpec>;
#[doc = "Field `MACMSB` reader - Mac address MSB"]
pub type MacmsbR = crate::FieldReader<u32>;
#[doc = "Field `MACMSB` writer - Mac address MSB"]
pub type MacmsbW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - Mac address MSB"]
#[inline(always)]
pub fn macmsb(&self) -> MacmsbR {
MacmsbR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - Mac address MSB"]
#[inline(always)]
pub fn macmsb(&mut self) -> MacmsbW<MacmsbSpec> {
MacmsbW::new(self, 0)
}
}
#[doc = "Mac address MSB\n\nYou can [`read`](crate::Reg::read) this register and get [`macmsb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`macmsb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MacmsbSpec;
impl crate::RegisterSpec for MacmsbSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`macmsb::R`](R) reader structure"]
impl crate::Readable for MacmsbSpec {}
#[doc = "`write(|w| ..)` method takes [`macmsb::W`](W) writer structure"]
impl crate::Writable for MacmsbSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets MACMSB to value 0"]
impl crate::Resettable for MacmsbSpec {}
}
#[doc = "MACLSB (rw) register accessor: Mac address LSB\n\nYou can [`read`](crate::Reg::read) this register and get [`maclsb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`maclsb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@maclsb`] module"]
#[doc(alias = "MACLSB")]
pub type Maclsb = crate::Reg<maclsb::MaclsbSpec>;
#[doc = "Mac address LSB"]
pub mod maclsb {
#[doc = "Register `MACLSB` reader"]
pub type R = crate::R<MaclsbSpec>;
#[doc = "Register `MACLSB` writer"]
pub type W = crate::W<MaclsbSpec>;
#[doc = "Field `MACLSB` reader - Mac address LSB"]
pub type MaclsbR = crate::FieldReader<u32>;
#[doc = "Field `MACLSB` writer - Mac address LSB"]
pub type MaclsbW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - Mac address LSB"]
#[inline(always)]
pub fn maclsb(&self) -> MaclsbR {
MaclsbR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - Mac address LSB"]
#[inline(always)]
pub fn maclsb(&mut self) -> MaclsbW<MaclsbSpec> {
MaclsbW::new(self, 0)
}
}
#[doc = "Mac address LSB\n\nYou can [`read`](crate::Reg::read) this register and get [`maclsb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`maclsb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MaclsbSpec;
impl crate::RegisterSpec for MaclsbSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`maclsb::R`](R) reader structure"]
impl crate::Readable for MaclsbSpec {}
#[doc = "`write(|w| ..)` method takes [`maclsb::W`](W) writer structure"]
impl crate::Writable for MaclsbSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets MACLSB to value 0"]
impl crate::Resettable for MaclsbSpec {}
}
#[doc = "MDIO (rw) register accessor: MDIO control and status register\n\nYou can [`read`](crate::Reg::read) this register and get [`mdio::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mdio::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mdio`] module"]
#[doc(alias = "MDIO")]
pub type Mdio = crate::Reg<mdio::MdioSpec>;
#[doc = "MDIO control and status register"]
pub mod mdio {
#[doc = "Register `MDIO` reader"]
pub type R = crate::R<MdioSpec>;
#[doc = "Register `MDIO` writer"]
pub type W = crate::W<MdioSpec>;
#[doc = "Field `MDIO_WRITE` reader - MDIO write"]
pub type MdioWriteR = crate::BitReader;
#[doc = "Field `MDIO_WRITE` writer - MDIO write"]
pub type MdioWriteW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MDIO_READ` reader - MDIO read"]
pub type MdioReadR = crate::BitReader;
#[doc = "Field `MDIO_READ` writer - MDIO read"]
pub type MdioReadW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MDIO_LINK_FAIL` reader - Link fail, read only"]
pub type MdioLinkFailR = crate::BitReader;
#[doc = "Field `MDIO_BUSY` reader - MDIO busy, read only"]
pub type MdioBusyR = crate::BitReader;
#[doc = "MDC Scaler\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum MdioMdcsc {
#[doc = "0: Div 128"]
Div128 = 0,
#[doc = "1: Div 64"]
Div64 = 1,
#[doc = "2: Div 32"]
Div32 = 2,
#[doc = "3: Div 16"]
Div16 = 3,
}
impl From<MdioMdcsc> for u8 {
#[inline(always)]
fn from(variant: MdioMdcsc) -> Self {
variant as _
}
}
impl crate::FieldSpec for MdioMdcsc {
type Ux = u8;
}
impl crate::IsEnum for MdioMdcsc {}
#[doc = "Field `MDIO_MDCSC` reader - MDC Scaler"]
pub type MdioMdcscR = crate::FieldReader<MdioMdcsc>;
impl MdioMdcscR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> MdioMdcsc {
match self.bits {
0 => MdioMdcsc::Div128,
1 => MdioMdcsc::Div64,
2 => MdioMdcsc::Div32,
3 => MdioMdcsc::Div16,
_ => unreachable!(),
}
}
#[doc = "Div 128"]
#[inline(always)]
pub fn is_div128(&self) -> bool {
*self == MdioMdcsc::Div128
}
#[doc = "Div 64"]
#[inline(always)]
pub fn is_div64(&self) -> bool {
*self == MdioMdcsc::Div64
}
#[doc = "Div 32"]
#[inline(always)]
pub fn is_div32(&self) -> bool {
*self == MdioMdcsc::Div32
}
#[doc = "Div 16"]
#[inline(always)]
pub fn is_div16(&self) -> bool {
*self == MdioMdcsc::Div16
}
}
#[doc = "Field `MDIO_MDCSC` writer - MDC Scaler"]
pub type MdioMdcscW<'a, REG> = crate::FieldWriter<'a, REG, 2, MdioMdcsc, crate::Safe>;
impl<'a, REG> MdioMdcscW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Div 128"]
#[inline(always)]
pub fn div128(self) -> &'a mut crate::W<REG> {
self.variant(MdioMdcsc::Div128)
}
#[doc = "Div 64"]
#[inline(always)]
pub fn div64(self) -> &'a mut crate::W<REG> {
self.variant(MdioMdcsc::Div64)
}
#[doc = "Div 32"]
#[inline(always)]
pub fn div32(self) -> &'a mut crate::W<REG> {
self.variant(MdioMdcsc::Div32)
}
#[doc = "Div 16"]
#[inline(always)]
pub fn div16(self) -> &'a mut crate::W<REG> {
self.variant(MdioMdcsc::Div16)
}
}
#[doc = "Field `MDIO_REGADDR` reader - Register address"]
pub type MdioRegaddrR = crate::FieldReader;
#[doc = "Field `MDIO_REGADDR` writer - Register address"]
pub type MdioRegaddrW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
#[doc = "Field `MDIO_PHYADDR` reader - PHY address"]
pub type MdioPhyaddrR = crate::FieldReader;
#[doc = "Field `MDIO_PHYADDR` writer - PHY address"]
pub type MdioPhyaddrW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
#[doc = "Field `MDIO_DATA` reader - Data to/from PHY"]
pub type MdioDataR = crate::FieldReader<u16>;
#[doc = "Field `MDIO_DATA` writer - Data to/from PHY"]
pub type MdioDataW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bit 0 - MDIO write"]
#[inline(always)]
pub fn mdio_write(&self) -> MdioWriteR {
MdioWriteR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - MDIO read"]
#[inline(always)]
pub fn mdio_read(&self) -> MdioReadR {
MdioReadR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Link fail, read only"]
#[inline(always)]
pub fn mdio_link_fail(&self) -> MdioLinkFailR {
MdioLinkFailR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - MDIO busy, read only"]
#[inline(always)]
pub fn mdio_busy(&self) -> MdioBusyR {
MdioBusyR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bits 4:5 - MDC Scaler"]
#[inline(always)]
pub fn mdio_mdcsc(&self) -> MdioMdcscR {
MdioMdcscR::new(((self.bits >> 4) & 3) as u8)
}
#[doc = "Bits 6:10 - Register address"]
#[inline(always)]
pub fn mdio_regaddr(&self) -> MdioRegaddrR {
MdioRegaddrR::new(((self.bits >> 6) & 0x1f) as u8)
}
#[doc = "Bits 11:15 - PHY address"]
#[inline(always)]
pub fn mdio_phyaddr(&self) -> MdioPhyaddrR {
MdioPhyaddrR::new(((self.bits >> 11) & 0x1f) as u8)
}
#[doc = "Bits 16:31 - Data to/from PHY"]
#[inline(always)]
pub fn mdio_data(&self) -> MdioDataR {
MdioDataR::new(((self.bits >> 16) & 0xffff) as u16)
}
}
impl W {
#[doc = "Bit 0 - MDIO write"]
#[inline(always)]
pub fn mdio_write(&mut self) -> MdioWriteW<MdioSpec> {
MdioWriteW::new(self, 0)
}
#[doc = "Bit 1 - MDIO read"]
#[inline(always)]
pub fn mdio_read(&mut self) -> MdioReadW<MdioSpec> {
MdioReadW::new(self, 1)
}
#[doc = "Bits 4:5 - MDC Scaler"]
#[inline(always)]
pub fn mdio_mdcsc(&mut self) -> MdioMdcscW<MdioSpec> {
MdioMdcscW::new(self, 4)
}
#[doc = "Bits 6:10 - Register address"]
#[inline(always)]
pub fn mdio_regaddr(&mut self) -> MdioRegaddrW<MdioSpec> {
MdioRegaddrW::new(self, 6)
}
#[doc = "Bits 11:15 - PHY address"]
#[inline(always)]
pub fn mdio_phyaddr(&mut self) -> MdioPhyaddrW<MdioSpec> {
MdioPhyaddrW::new(self, 11)
}
#[doc = "Bits 16:31 - Data to/from PHY"]
#[inline(always)]
pub fn mdio_data(&mut self) -> MdioDataW<MdioSpec> {
MdioDataW::new(self, 16)
}
}
#[doc = "MDIO control and status register\n\nYou can [`read`](crate::Reg::read) this register and get [`mdio::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mdio::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MdioSpec;
impl crate::RegisterSpec for MdioSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`mdio::R`](R) reader structure"]
impl crate::Readable for MdioSpec {}
#[doc = "`write(|w| ..)` method takes [`mdio::W`](W) writer structure"]
impl crate::Writable for MdioSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets MDIO to value 0"]
impl crate::Resettable for MdioSpec {}
}
#[doc = "TXBASE (rw) register accessor: Transmit descriptor table base address\n\nYou can [`read`](crate::Reg::read) this register and get [`txbase::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txbase::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txbase`] module"]
#[doc(alias = "TXBASE")]
pub type Txbase = crate::Reg<txbase::TxbaseSpec>;
#[doc = "Transmit descriptor table base address"]
pub mod txbase {
#[doc = "Register `TXBASE` reader"]
pub type R = crate::R<TxbaseSpec>;
#[doc = "Register `TXBASE` writer"]
pub type W = crate::W<TxbaseSpec>;
#[doc = "Field `TXBASE` reader - Transmit descriptor table base address"]
pub type TxbaseR = crate::FieldReader<u32>;
#[doc = "Field `TXBASE` writer - Transmit descriptor table base address"]
pub type TxbaseW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - Transmit descriptor table base address"]
#[inline(always)]
pub fn txbase(&self) -> TxbaseR {
TxbaseR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - Transmit descriptor table base address"]
#[inline(always)]
pub fn txbase(&mut self) -> TxbaseW<TxbaseSpec> {
TxbaseW::new(self, 0)
}
}
#[doc = "Transmit descriptor table base address\n\nYou can [`read`](crate::Reg::read) this register and get [`txbase::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txbase::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TxbaseSpec;
impl crate::RegisterSpec for TxbaseSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`txbase::R`](R) reader structure"]
impl crate::Readable for TxbaseSpec {}
#[doc = "`write(|w| ..)` method takes [`txbase::W`](W) writer structure"]
impl crate::Writable for TxbaseSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets TXBASE to value 0"]
impl crate::Resettable for TxbaseSpec {}
}
#[doc = "RXBASE (rw) register accessor: Receive descriptor table base address\n\nYou can [`read`](crate::Reg::read) this register and get [`rxbase::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxbase::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxbase`] module"]
#[doc(alias = "RXBASE")]
pub type Rxbase = crate::Reg<rxbase::RxbaseSpec>;
#[doc = "Receive descriptor table base address"]
pub mod rxbase {
#[doc = "Register `RXBASE` reader"]
pub type R = crate::R<RxbaseSpec>;
#[doc = "Register `RXBASE` writer"]
pub type W = crate::W<RxbaseSpec>;
#[doc = "Field `RXBASE` reader - Receive descriptor table base address"]
pub type RxbaseR = crate::FieldReader<u32>;
#[doc = "Field `RXBASE` writer - Receive descriptor table base address"]
pub type RxbaseW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - Receive descriptor table base address"]
#[inline(always)]
pub fn rxbase(&self) -> RxbaseR {
RxbaseR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - Receive descriptor table base address"]
#[inline(always)]
pub fn rxbase(&mut self) -> RxbaseW<RxbaseSpec> {
RxbaseW::new(self, 0)
}
}
#[doc = "Receive descriptor table base address\n\nYou can [`read`](crate::Reg::read) this register and get [`rxbase::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxbase::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RxbaseSpec;
impl crate::RegisterSpec for RxbaseSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`rxbase::R`](R) reader structure"]
impl crate::Readable for RxbaseSpec {}
#[doc = "`write(|w| ..)` method takes [`rxbase::W`](W) writer structure"]
impl crate::Writable for RxbaseSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets RXBASE to value 0"]
impl crate::Resettable for RxbaseSpec {}
}
#[doc = "HTMSB (rw) register accessor: Hash table MSB\n\nYou can [`read`](crate::Reg::read) this register and get [`htmsb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`htmsb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@htmsb`] module"]
#[doc(alias = "HTMSB")]
pub type Htmsb = crate::Reg<htmsb::HtmsbSpec>;
#[doc = "Hash table MSB"]
pub mod htmsb {
#[doc = "Register `HTMSB` reader"]
pub type R = crate::R<HtmsbSpec>;
#[doc = "Register `HTMSB` writer"]
pub type W = crate::W<HtmsbSpec>;
#[doc = "Field `HTMSB` reader - Hash table MSB"]
pub type HtmsbR = crate::FieldReader<u32>;
#[doc = "Field `HTMSB` writer - Hash table MSB"]
pub type HtmsbW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - Hash table MSB"]
#[inline(always)]
pub fn htmsb(&self) -> HtmsbR {
HtmsbR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - Hash table MSB"]
#[inline(always)]
pub fn htmsb(&mut self) -> HtmsbW<HtmsbSpec> {
HtmsbW::new(self, 0)
}
}
#[doc = "Hash table MSB\n\nYou can [`read`](crate::Reg::read) this register and get [`htmsb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`htmsb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HtmsbSpec;
impl crate::RegisterSpec for HtmsbSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`htmsb::R`](R) reader structure"]
impl crate::Readable for HtmsbSpec {}
#[doc = "`write(|w| ..)` method takes [`htmsb::W`](W) writer structure"]
impl crate::Writable for HtmsbSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets HTMSB to value 0"]
impl crate::Resettable for HtmsbSpec {}
}
#[doc = "HTLSB (rw) register accessor: Hash table LSB\n\nYou can [`read`](crate::Reg::read) this register and get [`htlsb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`htlsb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@htlsb`] module"]
#[doc(alias = "HTLSB")]
pub type Htlsb = crate::Reg<htlsb::HtlsbSpec>;
#[doc = "Hash table LSB"]
pub mod htlsb {
#[doc = "Register `HTLSB` reader"]
pub type R = crate::R<HtlsbSpec>;
#[doc = "Register `HTLSB` writer"]
pub type W = crate::W<HtlsbSpec>;
#[doc = "Field `HTLSB` reader - Hash table LSB"]
pub type HtlsbR = crate::FieldReader<u32>;
#[doc = "Field `HTLSB` writer - Hash table LSB"]
pub type HtlsbW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - Hash table LSB"]
#[inline(always)]
pub fn htlsb(&self) -> HtlsbR {
HtlsbR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - Hash table LSB"]
#[inline(always)]
pub fn htlsb(&mut self) -> HtlsbW<HtlsbSpec> {
HtlsbW::new(self, 0)
}
}
#[doc = "Hash table LSB\n\nYou can [`read`](crate::Reg::read) this register and get [`htlsb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`htlsb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HtlsbSpec;
impl crate::RegisterSpec for HtlsbSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`htlsb::R`](R) reader structure"]
impl crate::Readable for HtlsbSpec {}
#[doc = "`write(|w| ..)` method takes [`htlsb::W`](W) writer structure"]
impl crate::Writable for HtlsbSpec {
type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets HTLSB to value 0"]
impl crate::Resettable for HtlsbSpec {}
}
}
#[no_mangle]
static mut DEVICE_PERIPHERALS: bool = false;
#[doc = r" All the peripherals."]
#[allow(non_snake_case)]
pub struct Peripherals {
#[doc = "CLINT"]
pub clint: Clint,
#[doc = "PLIC"]
pub plic: Plic,
#[doc = "RTC"]
pub rtc: Rtc,
#[doc = "SYS"]
pub sys: Sys,
#[doc = "FLASH"]
pub flash: Flash,
#[doc = "FCB0"]
pub fcb0: Fcb0,
#[doc = "WATCHDOG0"]
pub watchdog0: Watchdog0,
#[doc = "SPI0"]
pub spi0: Spi0,
#[doc = "SPI1"]
pub spi1: Spi1,
#[doc = "GPIO0"]
pub gpio0: Gpio0,
#[doc = "GPIO1"]
pub gpio1: Gpio1,
#[doc = "GPIO2"]
pub gpio2: Gpio2,
#[doc = "GPIO3"]
pub gpio3: Gpio3,
#[doc = "GPIO4"]
pub gpio4: Gpio4,
#[doc = "GPIO5"]
pub gpio5: Gpio5,
#[doc = "GPIO6"]
pub gpio6: Gpio6,
#[doc = "GPIO7"]
pub gpio7: Gpio7,
#[doc = "GPIO8"]
pub gpio8: Gpio8,
#[doc = "GPIO9"]
pub gpio9: Gpio9,
#[doc = "TIMER0"]
pub timer0: Timer0,
#[doc = "TIMER1"]
pub timer1: Timer1,
#[doc = "GPTIMER0"]
pub gptimer0: Gptimer0,
#[doc = "GPTIMER1"]
pub gptimer1: Gptimer1,
#[doc = "GPTIMER2"]
pub gptimer2: Gptimer2,
#[doc = "GPTIMER3"]
pub gptimer3: Gptimer3,
#[doc = "GPTIMER4"]
pub gptimer4: Gptimer4,
#[doc = "UART0"]
pub uart0: Uart0,
#[doc = "UART1"]
pub uart1: Uart1,
#[doc = "UART2"]
pub uart2: Uart2,
#[doc = "UART3"]
pub uart3: Uart3,
#[doc = "UART4"]
pub uart4: Uart4,
#[doc = "CAN0"]
pub can0: Can0,
#[doc = "I2C0"]
pub i2c0: I2c0,
#[doc = "I2C1"]
pub i2c1: I2c1,
#[doc = "DMAC0"]
pub dmac0: Dmac0,
#[doc = "USB0"]
pub usb0: Usb0,
#[doc = "CRC0"]
pub crc0: Crc0,
#[doc = "MAC0"]
pub mac0: Mac0,
}
impl Peripherals {
#[doc = r" Returns all the peripherals *once*."]
#[cfg(feature = "critical-section")]
#[inline]
pub fn take() -> Option<Self> {
critical_section::with(|_| {
if unsafe { DEVICE_PERIPHERALS } {
return None;
}
Some(unsafe { Peripherals::steal() })
})
}
#[doc = r" Unchecked version of `Peripherals::take`."]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" Each of the returned peripherals must be used at most once."]
#[inline]
pub unsafe fn steal() -> Self {
DEVICE_PERIPHERALS = true;
Peripherals {
clint: Clint::steal(),
plic: Plic::steal(),
rtc: Rtc::steal(),
sys: Sys::steal(),
flash: Flash::steal(),
fcb0: Fcb0::steal(),
watchdog0: Watchdog0::steal(),
spi0: Spi0::steal(),
spi1: Spi1::steal(),
gpio0: Gpio0::steal(),
gpio1: Gpio1::steal(),
gpio2: Gpio2::steal(),
gpio3: Gpio3::steal(),
gpio4: Gpio4::steal(),
gpio5: Gpio5::steal(),
gpio6: Gpio6::steal(),
gpio7: Gpio7::steal(),
gpio8: Gpio8::steal(),
gpio9: Gpio9::steal(),
timer0: Timer0::steal(),
timer1: Timer1::steal(),
gptimer0: Gptimer0::steal(),
gptimer1: Gptimer1::steal(),
gptimer2: Gptimer2::steal(),
gptimer3: Gptimer3::steal(),
gptimer4: Gptimer4::steal(),
uart0: Uart0::steal(),
uart1: Uart1::steal(),
uart2: Uart2::steal(),
uart3: Uart3::steal(),
uart4: Uart4::steal(),
can0: Can0::steal(),
i2c0: I2c0::steal(),
i2c1: I2c1::steal(),
dmac0: Dmac0::steal(),
usb0: Usb0::steal(),
crc0: Crc0::steal(),
mac0: Mac0::steal(),
}
}
}