ADuCM302x/
clkg0_clk.rs

1#[doc = r"Register block"]
2#[repr(C)]
3pub struct RegisterBlock {
4    #[doc = "0x00 - Miscellaneous Clock Settings"]
5    pub ctl0: CTL0,
6    #[doc = "0x04 - Clock Dividers"]
7    pub ctl1: CTL1,
8    _reserved2: [u8; 4usize],
9    #[doc = "0x0c - System PLL"]
10    pub ctl3: CTL3,
11    _reserved3: [u8; 4usize],
12    #[doc = "0x14 - User Clock Gating Control"]
13    pub ctl5: CTL5,
14    #[doc = "0x18 - Clocking Status"]
15    pub stat0: STAT0,
16}
17#[doc = "Miscellaneous Clock Settings\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctl0](ctl0) module"]
18pub type CTL0 = crate::Reg<u32, _CTL0>;
19#[allow(missing_docs)]
20#[doc(hidden)]
21pub struct _CTL0;
22#[doc = "`read()` method returns [ctl0::R](ctl0::R) reader structure"]
23impl crate::Readable for CTL0 {}
24#[doc = "`write(|w| ..)` method takes [ctl0::W](ctl0::W) writer structure"]
25impl crate::Writable for CTL0 {}
26#[doc = "Miscellaneous Clock Settings"]
27pub mod ctl0;
28#[doc = "Clock Dividers\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctl1](ctl1) module"]
29pub type CTL1 = crate::Reg<u32, _CTL1>;
30#[allow(missing_docs)]
31#[doc(hidden)]
32pub struct _CTL1;
33#[doc = "`read()` method returns [ctl1::R](ctl1::R) reader structure"]
34impl crate::Readable for CTL1 {}
35#[doc = "`write(|w| ..)` method takes [ctl1::W](ctl1::W) writer structure"]
36impl crate::Writable for CTL1 {}
37#[doc = "Clock Dividers"]
38pub mod ctl1;
39#[doc = "System PLL\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctl3](ctl3) module"]
40pub type CTL3 = crate::Reg<u32, _CTL3>;
41#[allow(missing_docs)]
42#[doc(hidden)]
43pub struct _CTL3;
44#[doc = "`read()` method returns [ctl3::R](ctl3::R) reader structure"]
45impl crate::Readable for CTL3 {}
46#[doc = "`write(|w| ..)` method takes [ctl3::W](ctl3::W) writer structure"]
47impl crate::Writable for CTL3 {}
48#[doc = "System PLL"]
49pub mod ctl3;
50#[doc = "User Clock Gating Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctl5](ctl5) module"]
51pub type CTL5 = crate::Reg<u32, _CTL5>;
52#[allow(missing_docs)]
53#[doc(hidden)]
54pub struct _CTL5;
55#[doc = "`read()` method returns [ctl5::R](ctl5::R) reader structure"]
56impl crate::Readable for CTL5 {}
57#[doc = "`write(|w| ..)` method takes [ctl5::W](ctl5::W) writer structure"]
58impl crate::Writable for CTL5 {}
59#[doc = "User Clock Gating Control"]
60pub mod ctl5;
61#[doc = "Clocking Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [stat0](stat0) module"]
62pub type STAT0 = crate::Reg<u32, _STAT0>;
63#[allow(missing_docs)]
64#[doc(hidden)]
65pub struct _STAT0;
66#[doc = "`read()` method returns [stat0::R](stat0::R) reader structure"]
67impl crate::Readable for STAT0 {}
68#[doc = "`write(|w| ..)` method takes [stat0::W](stat0::W) writer structure"]
69impl crate::Writable for STAT0 {}
70#[doc = "Clocking Status"]
71pub mod stat0;
ADuCM302x/clkg0_clk.rs

ADuCM302x/
clkg0_clk.rs
