Struct cranelift_codegen::machinst::vcode::VCode [−][src]
pub struct VCode<I: VCodeInst> { /* fields omitted */ }
Expand description
A function in “VCode” (virtualized-register code) form, after lowering. This is essentially a standard CFG of basic blocks, where each basic block consists of lowered instructions produced by the machine-specific backend.
Implementations
Get the IR-level type of a VReg.
Are there any reference-typed values at all among the vregs?
Get the entry block.
Get the number of blocks. Block indices will be in the range 0 .. (self.num_blocks() - 1)
.
Stack frame size for the full function’s body.
Inbound stack-args size.
Get the successors for a block.
Take the results of register allocation, with a sequence of instructions including spliced fill/reload/move instructions, and replace the VCode with them.
pub fn emit(
&self
) -> (MachBuffer<I>, Vec<CodeOffset>, Vec<(CodeOffset, CodeOffset)>) where
I: MachInstEmit,
[src]
pub fn emit(
&self
) -> (MachBuffer<I>, Vec<CodeOffset>, Vec<(CodeOffset, CodeOffset)>) where
I: MachInstEmit,
[src]Emit the instructions to a MachBuffer
, containing fixed-up code and external
reloc/trap/etc. records ready for use.
Generates value-label ranges.
Get the offsets of stackslots.
Get the IR block for a BlockIndex, if one exists.
Trait Implementations
type Inst = I
type Inst = I
Regalloc is parameterized on F: Function and so can use the projected type F::Inst. Read more
Allow access to the underlying vector of instructions.
Allow mutable access to the underlying vector of instructions.
Get a mutable borrow of an instruction with the given type-safe InstIx index. Read more
Get the index of the entry block.
Provide the range of instruction indices contained in each block.
Get CFG successors for a given block.
Determine whether an instruction is a return instruction.
Determine whether an instruction should be considered while computing
the set of registers that need to be saved/restored in the function’s
prologue/epilogue, that is, the registers returned in
clobbered_registers
in RegAllocResult
. computation. Only
instructions for which this function returns true
will be used to
compute that set. Read more
Add to collector
the used, defined, and modified registers for an
instruction. Read more
Map each register slot through a virtual-to-real mapping indexed
by virtual register. The two separate maps in maps.pre
and
maps.post
provide the mapping to use for uses (which semantically
occur just prior to the instruction’s effect) and defs (which
semantically occur just after the instruction’s effect). Regs that were
“modified” can use either map; the vreg should be the same in both. Read more
Allow the regalloc to query whether this is a move. Returns (dst, src).
Get the precise number of VirtualReg
in use in this function, to allow preallocating data
structures. This number must be a correct lower-bound, otherwise invalid index failures
may happen; it is of course better if it is exact. Read more
How many logical spill slots does the given regclass require? E.g., on a 64-bit machine, spill slots may nominally be 64-bit words, but a 128-bit vector value will require two slots. The regalloc will always align on this size. Read more
Generate a spill instruction for insertion into the instruction sequence. The associated virtual register (whose value is being spilled) is passed, if it exists, so that the client may make decisions about the instruction to generate based on the type of value in question. Because the register allocator will insert spill instructions at arbitrary points, the returned instruction here must not modify the machine’s condition codes. Read more
fn gen_reload(
&self,
to_reg: Writable<RealReg>,
from_slot: SpillSlot,
vreg: Option<VirtualReg>
) -> I
[src]
fn gen_reload(
&self,
to_reg: Writable<RealReg>,
from_slot: SpillSlot,
vreg: Option<VirtualReg>
) -> I
[src]Generate a reload instruction for insertion into the instruction sequence. The associated virtual register (whose value is being loaded) is passed as well, if it exists. The returned instruction must not modify the machine’s condition codes. Read more
Generate a register-to-register move for insertion into the instruction sequence. The associated virtual register is passed as well. The returned instruction must not modify the machine’s condition codes. Read more
Generate an instruction which is a no-op and has zero length.
Try to alter an existing instruction to use a value directly in a spillslot (accessing memory directly) instead of the given register. May be useful on ISAs that have mem/reg ops, like x86. Read more
Return the set of registers that should be considered live at the beginning of the function. This is semantically equivalent to an instruction at the top of the entry block def’ing all registers in this set. Read more
Return the set of registers that should be considered live at the end of the function (after every return instruction). This is semantically equivalent to an instruction at each block with no successors that uses each of these registers. Read more
Get all instruction indices as an iterable range.
Pretty-printing with RealRegUniverse
context.
Auto Trait Implementations
impl<I> !RefUnwindSafe for VCode<I>
impl<I> !UnwindSafe for VCode<I>