[−][src]Trait cranelift_codegen::machinst::MachInst
A machine instruction.
Associated Types
type LabelUse: MachInstLabelUse
A label-use kind: a type that describes the types of label references that can occur in an instruction.
Required methods
fn get_regs(&self, collector: &mut RegUsageCollector)
Return the registers referenced by this machine instruction along with the modes of reference (use, def, modify).
fn map_regs<RUM: RegUsageMapper>(&mut self, maps: &RUM)
Map virtual registers to physical registers using the given virt->phys maps corresponding to the program points prior to, and after, this instruction.
fn is_move(&self) -> Option<(Writable<Reg>, Reg)>
If this is a simple move, return the (source, destination) tuple of registers.
fn is_term<'a>(&'a self) -> MachTerminator<'a>
Is this a terminator (branch or ret)? If so, return its type (ret/uncond/cond) and target if applicable.
fn is_epilogue_placeholder(&self) -> bool
Returns true if the instruction is an epilogue placeholder.
fn gen_move(to_reg: Writable<Reg>, from_reg: Reg, ty: Type) -> Self
Generate a move.
fn gen_constant(
to_reg: Writable<Reg>,
value: u64,
ty: Type
) -> SmallVec<[Self; 4]>
to_reg: Writable<Reg>,
value: u64,
ty: Type
) -> SmallVec<[Self; 4]>
Generate a constant into a reg.
fn gen_zero_len_nop() -> Self
Generate a zero-length no-op.
fn maybe_direct_reload(&self, reg: VirtualReg, slot: SpillSlot) -> Option<Self>
Possibly operate on a value directly in a spill-slot rather than a register. Useful if the machine has register-memory instruction forms (e.g., add directly from or directly to memory), like x86.
fn rc_for_type(ty: Type) -> CodegenResult<RegClass>
Determine a register class to store the given Cranelift type. May return an error if the type isn't supported by this backend.
fn gen_jump(target: MachLabel) -> Self
Generate a jump to another target. Used during lowering of control flow.
fn gen_nop(preferred_size: usize) -> Self
Generate a NOP. The preferred_size
parameter allows the caller to
request a NOP of that size, or as close to it as possible. The machine
backend may return a NOP whose binary encoding is smaller than the
preferred size, but must not return a NOP that is larger. However,
the instruction must have a nonzero size.
fn reg_universe(flags: &Flags) -> RealRegUniverse
Get the register universe for this backend.
fn worst_case_size() -> CodeOffset
What is the worst-case instruction size emitted by this instruction type?
Provided methods
fn align_basic_block(offset: CodeOffset) -> CodeOffset
Align a basic block offset (from start of function). By default, no alignment occurs.