Expand description
Initial-layout algorithms for quantum compilation.
A layout maps each logical circuit qubit to one usable physical qubit on a target device. This module only chooses that initial mapping. It does not insert SWAP operations, rewrite instructions, or produce a fully routed physical circuit; routing is handled by later compiler stages such as the SABRE routing core.
The shared pipeline is:
analyze_circuit_for_layoutextracts weighted logical interactions from aCircuit.PhysicalLayoutGraph::from_deviceturns aDeviceinto a compiler-local physical topology and calibration view.- A concrete algorithm, such as
trivial_layout,greedy_layout,vf2_perfect_layout, orsabre_layout, returns aLayoutResult.
Mixed quantum/classical circuits are analyzed structurally. Layout analysis
recursively visits if, while, for, and switch bodies so interactions
hidden behind classical control still influence the initial mapping. It does
not estimate branch probabilities, loop trip counts, or runtime paths.
§Examples
use cqlib_core::circuit::{Circuit, Qubit};
use cqlib_core::compile::transform::{LayoutObjective, trivial_layout};
use cqlib_core::device::Device;
let mut circuit = Circuit::new(2);
circuit.cx(Qubit::new(0), Qubit::new(1)).unwrap();
let device = Device::line("line-2", 2).unwrap();
let result = trivial_layout(&circuit, &device, &LayoutObjective::topology_only()).unwrap();
assert!(result.score.is_some());Re-exports§
pub use crate::compile::physical_target::DistanceTable;pub use crate::compile::physical_target::PhysicalLayoutGraph;
Structs§
- Circuit
Layout Analysis - Layout-relevant summary of a circuit.
- Interaction
- One weighted logical interaction between two logical qubits.
- Interaction
Graph - Weighted logical interaction graph.
- Layout
Diagnostics - Diagnostics emitted by layout planning.
- Layout
Objective - Weighted scoring objective used to rank candidate layouts.
- Layout
Result - Candidate or selected layout produced by a concrete layout algorithm.
- Layout
Score - Breakdown of one layout score.
- Prepared
Sabre Circuit - Circuit-side data prepared once for repeated SABRE layout selection.
- Prepared
Sabre Target - Device-side SABRE data prepared for one circuit’s interaction signatures.
- Vf2Layout
Config - Configuration for
vf2_perfect_layout.
Enums§
- Vf2Edge
Requirement - Selects which logical interaction edges must be matched by VF2.
Functions§
- analyze_
circuit_ for_ layout - Extracts layout-relevant interaction data from a circuit.
- greedy_
layout - Builds a deterministic greedy initial layout from weighted interactions.
- greedy_
layout_ prepared - Builds a deterministic greedy layout from an already-built physical graph.
- prepare_
sabre_ circuit - Prepares the circuit-side analysis and dependency models used by SABRE.
- prepare_
sabre_ device_ target - Prepares exact device-native SABRE data for a circuit.
- prepare_
sabre_ topology_ target - Prepares topology-only SABRE data for a circuit.
- sabre_
layout - Selects an initial layout with fused SABRE refinement and routing search.
- sabre_
layout_ prepared - Selects a SABRE initial layout from prepared circuit-side data.
- trivial_
layout - Maps logical qubits to usable physical qubits in their existing order.
- trivial_
layout_ prepared - Maps logical qubits to a prepared physical graph in their existing order.
- vf2_
perfect_ layout - Searches for a perfect initial layout using non-induced VF2++ matching.
- vf2_
perfect_ layout_ prepared - Searches for a perfect initial layout on an already-built physical graph.