Low level access to Cortex-M processors
This crate provides:
- Access to core peripherals like NVIC, SCB and SysTick.
- Access to core registers like CONTROL, MSP and PSR.
- Interrupt manipulation mechanisms
- Safe wrappers around Cortex-M specific instructions like
When this feature is enabled the implementation of all the functions inside the
register modules use inline assembly (
asm!) instead of external assembly (FFI into separate
assembly files pre-compiled using
arm-none-eabi-gcc). The advantages of enabling
Reduced overhead. FFI eliminates the possibility of inlining so all operations include a function call overhead when
inline-asmis not enabled.
Some of the
registerAPI only becomes available only when
inline-asmis enabled. Check the API docs for details.
The disadvantage is that
inline-asm requires a nightly toolchain.
This feature enables workarounds for errata found on Cortex-M7 chips with revision r0p1. Some functions in this crate only work correctly on those chips if this Cargo feature is enabled (the functions are documented accordingly).
This feature links against prebuilt assembly blobs that are compatible with Linker-Plugin LTO.
This allows inlining assembly routines into the caller, even without the
and works on stable Rust (but note the drawbacks below!).
If you want to use this feature, you need to be aware of a few things:
You need to make sure that
-Clinker-plugin-ltois passed to rustc. Please refer to the Linker-Plugin LTO documentation for details.
You have to use a Rust version whose LLVM version is compatible with the toolchain in
Due to a Rust bug in compiler versions before 1.49, this option does not work with optimization levels
This crate is guaranteed to compile on stable Rust 1.38 and up. It might compile with older versions but that may change in any new patch release.
pub use crate::peripheral::Peripherals;
Miscellaneous assembly instructions
Cortex-M Security Extensions
A delay driver based on SysTick.
Instrumentation Trace Macrocell
Processor core registers