Struct cortex_m::peripheral::cpuid::RegisterBlock
[−]
[src]
#[repr(C)]pub struct RegisterBlock { pub base: RO<u32>, pub pfr: [RO<u32>; 2], pub dfr: RO<u32>, pub afr: RO<u32>, pub mmfr: [RO<u32>; 4], pub isar: [RO<u32>; 5], pub clidr: RO<u32>, pub ctr: RO<u32>, pub ccsidr: RO<u32>, pub csselr: RW<u32>, // some fields omitted }
Register block
Fields
base: RO<u32>
CPUID base
pfr: [RO<u32>; 2]
Processor Feature (not present on Cortex-M0 variants)
dfr: RO<u32>
Debug Feature (not present on Cortex-M0 variants)
afr: RO<u32>
Auxiliary Feature (not present on Cortex-M0 variants)
mmfr: [RO<u32>; 4]
Memory Model Feature (not present on Cortex-M0 variants)
isar: [RO<u32>; 5]
Instruction Set Attribute (not present on Cortex-M0 variants)
clidr: RO<u32>
Cache Level ID (only present on Cortex-M7)
ctr: RO<u32>
Cache Type (only present on Cortex-M7)
ccsidr: RO<u32>
Cache Size ID (only present on Cortex-M7)
csselr: RW<u32>
Cache Size Selection (only present on Cortex-M7)