Enum cortex_a::registers::SCTLR_EL2::I::Value

#[repr(u64)]
pub enum Value {
    NonCacheable,
    Cacheable,
}

Instruction Cache Control, two possible values:

0 All instruction access to Normal memory from EL2 are Non-cacheable for all levels of instruction and unified cache.

If the value of SCTLR_EL2.M is 0, instruction accesses from stage 1 of the EL2 or EL2&0 translation regime are to Normal, Outer Shareable, Inner Non-cacheable, Outer Non-cacheable memory.

1 This control has no effect on the Cacheability of instruction access to Normal memory from EL2 and, when EL2 is enabled in the current Security state and HCR_EL2.{E2H, TGE} == {1, 1}, instruction access to Normal memory from EL0.

If the value of SCTLR_EL2.M is 0, instruction accesses from stage 1 of the EL2&0 translation regime are to Normal, Outer Shareable, Inner Write-Through, Outer Write-Through memory.

When EL2 is disabled, and the value of HCR_EL2.{E2H, TGE} is {1, 1}, this bit has no effect on the PE.

On a Warm reset, in a system where the PE resets into EL2, this field resets to 0.

Variants

NonCacheable

Cacheable

Trait Implementations

impl TryFromValue<u64> for Value

type EnumType = Value

fn try_from(v: u64) -> Option<Self::EnumType>