[−][src]Enum cortex_a::regs::HCR_EL2::SWIO::Value
Set/Way Invalidation Override. Causes Non-secure EL1 execution of the data cache invalidate by set/way instructions to perform a data cache clean and invalidate by set/way:
0 This control has no effect on the operation of data cache invalidate by set/way instructions.
1 Data cache invalidate by set/way instructions perform a data cache clean and invalidate by set/way.
When the value of this bit is 1:
AArch32: DCISW performs the same invalidation as a DCCISW instruction.
AArch64: DC ISW performs the same invalidation as a DC CISW instruction.
This bit can be implemented as RES 1.
In an implementation that includes EL3, when the value of SCR_EL3.NS is 0 the PE behaves as if this field is 0 for all purposes other than a direct read or write access of HCR_EL2.
When HCR_EL2.TGE is 1, the PE ignores the value of this field for all purposes other than a direct read of this field.
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