RegisterBlock

corstone300_pac::syscontrol

Struct RegisterBlock 

Source 
#[repr(C)]
pub struct RegisterBlock {
Show 28 fields
    pub secdbgstat: SECDBGSTAT,
    pub secdbgset: SECDBGSET,
    pub secdbgclr: SECDBGCLR,
    pub scsecctrl: SCSECCTRL,
    pub clk_cfg0: CLK_CFG0,
    pub clk_cfg1: CLK_CFG1,
    pub clock_force: CLOCK_FORCE,
    pub reset_syndrome: RESET_SYNDROME,
    pub reset_mask: RESET_MASK,
    pub swreset: SWRESET,
    pub gretreg: GRETREG,
    pub initsvrtor0: INITSVRTOR0,
    pub cpuwait: CPUWAIT,
    pub nmi_enable: NMI_ENABLE,
    pub pwrctrl: PWRCTRL,
    pub pdcm_pd_sys_sense: PDCM_PD_SYS_SENSE,
    pub pdcm_pd_cpu0_sense: PDCM_PD_CPU0_SENSE,
    pub pdcm_pd_vmr0_sense: PDCM_PD_VMR0_SENSE,
    pub pdcm_pd_vmr1_sense: PDCM_PD_VMR1_SENSE,
    pub pidr4: PIDR4,
    pub pidr0: PIDR0,
    pub pidr1: PIDR1,
    pub pidr2: PIDR2,
    pub pidr3: PIDR3,
    pub cidr0: CIDR0,
    pub cidr1: CIDR1,
    pub cidr2: CIDR2,
    pub cidr3: CIDR3,
    /* private fields */

}
Expand description

Register block

Fields§

§secdbgstat: SECDBGSTAT

0x00 - Secure Debug Configuration Status

§secdbgset: SECDBGSET

0x04 - Secure Debug Configuration Set

§secdbgclr: SECDBGCLR

0x08 - Secure Debug Configuration Clear

§scsecctrl: SCSECCTRL

0x0c - System Security Control

§clk_cfg0: CLK_CFG0

0x10 - Clock Configuration Register 0.

§clk_cfg1: CLK_CFG1

0x14 - Clock Configuration Register 1.

§clock_force: CLOCK_FORCE

0x18 - Clock Force

§reset_syndrome: RESET_SYNDROME

0x100 - Reset Syndrome

§reset_mask: RESET_MASK

0x104 - Reset Mask

§swreset: SWRESET

0x108 - Software Reset

§gretreg: GRETREG

0x10c - General Purpose Retention

§initsvrtor0: INITSVRTOR0

0x110 - Initial Secure Reset Vector Register For CPU 0

§cpuwait: CPUWAIT

0x120 - CPU Boot wait control after reset

§nmi_enable: NMI_ENABLE

0x124 - NMI Enable Register

§pwrctrl: PWRCTRL

0x1fc - Power Configuration and Control.

§pdcm_pd_sys_sense: PDCM_PD_SYS_SENSE

0x200 - External Wakeup Control

§pdcm_pd_cpu0_sense: PDCM_PD_CPU0_SENSE

0x204 - PDCM PD_CPU0 Sensitivity.

§pdcm_pd_vmr0_sense: PDCM_PD_VMR0_SENSE

0x214 - PDCM PD_VMR0 Sensitivity.

§pdcm_pd_vmr1_sense: PDCM_PD_VMR1_SENSE

0x218 - PDCM PD_VMR1 Sensitivity.

§pidr4: PIDR4

0xfd0 - Peripheral ID 4

§pidr0: PIDR0

0xfe0 - Peripheral ID 0

§pidr1: PIDR1

0xfe4 - Peripheral ID 1

§pidr2: PIDR2

0xfe8 - Peripheral ID 2

§pidr3: PIDR3

0xfec - Peripheral ID 3

§cidr0: CIDR0

0xff0 - Component ID 0

§cidr1: CIDR1

0xff4 - Component ID 1

§cidr2: CIDR2

0xff8 - Component ID 2

§cidr3: CIDR3

0xffc - Component ID 3

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