Trait ckb_vm::machine::CoreMachine[−][src]

pub trait CoreMachine {
    type REG: Register;
    type MEM: Memory<REG = Self::REG>;
    fn pc(&self) -> &Self::REG;

    fn update_pc(&mut self, pc: Self::REG);

    fn commit_pc(&mut self);

    fn memory(&self) -> &Self::MEM;

    fn memory_mut(&mut self) -> &mut Self::MEM;

    fn registers(&self) -> &[Self::REG]ⓘ
Notable traits for &'_ [u8]
impl<'_> Read for &'_ [u8]impl<'_> Write for &'_ mut [u8]
;

    fn set_register(&mut self, idx: usize, value: Self::REG);

    fn version(&self) -> u32;

    fn isa(&self) -> u8;
}
Expand description

This is the core part of RISC-V that only deals with data part, it is extracted from Machine so we can handle lifetime logic in dynamic syscall support.

Associated Types

Required methods

Implementors