Struct ExcIEEEST7B 

pub struct ExcIEEEST7B {

    pub base: ExcitationSystemDynamics,
    pub kh: Option<f64>,
    pub kia: Option<f64>,
    pub kl: Option<f64>,
    pub kpa: Option<f64>,
    pub oelin: Option<UriRef>,
    pub tb: Option<f64>,
    pub tc: Option<f64>,
    pub tf: Option<f64>,
    pub tg: Option<f64>,
    pub tia: Option<f64>,
    pub uelin: Option<UriRef>,
    pub vmax: Option<f64>,
    pub vmin: Option<f64>,
    pub vrmax: Option<f64>,
    pub vrmin: Option<f64>,
}

IEEE 421.5-2005 type ST7B model. This model is representative of static potential-source excitation systems. In this system, the AVR consists of a PI voltage regulator. A phase lead-lag filter in series allows the introduction of a derivative function, typically used with brushless excitation systems. In that case, the regulator is of the PID type. In addition, the terminal voltage channel includes a phase lead-lag filter. The AVR includes the appropriate inputs on its reference for overexcitation limiter (OEL1), underexcitation limiter (UEL), stator current limiter (SCL), and current compensator (DROOP). All these limitations, when they work at voltage reference level, keep the PSS (VS signal from PSS) in operation. However, the UEL limitation can also be transferred to the high value (HV) gate acting on the output signal. In addition, the output signal passes through a low value (LV) gate for a ceiling overexcitation limiter (OEL2). Reference: IEEE 421.5-2005, 7.7.

Fields

base: ExcitationSystemDynamics

kh: Option<f64>

High-value gate feedback gain (KH) (>= 0). Typical value = 1.

kia: Option<f64>

Voltage regulator integral gain (KIA) (>= 0). Typical value = 1.

kl: Option<f64>

Low-value gate feedback gain (KL) (>= 0). Typical value = 1.

kpa: Option<f64>

Voltage regulator proportional gain (KPA) (> 0). Typical value = 40.

oelin: Option<UriRef>

OEL input selector (OELin). Typical value = noOELinput.

tb: Option<f64>

Regulator lag time constant (TB) (>= 0). Typical value = 1.

tc: Option<f64>

Regulator lead time constant (TC) (>= 0). Typical value = 1.

tf: Option<f64>

Excitation control system stabilizer time constant (TF) (>= 0). Typical value = 1.

tg: Option<f64>

Feedback time constant of inner loop field voltage regulator (TG) (>= 0). Typical value = 1.

tia: Option<f64>

Feedback time constant (TIA) (>= 0). Typical value = 3.

uelin: Option<UriRef>

UEL input selector (UELin). Typical value = noUELinput.

vmax: Option<f64>

Maximum voltage reference signal (VMAX) (> 0 and > ExcIEEEST7B.vmin). Typical value = 1,1.

vmin: Option<f64>

Minimum voltage reference signal (VMIN) (> 0 and < ExcIEEEST7B.vmax). Typical value = 0,9.

vrmax: Option<f64>

Maximum voltage regulator output (VRMAX) (> 0). Typical value = 5.

vrmin: Option<f64>

Minimum voltage regulator output (VRMIN) (< 0). Typical value = -4,5.

Implementations

impl ExcIEEEST7B

pub fn from_block(b: &RdfBlock) -> Self

Trait Implementations

impl CimElement for ExcIEEEST7B

fn mrid(&self) -> &str

fn type_name(&self) -> &'static str

fn as_any(&self) -> &dyn Any

fn to_json_value(&self) -> Value

fn to_block(&self) -> RdfBlock

impl Clone for ExcIEEEST7B

fn clone(&self) -> ExcIEEEST7B

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for ExcIEEEST7B

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for ExcIEEEST7B

fn default() -> ExcIEEEST7B

Returns the “default value” for a type.

impl<'de> Deserialize<'de> for ExcIEEEST7B

fn deserialize<__D>(__deserializer: __D) -> Result<Self, __D::Error>

where __D: Deserializer<'de>,

Deserialize this value from the given Serde deserializer.

impl Serialize for ExcIEEEST7B

fn serialize<__S>(&self, __serializer: __S) -> Result<__S::Ok, __S::Error>

where __S: Serializer,

Serialize this value into the given Serde serializer.