Struct ExcIEEEST4B 

pub struct ExcIEEEST4B {

    pub base: ExcitationSystemDynamics,
    pub kc: Option<f64>,
    pub kg: Option<f64>,
    pub ki: Option<f64>,
    pub kim: Option<f64>,
    pub kir: Option<f64>,
    pub kp: Option<f64>,
    pub kpm: Option<f64>,
    pub kpr: Option<f64>,
    pub ta: Option<f64>,
    pub thetap: Option<f64>,
    pub vbmax: Option<f64>,
    pub vmmax: Option<f64>,
    pub vmmin: Option<f64>,
    pub vrmax: Option<f64>,
    pub vrmin: Option<f64>,
    pub xl: Option<f64>,
}

IEEE 421.5-2005 type ST4B model. This model is a variation of the type ST3A model, with a proportional plus integral (PI) regulator block replacing the lag-lead regulator characteristic that is in the ST3A model. Both potential and compound source rectifier excitation systems are modelled. The PI regulator blocks have non-windup limits that are represented. The voltage regulator of this model is typically implemented digitally. Reference: IEEE 421.5-2005, 7.4.

Fields

base: ExcitationSystemDynamics

kc: Option<f64>

Rectifier loading factor proportional to commutating reactance (KC) (>= 0). Typical value = 0,113.

kg: Option<f64>

Feedback gain constant of the inner loop field regulator (KG) (>= 0). Typical value = 0.

ki: Option<f64>

Potential circuit gain coefficient (KI) (>= 0). Typical value = 0.

kim: Option<f64>

Voltage regulator integral gain output (KIM). Typical value = 0.

kir: Option<f64>

Voltage regulator integral gain (KIR). Typical value = 10,75.

kp: Option<f64>

Potential circuit gain coefficient (KP) (> 0). Typical value = 9,3.

kpm: Option<f64>

Voltage regulator proportional gain output (KPM). Typical value = 1.

kpr: Option<f64>

Voltage regulator proportional gain (KPR). Typical value = 10,75.

ta: Option<f64>

Voltage regulator time constant (TA) (>= 0). Typical value = 0,02.

thetap: Option<f64>

Potential circuit phase angle (thetap). Typical value = 0.

vbmax: Option<f64>

Maximum excitation voltage (VBMax) (> 0). Typical value = 11,63.

vmmax: Option<f64>

Maximum inner loop output (VMMax) (> ExcIEEEST4B.vmmin). Typical value = 99.

vmmin: Option<f64>

Minimum inner loop output (VMMin) (< ExcIEEEST4B.vmmax). Typical value = -99.

vrmax: Option<f64>

Maximum voltage regulator output (VRMAX) (> 0). Typical value = 1.

vrmin: Option<f64>

Minimum voltage regulator output (VRMIN) (< 0). Typical value = -0,87.

xl: Option<f64>

Reactance associated with potential source (XL) (>= 0). Typical value = 0,124.

Implementations

impl ExcIEEEST4B

pub fn from_block(b: &RdfBlock) -> Self

Trait Implementations

impl CimElement for ExcIEEEST4B

fn mrid(&self) -> &str

fn type_name(&self) -> &'static str

fn as_any(&self) -> &dyn Any

fn to_json_value(&self) -> Value

fn to_block(&self) -> RdfBlock

impl Clone for ExcIEEEST4B

fn clone(&self) -> ExcIEEEST4B

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for ExcIEEEST4B

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for ExcIEEEST4B

fn default() -> ExcIEEEST4B

Returns the “default value” for a type.

impl<'de> Deserialize<'de> for ExcIEEEST4B

fn deserialize<__D>(__deserializer: __D) -> Result<Self, __D::Error>

where __D: Deserializer<'de>,

Deserialize this value from the given Serde deserializer.

impl Serialize for ExcIEEEST4B

fn serialize<__S>(&self, __serializer: __S) -> Result<__S::Ok, __S::Error>

where __S: Serializer,

Serialize this value into the given Serde serializer.