Struct ExcIEEEST1A 

pub struct ExcIEEEST1A {

    pub base: ExcitationSystemDynamics,
    pub ilr: Option<f64>,
    pub ka: Option<f64>,
    pub kc: Option<f64>,
    pub kf: Option<f64>,
    pub klr: Option<f64>,
    pub pssin: Option<bool>,
    pub ta: Option<f64>,
    pub tb: Option<f64>,
    pub tb1: Option<f64>,
    pub tc: Option<f64>,
    pub tc1: Option<f64>,
    pub tf: Option<f64>,
    pub uelin: Option<UriRef>,
    pub vamax: Option<f64>,
    pub vamin: Option<f64>,
    pub vimax: Option<f64>,
    pub vimin: Option<f64>,
    pub vrmax: Option<f64>,
    pub vrmin: Option<f64>,
}

IEEE 421.5-2005 type ST1A model. This model represents systems in which excitation power is supplied through a transformer from the generator terminals (or the unit’s auxiliary bus) and is regulated by a controlled rectifier. The maximum exciter voltage available from such systems is directly related to the generator terminal voltage. Reference: IEEE 421.5-2005, 7.1.

Fields

base: ExcitationSystemDynamics

ilr: Option<f64>

Exciter output current limit reference (ILR). Typical value = 0.

ka: Option<f64>

Voltage regulator gain (KA) (> 0). Typical value = 190.

kc: Option<f64>

Rectifier loading factor proportional to commutating reactance (KC) (>= 0). Typical value = 0,08.

kf: Option<f64>

Excitation control system stabilizer gains (KF) (>= 0). Typical value = 0.

klr: Option<f64>

Exciter output current limiter gain (KLR). Typical value = 0.

pssin: Option<bool>

Selector of the Power System Stabilizer (PSS) input (PSSin). true = PSS input (Vs) added to error signal false = PSS input (Vs) added to voltage regulator output. Typical value = true.

ta: Option<f64>

Voltage regulator time constant (TA) (>= 0). Typical value = 0.

tb: Option<f64>

Voltage regulator time constant (TB) (>= 0). Typical value = 10.

tb1: Option<f64>

Voltage regulator time constant (TB1) (>= 0). Typical value = 0.

tc: Option<f64>

Voltage regulator time constant (TC) (>= 0). Typical value = 1.

tc1: Option<f64>

Voltage regulator time constant (TC1) (>= 0). Typical value = 0.

tf: Option<f64>

Excitation control system stabilizer time constant (TF) (>= 0). Typical value = 1.

uelin: Option<UriRef>

Selector of the connection of the UEL input (UELin). Typical value = ignoreUELsignal.

vamax: Option<f64>

Maximum voltage regulator output (VAMAX) (> 0). Typical value = 14,5.

vamin: Option<f64>

Minimum voltage regulator output (VAMIN) (< 0). Typical value = -14,5.

vimax: Option<f64>

Maximum voltage regulator input limit (VIMAX) (> 0). Typical value = 999.

vimin: Option<f64>

Minimum voltage regulator input limit (VIMIN) (< 0). Typical value = -999.

vrmax: Option<f64>

Maximum voltage regulator outputs (VRMAX) (> 0). Typical value = 7,8.

vrmin: Option<f64>

Minimum voltage regulator outputs (VRMIN) (< 0). Typical value = -6,7.

Implementations

impl ExcIEEEST1A

pub fn from_block(b: &RdfBlock) -> Self

Trait Implementations

impl CimElement for ExcIEEEST1A

fn mrid(&self) -> &str

fn type_name(&self) -> &'static str

fn as_any(&self) -> &dyn Any

fn to_json_value(&self) -> Value

fn to_block(&self) -> RdfBlock

impl Clone for ExcIEEEST1A

fn clone(&self) -> ExcIEEEST1A

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for ExcIEEEST1A

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for ExcIEEEST1A

fn default() -> ExcIEEEST1A

Returns the “default value” for a type.

impl<'de> Deserialize<'de> for ExcIEEEST1A

fn deserialize<__D>(__deserializer: __D) -> Result<Self, __D::Error>

where __D: Deserializer<'de>,

Deserialize this value from the given Serde deserializer.

impl Serialize for ExcIEEEST1A

fn serialize<__S>(&self, __serializer: __S) -> Result<__S::Ok, __S::Error>

where __S: Serializer,

Serialize this value into the given Serde serializer.