ch58x_hal::pac::sys

Struct RegisterBlock

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#[repr(C)]
pub struct RegisterBlock { /* private fields */ }
Expand description

Register block

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impl RegisterBlock

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pub const fn clk_sys_cfg(&self) -> &Reg<CLK_SYS_CFG_SPEC>

0x08 - RWA, system clock configuration, SAM

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pub const fn hfck_pwr_ctrl(&self) -> &Reg<HFCK_PWR_CTRL_SPEC>

0x0a - RWA, high frequency clock module power control, SAM

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pub const fn slp_clk_off0(&self) -> &Reg<SLP_CLK_OFF0_SPEC>

0x0c - RWA, sleep clock off control byte 0, SAM

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pub const fn slp_clk_off1(&self) -> &Reg<SLP_CLK_OFF1_SPEC>

0x0d - RWA, sleep clock off control byte 1, SAM

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pub const fn slp_wake_ctrl(&self) -> &Reg<SLP_WAKE_CTRL_SPEC>

0x0e - RWA, wake control, SAM

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pub const fn slp_power_ctrl(&self) -> &Reg<SLP_POWER_CTRL_SPEC>

0x0f - RWA, peripherals power down control, SAM

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pub const fn pin_alternate(&self) -> &Reg<PIN_ALTERNATE_SPEC>

0x18 - RW, function pin alternate configuration

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pub const fn pin_analog_ie(&self) -> &Reg<PIN_ANALOG_IE_SPEC>

0x1a - RW, analog pin enable and digital input disable

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pub const fn power_plan(&self) -> &Reg<POWER_PLAN_SPEC>

0x20 - RWA, power plan before sleep instruction, SAM

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pub const fn aux_power_adj(&self) -> &Reg<AUX_POWER_ADJ_SPEC>

0x22 - RWA, aux power adjust control, SAM

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pub const fn bat_det_ctrl(&self) -> &Reg<BAT_DET_CTRL_SPEC>

0x24 - RWA, battery voltage detector control, SAM

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pub const fn bat_det_cfg(&self) -> &Reg<BAT_DET_CFG_SPEC>

0x25 - RWA, battery voltage detector configuration, SAM

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pub const fn bat_status(&self) -> &Reg<BAT_STATUS_SPEC>

0x26 - RO, battery status

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pub const fn int32k_tune(&self) -> &Reg<INT32K_TUNE_SPEC>

0x2c - RWA, internal 32KHz oscillator tune control, SAM

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pub const fn xt32k_tune(&self) -> &Reg<XT32K_TUNE_SPEC>

0x2e - RWA, external 32KHz oscillator tune control, SAM

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pub const fn ck32k_config(&self) -> &Reg<CK32K_CONFIG_SPEC>

0x2f - RWA, 32KHz oscillator configure

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pub const fn rtc_flag_ctrl(&self) -> &Reg<RTC_FLAG_CTRL_SPEC>

0x30 - RW, RTC flag and clear control

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pub const fn rtc_mode_ctrl(&self) -> &Reg<RTC_MODE_CTRL_SPEC>

0x31 - RWA, RTC mode control, SAM

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pub const fn rtc_trig(&self) -> &Reg<RTC_TRIG_SPEC>

0x34 - RWA, RTC trigger value, SAM

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pub const fn rtc_cnt_32k(&self) -> &Reg<RTC_CNT_32K_SPEC>

0x38 - RO, RTC count based 32KHz

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pub const fn rtc_cnt_2s(&self) -> &Reg<RTC_CNT_2S_SPEC>

0x3a - RO, RTC count based 2 second

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pub const fn rtc_cnt_day(&self) -> &Reg<RTC_CNT_DAY_SPEC>

0x3c - RO, RTC count based one day, only low 14 bit

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pub const fn safe_access_sig(&self) -> &Reg<SAFE_ACCESS_SIG_SPEC>

0x40 - WO, safe accessing sign register, must write SAFE_ACCESS_SIG1 then SAFE_ACCESS_SIG2 to enter safe accessing mode

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pub const fn chip_id(&self) -> &Reg<CHIP_ID_SPEC>

0x41 - RF, chip ID register, always is ID_CH58*

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pub const fn safe_access_id(&self) -> &Reg<SAFE_ACCESS_ID_SPEC>

0x42 - RF, safe accessing ID register, always 0x0C

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pub const fn wdog_count(&self) -> &Reg<WDOG_COUNT_SPEC>

0x43 - RW, watch-dog count, count by clock frequency Fsys/131072

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pub const fn reset_status__glob_rom_cfg( &self, ) -> &Reg<RESET_STATUS__GLOB_ROM_CFG_SPEC>

0x44 - RWA, reset status, SAM or flash ROM configuration

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pub const fn glob_cfg_info(&self) -> &Reg<GLOB_CFG_INFO_SPEC>

0x45 - RO, global configuration information and status

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pub const fn rst_wdog_ctrl(&self) -> &Reg<RST_WDOG_CTRL_SPEC>

0x46 - RWA, reset and watch-dog control, SAM

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pub const fn glob_reset_keep(&self) -> &Reg<GLOB_RESET_KEEP_SPEC>

0x47 - RW, value keeper during global reset

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pub const fn pll_config(&self) -> &Reg<PLL_CONFIG_SPEC>

0x4b - RWA, PLL configuration control, SAM

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pub const fn xt32m_tune(&self) -> &Reg<XT32M_TUNE_SPEC>

0x4e - RWA, external 32MHz oscillator tune control, SAM

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pub const fn osc_cal_cnt(&self) -> &Reg<OSC_CAL_CNT_SPEC>

0x50 - RO, system clock count value for 32KHz multi-cycles

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pub const fn osc_cal_ov_cnt(&self) -> &Reg<OSC_CAL_OV_CNT_SPEC>

0x52 - RO, oscillator frequency calibration overflow times

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pub const fn osc_cal_ctrl(&self) -> &Reg<OSC_CAL_CTRL_SPEC>

0x53 - RWA, oscillator frequency calibration control, SAM

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pub const fn tkey_count(&self) -> &Reg<TKEY_COUNT_SPEC>

0x54 - RW, Touchkey charge and discharge count

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pub const fn tkey_convert(&self) -> &Reg<TKEY_CONVERT_SPEC>

0x56 - RW, Touchkey convert start control

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pub const fn tkey_cfg(&self) -> &Reg<TKEY_CFG_SPEC>

0x57 - RW, Touchkey configure

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pub const fn adc_channel(&self) -> &Reg<ADC_CHANNEL_SPEC>

0x58 - RW, ADC input channel selection

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pub const fn adc_cfg(&self) -> &Reg<ADC_CFG_SPEC>

0x59 - RW, ADC configure

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pub const fn adc_convert(&self) -> &Reg<ADC_CONVERT_SPEC>

0x5a - RW, ADC convert control

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pub const fn tem_sensor(&self) -> &Reg<TEM_SENSOR_SPEC>

0x5b - RW, temperature sensor control

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pub const fn adc_data(&self) -> &Reg<ADC_DATA_SPEC>

0x5c - RO, ADC data

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pub const fn adc_int_flag(&self) -> &Reg<ADC_INT_FLAG_SPEC>

0x5e - RO, ADC interrupt flag register

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pub const fn adc_dma_ctrl(&self) -> &Reg<ADC_DMA_CTRL_SPEC>

0x60 - RO, ADC DMA control and status register

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pub const fn adc_ctrl_dma(&self) -> &Reg<ADC_CTRL_DMA_SPEC>

0x61 - RW, ADC DMA control

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pub const fn adc_dma_if(&self) -> &Reg<ADC_DMA_IF_SPEC>

0x62 - RO, ADC interrupt flag

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pub const fn adc_auto_cycle(&self) -> &Reg<ADC_AUTO_CYCLE_SPEC>

0x63 - RO, ADC interrupt flag

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pub const fn adc_dma_now(&self) -> &Reg<ADC_DMA_NOW_SPEC>

0x64 - RO, ADC DMA current address

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pub const fn adc_dma_beg(&self) -> &Reg<ADC_DMA_BEG_SPEC>

0x68 - RW, ADC DMA begin address

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pub const fn adc_dma_end(&self) -> &Reg<ADC_DMA_END_SPEC>

0x6c - RW, ADC DMA end address

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pub const fn pa_int_en(&self) -> &Reg<PA_INT_EN_SPEC>

0x90 - RW, GPIO PA interrupt enable

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pub const fn pb_int_en(&self) -> &Reg<PB_INT_EN_SPEC>

0x92 - RW, GPIO PB interrupt enable

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pub const fn pa_int_mode(&self) -> &Reg<PA_INT_MODE_SPEC>

0x94 - RW, GPIO PA interrupt mode: 0=level action, 1=edge action

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pub const fn pb_int_mode(&self) -> &Reg<PB_INT_MODE_SPEC>

0x96 - RW, GPIO PB interrupt mode: 0=level action, 1=edge action;RW, status for parallel slave read

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pub const fn pa_int_if(&self) -> &Reg<PA_INT_IF_SPEC>

0x9c - RW1, GPIO PA interrupt flag

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pub const fn pb_int_if(&self) -> &Reg<PB_INT_IF_SPEC>

0x9e - RW1, GPIO PB interrupt flag

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pub const fn pa_dir(&self) -> &Reg<PA_DIR_SPEC>

0xa0 - RW, GPIO PA I/O direction: 0=in, 1=out

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pub const fn pa_pin(&self) -> &Reg<PA_PIN_SPEC>

0xa4 - RO, GPIO PA input

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pub const fn pa_out(&self) -> &Reg<PA_OUT_SPEC>

0xa8 - RW, GPIO PA output

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pub const fn pa_clr(&self) -> &Reg<PA_CLR_SPEC>

0xac - WZ, GPIO PA clear output: 0=keep, 1=clear

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pub const fn pa_pu(&self) -> &Reg<PA_PU_SPEC>

0xb0 - RW, GPIO PA pullup resistance enable

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pub const fn pa_pd_drv(&self) -> &Reg<PA_PD_DRV_SPEC>

0xb4 - RW, PA pulldown for input or PA driving capability for output

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pub const fn pb_dir(&self) -> &Reg<PB_DIR_SPEC>

0xc0 - RW, GPIO PB I/O direction: 0=in, 1=out

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pub const fn pb_pin(&self) -> &Reg<PB_PIN_SPEC>

0xc4 - RO, GPIO PB input

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pub const fn pb_out(&self) -> &Reg<PB_OUT_SPEC>

0xc8 - RW, GPIO PB output;RW, data for parallel slave read

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pub const fn pb_clr(&self) -> &Reg<PB_CLR_SPEC>

0xcc - WZ, GPIO PB clear output: 0=keep, 1=clear

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pub const fn pb_pu(&self) -> &Reg<PB_PU_SPEC>

0xd0 - RW, GPIO PB pullup resistance enable

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pub const fn pb_pd_drv(&self) -> &Reg<PB_PD_DRV_SPEC>

0xd4 - RW, PB pulldown for input or PB driving capability for output

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pub const fn flash_cfg(&self) -> &Reg<FLASH_CFG_SPEC>

0x807 - Flash configuration

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