Struct ch569_pac::sys::RegisterBlock
source · [−]#[repr(C)]pub struct RegisterBlock {Show 38 fields
pub r8_safe_access_sig: R8_SAFE_ACCESS_SIG,
pub r8_chip_id: R8_CHIP_ID,
pub r8_safe_access_id: R8_SAFE_ACCESS_ID,
pub r8_wdog_count: R8_WDOG_COUNT,
pub r8_glob_rom_cfg: R8_GLOB_ROM_CFG,
pub r8_rst_boot_stat: R8_RST_BOOT_STAT,
pub r8_rst_wdog_ctrl: R8_RST_WDOG_CTRL,
pub r8_glob_reset_keep: R8_GLOB_RESET_KEEP,
pub r8_clk_pll_div: R8_CLK_PLL_DIV,
pub r8_clk_cfg_ctrl: R8_CLK_CFG_CTRL,
pub r8_clk_mod_aux: R8_CLK_MOD_AUX,
pub r8_slp_clk_off0: R8_SLP_CLK_OFF0,
pub r8_slp_clk_off1: R8_SLP_CLK_OFF1,
pub r8_slp_wake_ctrl: R8_SLP_WAKE_CTRL,
pub r8_slp_power_ctrl: R8_SLP_POWER_CTRL,
pub r8_pin_alternate: R8_PIN_ALTERNATE,
pub r8_gpio_int_flag: R8_GPIO_INT_FLAG,
pub r8_gpio_int_enable: R8_GPIO_INT_ENABLE,
pub r8_gpio_int_mode: R8_GPIO_INT_MODE,
pub r8_gpio_int_polar: R8_GPIO_INT_POLAR,
pub r16_serd_ana_cfg1: R16_SERD_ANA_CFG1,
pub r32_serd_ana_cfg2: R32_SERD_ANA_CFG2,
pub r32_pa_dir: R32_PA_DIR,
pub r32_pa_pin: R32_PA_PIN,
pub r32_pa_out: R32_PA_OUT,
pub r32_pa_clr: R32_PA_CLR,
pub r32_pa_pu: R32_PA_PU,
pub r32_pa_pd: R32_PA_PD,
pub r32_pa_drv: R32_PA_DRV,
pub r32_pa_smt: R32_PA_SMT,
pub r32_pb_dir: R32_PB_DIR,
pub r32_pb_pin: R32_PB_PIN,
pub r32_pb_out: R32_PB_OUT,
pub r32_pb_clr: R32_PB_CLR,
pub r32_pb_pu: R32_PB_PU,
pub r32_pb_pd: R32_PB_PD,
pub r32_pb_drv: R32_PB_DRV,
pub r32_pb_smt: R32_PB_SMT,
/* private fields */
}Expand description
Register block
Fields
r8_safe_access_sig: R8_SAFE_ACCESS_SIG0x00 - safe accessing sign register
r8_chip_id: R8_CHIP_ID0x01 - chip ID register
r8_safe_access_id: R8_SAFE_ACCESS_ID0x02 - safe accessing ID register
r8_wdog_count: R8_WDOG_COUNT0x03 - watch-dog count register
r8_glob_rom_cfg: R8_GLOB_ROM_CFG0x04 - flash ROM configuration register
r8_rst_boot_stat: R8_RST_BOOT_STAT0x05 - reset status and boot/debug status
r8_rst_wdog_ctrl: R8_RST_WDOG_CTRL0x06 - reset and watch-dog control
r8_glob_reset_keep: R8_GLOB_RESET_KEEP0x07 - value keeper during global reset
r8_clk_pll_div: R8_CLK_PLL_DIV0x08 - output clock divider from PLL
r8_clk_cfg_ctrl: R8_CLK_CFG_CTRL0x0a - clock control
r8_clk_mod_aux: R8_CLK_MOD_AUX0x0b - clock mode aux register
r8_slp_clk_off0: R8_SLP_CLK_OFF00x0c - sleep clock off control byte 0
r8_slp_clk_off1: R8_SLP_CLK_OFF10x0d - sleep clock off control byte 1
r8_slp_wake_ctrl: R8_SLP_WAKE_CTRL0x0e - wake control
r8_slp_power_ctrl: R8_SLP_POWER_CTRL0x0f - power control
r8_pin_alternate: R8_PIN_ALTERNATE0x12 - alternate pin control
r8_gpio_int_flag: R8_GPIO_INT_FLAG0x1c - GPIO interrupt control
r8_gpio_int_enable: R8_GPIO_INT_ENABLE0x1d - GPIO interrupt enable
r8_gpio_int_mode: R8_GPIO_INT_MODE0x1e - GPIO interrupt mode
r8_gpio_int_polar: R8_GPIO_INT_POLAR0x1f - GPIO interrupt polarity
r16_serd_ana_cfg1: R16_SERD_ANA_CFG10x20 - Serdes Analog parameter configuration1
r32_serd_ana_cfg2: R32_SERD_ANA_CFG20x24 - Serdes Analog parameter configuration2
r32_pa_dir: R32_PA_DIR0x40 - GPIO PA I/O direction
r32_pa_pin: R32_PA_PIN0x44 - GPIO PA input
r32_pa_out: R32_PA_OUT0x48 - GPIO PA output
r32_pa_clr: R32_PA_CLR0x4c - GPIO PA clear output
r32_pa_pu: R32_PA_PU0x50 - GPIO PA pullup resistance enable
r32_pa_pd: R32_PA_PD0x54 - GPIO PA output open-drain and input pulldown resistance enable
r32_pa_drv: R32_PA_DRV0x58 - GPIO PA driving capability
r32_pa_smt: R32_PA_SMT0x5c - GPIO PA output slew rate and input schmitt trigger
r32_pb_dir: R32_PB_DIR0x60 - GPIO PB I/O direction
r32_pb_pin: R32_PB_PIN0x64 - GPIO PB input
r32_pb_out: R32_PB_OUT0x68 - GPIO PB output
r32_pb_clr: R32_PB_CLR0x6c - GPIO PB clear output
r32_pb_pu: R32_PB_PU0x70 - GPIO PB pullup resistance enable
r32_pb_pd: R32_PB_PD0x74 - GPIO PB output open-drain and input pulldown resistance enable
r32_pb_drv: R32_PB_DRV0x78 - GPIO PB driving capability
r32_pb_smt: R32_PB_SMT0x7c - GPIO PB output slew rate and input schmitt trigger