Struct ch569_pac::emmc::RegisterBlock

source · [−]
#[repr(C)]
pub struct RegisterBlock {
Show 15 fields
    pub r32_emmc_argument: R32_EMMC_ARGUMENT,
    pub r16_emmc_cmd_set: R16_EMMC_CMD_SET,
    pub r32_emmc_response0: R32_EMMC_RESPONSE0,
    pub r32_emmc_response1: R32_EMMC_RESPONSE1,
    pub r32_emmc_response2: R32_EMMC_RESPONSE2,
    pub r8_emmc_control: R8_EMMC_CONTROL,
    pub r8_emmc_timeout: R8_EMMC_TIMEOUT,
    pub r32_emmc_status: R32_EMMC_STATUS,
    pub r16_emmc_int_fg: R16_EMMC_INT_FG,
    pub r16_emmc_int_en: R16_EMMC_INT_EN,
    pub r32_emmc_dma_beg1: R32_EMMC_DMA_BEG1,
    pub r32_emmc_block_cfg: R32_EMMC_BLOCK_CFG,
    pub r32_emmc_tran_mode: R32_EMMC_TRAN_MODE,
    pub r16_emmc_clk_div: R16_EMMC_CLK_DIV,
    pub r32_emmc_dma_beg2: R32_EMMC_DMA_BEG2,
    /* private fields */

}
Expand description

Register block

Fields

r32_emmc_argument: R32_EMMC_ARGUMENT

0x00 - SD 32bits command argument register

r16_emmc_cmd_set: R16_EMMC_CMD_SET

0x04 - SD 16bits cmd setting register

r32_emmc_response0: R32_EMMC_RESPONSE0

0x08 - SD 128bits response register, [31:0] 32bits

r32_emmc_response1: R32_EMMC_RESPONSE1

0x0c - SD 128bits response register, [63:32] 32bits

r32_emmc_response2: R32_EMMC_RESPONSE2

0x10 - SD 128bits response register, [95:64] 32bits

r8_emmc_control: R8_EMMC_CONTROL

0x18 - SD 8bits control register

r8_emmc_timeout: R8_EMMC_TIMEOUT

0x1c - SD 8bits data timeout value

r32_emmc_status: R32_EMMC_STATUS

0x20 - SD status

r16_emmc_int_fg: R16_EMMC_INT_FG

0x24 - SD 16bits interrupt flag register

r16_emmc_int_en: R16_EMMC_INT_EN

0x28 - SD 16bits interrupt enable register

r32_emmc_dma_beg1: R32_EMMC_DMA_BEG1

0x2c - SD 16bits DMA start address register when to operate

r32_emmc_block_cfg: R32_EMMC_BLOCK_CFG

0x30 - SD 32bits data counter, [15:0] number of blocks this time will tran/recv, [27:16] block sise(byte number) of every block in this time tran/recv

r32_emmc_tran_mode: R32_EMMC_TRAN_MODE

0x34 - SD TRANSFER MODE register

r16_emmc_clk_div: R16_EMMC_CLK_DIV

0x38 - SD clock divider register

r32_emmc_dma_beg2: R32_EMMC_DMA_BEG2

0x3c - SD 16bits DMA start address register when to operate

Implementations

0x14 - Multiplexing register of the EMMC_RESPONSE3,[127:96] 32bits

0x14 - SD 128bits response register, [127:96] 32bits

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