Struct ch32v3::ch32v30x::dac::RegisterBlock

source · 
#[repr(C)]
pub struct RegisterBlock {
Show 13 fields
    pub ctlr: CTLR,
    pub swtr: SWTR,
    pub r12bdhr1: R12BDHR1,
    pub l12bdhr1: L12BDHR1,
    pub r8bdhr1: R8BDHR1,
    pub r12bdhr2: R12BDHR2,
    pub l12bdhr2: L12BDHR2,
    pub r8bdhr2: R8BDHR2,
    pub rd12bdhr: RD12BDHR,
    pub ld12bdhr: LD12BDHR,
    pub rd8bdhr: RD8BDHR,
    pub dor1: DOR1,
    pub dor2: DOR2,

}
Expand description

Register block

Fields§

§ctlr: CTLR

0x00 - Control register (DAC_CR)

§swtr: SWTR

0x04 - DAC software trigger register (DAC_SWTRIGR)

§r12bdhr1: R12BDHR1

0x08 - DAC channel1 12-bit right-aligned data holding register(DAC_DHR12R1)

§l12bdhr1: L12BDHR1

0x0c - DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1)

§r8bdhr1: R8BDHR1

0x10 - DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1)

§r12bdhr2: R12BDHR2

0x14 - DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2)

§l12bdhr2: L12BDHR2

0x18 - DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2)

§r8bdhr2: R8BDHR2

0x1c - DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2)

§rd12bdhr: RD12BDHR

0x20 - Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD), Bits 31:28 Reserved, Bits 15:12 Reserved

§ld12bdhr: LD12BDHR

0x24 - DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD), Bits 19:16 Reserved, Bits 3:0 Reserved

§rd8bdhr: RD8BDHR

0x28 - DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD), Bits 31:16 Reserved

§dor1: DOR1

0x2c - DAC channel1 data output register (DAC_DOR1)

§dor2: DOR2

0x30 - DAC channel2 data output register (DAC_DOR2)

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