Expand description
Digital to analog converter
Modules
Control register (DAC_CR)
DAC channel1 data output register (DAC_DOR1)
DAC channel2 data output register (DAC_DOR2)
DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1)
DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2)
DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD), Bits 19:16 Reserved, Bits 3:0 Reserved
DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1)
DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2)
DAC channel1 12-bit right-aligned data holding register(DAC_DHR12R1)
DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2)
DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD), Bits 31:16 Reserved
Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD), Bits 31:28 Reserved, Bits 15:12 Reserved
DAC software trigger register (DAC_SWTRIGR)
Structs
Register block
Type Definitions
CTLR (rw) register accessor: an alias for
Reg<CTLR_SPEC>DOR1 (r) register accessor: an alias for
Reg<DOR1_SPEC>DOR2 (r) register accessor: an alias for
Reg<DOR2_SPEC>L12BDHR1 (rw) register accessor: an alias for
Reg<L12BDHR1_SPEC>L12BDHR2 (rw) register accessor: an alias for
Reg<L12BDHR2_SPEC>LD12BDHR (rw) register accessor: an alias for
Reg<LD12BDHR_SPEC>R8BDHR1 (rw) register accessor: an alias for
Reg<R8BDHR1_SPEC>R8BDHR2 (rw) register accessor: an alias for
Reg<R8BDHR2_SPEC>R12BDHR1 (rw) register accessor: an alias for
Reg<R12BDHR1_SPEC>R12BDHR2 (rw) register accessor: an alias for
Reg<R12BDHR2_SPEC>RD8BDHR (rw) register accessor: an alias for
Reg<RD8BDHR_SPEC>RD12BDHR (rw) register accessor: an alias for
Reg<RD12BDHR_SPEC>SWTR (w) register accessor: an alias for
Reg<SWTR_SPEC>