Struct Ch32Target 

pub struct Ch32Target<T: DtmAccess> { /* private fields */ }

en: gdbstub target that OWNS its transport T (owning, not borrowing, keeps the type free of a lifetime so it fits BlockingEventLoop::Target). Recover the transport with Ch32Target::into_inner to detach cleanly afterwards. ja: transport T を所有する gdbstub target(所有にすることでライフタイムが付かず BlockingEventLoop::Target に収まる)。後始末は Ch32Target::into_inner で回収する。

Implementations

impl<T: DtmAccess> Ch32Target<T>

pub fn new( dtm: T, flash: Option<(u32, FlashProgMode)>, ) -> Result<Self, DmiError>

en: Wrap a transport and halt the core so GDB attaches to a stopped target. flash is the FLASH-controller profile for this family (fast-page size + program mode, from ch32rv_flash::flash_controller_profile), or None to refuse flash software breakpoints. ja: transport を包んで halt。flash はこの family の FLASH-controller profile(fast page サイズ + program mode。None なら flash SW breakpoint を拒否)。

pub fn hw_trigger_count(&self) -> u32

Number of hardware trigger slots the core exposes (0 on V003/V2A).

pub fn is_halted(&mut self) -> Result<bool, DmiError>

True if the core is halted right now.

pub fn halt(&mut self) -> Result<(), DmiError>

Request a halt (used for Ctrl-C).

pub fn into_inner(self) -> T

Recover the owned transport (to detach after the session).

pub fn flash_breakpoints_supported(&self) -> bool

True if this core supports flash software breakpoints (verified FLASH-controller profile).

pub fn restore_flash_breakpoints(&mut self)

en: Restore every managed flash page to its pristine content (removing any ebreak still patched in). Call before detaching so an interrupted session never leaves a breakpoint baked into flash. Best-effort. ja: 管理中の flash page をすべて pristine に戻す(残った ebreak を消す)。detach 前に 呼び、途中終了しても flash に breakpoint が焼き付かないようにする。best-effort。

Trait Implementations

impl<T: DtmAccess> Breakpoints for Ch32Target<T>

fn support_sw_breakpoint(&mut self) -> Option<SwBreakpointOps<'_, Self>>

Support for setting / removing software breakpoints.

fn support_hw_breakpoint(&mut self) -> Option<HwBreakpointOps<'_, Self>>

Support for setting / removing hardware breakpoints.

fn support_hw_watchpoint( &mut self, ) -> Option<&mut dyn HwWatchpoint<Arch = Self::Arch, Error = Self::Error>>

Support for setting / removing hardware watchpoints.

impl<T: DtmAccess> HwBreakpoint for Ch32Target<T>

fn add_hw_breakpoint( &mut self, addr: u32, _kind: usize, ) -> TargetResult<bool, Self>

Add a new hardware breakpoint.

fn remove_hw_breakpoint( &mut self, addr: u32, _kind: usize, ) -> TargetResult<bool, Self>

Remove an existing hardware breakpoint.

impl<T: DtmAccess> SingleThreadBase for Ch32Target<T>

fn read_registers(&mut self, regs: &mut Rv32CoreRegs) -> TargetResult<(), Self>

Read the target’s registers.

fn write_registers(&mut self, regs: &Rv32CoreRegs) -> TargetResult<(), Self>

Write the target’s registers.

fn read_addrs( &mut self, start: u32, data: &mut [u8], ) -> TargetResult<usize, Self>

Read bytes from the specified address range and return the number of bytes that were read.

fn write_addrs(&mut self, start: u32, data: &[u8]) -> TargetResult<(), Self>

Write bytes to the specified address range.

fn support_resume(&mut self) -> Option<SingleThreadResumeOps<'_, Self>>

Support for resuming the target (e.g: via continue or step)

fn support_single_register_access( &mut self, ) -> Option<&mut dyn SingleRegisterAccess<(), Arch = Self::Arch, Error = Self::Error>>

Support for single-register access. See SingleRegisterAccess for more details.

impl<T: DtmAccess> SingleThreadResume for Ch32Target<T>

fn resume(&mut self, _signal: Option<Signal>) -> Result<(), Self::Error>

Resume execution on the target.

fn support_single_step(&mut self) -> Option<SingleThreadSingleStepOps<'_, Self>>

Support for optimized single stepping.

fn support_range_step( &mut self, ) -> Option<&mut dyn SingleThreadRangeStepping<Arch = Self::Arch, Error = Self::Error>>

Support for optimized range stepping.

fn support_reverse_step( &mut self, ) -> Option<&mut dyn ReverseStep<(), Arch = Self::Arch, Error = Self::Error>>

Support for reverse stepping a target.

fn support_reverse_cont( &mut self, ) -> Option<&mut dyn ReverseCont<(), Arch = Self::Arch, Error = Self::Error>>

Support for reverse continuing a target.

impl<T: DtmAccess> SingleThreadSingleStep for Ch32Target<T>

fn step(&mut self, _signal: Option<Signal>) -> Result<(), Self::Error>

Single step the target.

impl<T: DtmAccess> SwBreakpoint for Ch32Target<T>

fn add_sw_breakpoint( &mut self, addr: u32, kind: usize, ) -> TargetResult<bool, Self>

en: Set a breakpoint GDB asked for as “software” (Z0). We first try a RAM memory-patch (ebreak); if the write does not stick - the classic case being a flash address, where the DM sw silently no-ops - we transparently fall back to a hardware execute trigger when the core has a free slot. That makes plain break work on flash-resident code for V4-class cores (which expose triggers) without the risk of rewriting flash. Cores with no trigger module (V003/V103) can still set RAM breakpoints; a flash breakpoint there returns unsupported (a flash-patch approach is a follow-up). ja: GDB が Z0(software)で要求した breakpoint。まず RAM の memory patch(ebreak)を 試し、書き込みが定着しない(典型は flash 番地。DM の sw が無反応)場合は、空き HW slot が あれば HW execute trigger へ透過的にフォールバックし(flash 書き換えの危険なし)、trigger が 無ければ page 書き換えの flash software breakpoint へフォールバックする。これで trigger を 持たない core(V203 等)でも flash 上のコードに通常 break が効く(flash 書き換えの摩耗あり)。 順序は RAM → HW trigger → flash-patch。どれも不可なら未対応を返す。

fn remove_sw_breakpoint( &mut self, addr: u32, _kind: usize, ) -> TargetResult<bool, Self>

Remove an existing software breakpoint.

impl<T: DtmAccess> Target for Ch32Target<T>

type Arch = Rv32

The target’s architecture.

type Error = DmiError

A target-specific fatal error.

fn base_ops(&mut self) -> BaseOps<'_, Self::Arch, Self::Error>

Base operations such as reading/writing from memory/registers, stopping/resuming the target, etc….

fn support_breakpoints(&mut self) -> Option<BreakpointsOps<'_, Self>>

Support for setting / removing breakpoints.

fn guard_rail_implicit_sw_breakpoints(&self) -> bool

If the target supports resumption, but hasn’t implemented explicit support for software breakpoints (via SwBreakpoints), notify the user that the GDB client may set “implicit” software breakpoints by rewriting the target’s instruction stream.

fn use_no_ack_mode(&self) -> bool

Enable/disable support for activating “no ack mode”.

fn use_x_upcase_packet(&self) -> bool

Enable/disable using the more efficient X packet to write to target memory (as opposed to the basic M packet).

fn use_resume_stub(&self) -> bool

Whether gdbstub should provide a “stub” resume implementation on targets without support for resumption.

fn use_rle(&self) -> bool

Enable/Disable the use of run-length encoding on outgoing packets.

fn use_target_description_xml(&self) -> bool

Whether to send a target description XML to the client.

fn use_lldb_register_info(&self) -> bool

(LLDB extension) Whether to send register information to the client.

fn use_fork_stop_reason(&self) -> bool

Enable support for BaseStopReason::Fork.

fn use_vfork_stop_reason(&self) -> bool

Enable support for BaseStopReason::VFork.

fn use_vforkdone_stop_reason(&self) -> bool

Enable support for BaseStopReason::VForkDone.

fn support_monitor_cmd( &mut self, ) -> Option<&mut dyn MonitorCmd<Arch = Self::Arch, Error = Self::Error>>

Support for handling custom GDB monitor commands.

fn support_extended_mode( &mut self, ) -> Option<&mut dyn ExtendedMode<Arch = Self::Arch, Error = Self::Error>>

Support for Extended Mode operations.

fn support_section_offsets( &mut self, ) -> Option<&mut dyn SectionOffsets<Arch = Self::Arch, Error = Self::Error>>

Support for handling requests to get the target’s current section (or segment) offsets.

fn support_tracepoints( &mut self, ) -> Option<&mut dyn Tracepoints<Arch = Self::Arch, Error = Self::Error>>

Support for setting / removing tracepoints.

fn support_target_description_xml_override( &mut self, ) -> Option<&mut dyn TargetDescriptionXmlOverride<Arch = Self::Arch, Error = Self::Error>>

Support for overriding the target description XML specified by Target::Arch.

fn support_lldb_register_info_override( &mut self, ) -> Option<&mut dyn LldbRegisterInfoOverride<Arch = Self::Arch, Error = Self::Error>>

(LLDB extension) Support for overriding the register info specified by Target::Arch.

fn support_memory_map( &mut self, ) -> Option<&mut dyn MemoryMap<Arch = Self::Arch, Error = Self::Error>>

Support for reading the target’s memory map.

fn support_flash_operations( &mut self, ) -> Option<&mut dyn Flash<Arch = Self::Arch, Error = Self::Error>>

Support for flash memory operations.

fn support_catch_syscalls( &mut self, ) -> Option<&mut dyn CatchSyscalls<Arch = Self::Arch, Error = Self::Error>>

Support for setting / removing syscall catchpoints.

fn support_host_io( &mut self, ) -> Option<&mut dyn HostIo<Arch = Self::Arch, Error = Self::Error>>

Support for Host I/O operations.

fn support_exec_file( &mut self, ) -> Option<&mut dyn ExecFile<Arch = Self::Arch, Error = Self::Error>>

Support for reading the current exec-file.

fn support_auxv( &mut self, ) -> Option<&mut dyn Auxv<Arch = Self::Arch, Error = Self::Error>>

Support for reading the target’s Auxillary Vector.

fn support_libraries_svr4( &mut self, ) -> Option<&mut dyn LibrariesSvr4<Arch = Self::Arch, Error = Self::Error>>

Support for reading a list of libraries for SVR4 (System-V/Unix) platforms.

fn support_libraries( &mut self, ) -> Option<&mut dyn Libraries<Arch = Self::Arch, Error = Self::Error>>

Support for reading a list of libraries (Windows/generic format).

fn support_host_info( &mut self, ) -> Option<&mut dyn HostInfo<Arch = Self::Arch, Error = Self::Error>>

(LLDB extension) Support for reporting host information.

fn support_process_info( &mut self, ) -> Option<&mut dyn ProcessInfo<Arch = Self::Arch, Error = Self::Error>>

(LLDB extension) Support for reporting process information.

fn support_wasm( &mut self, ) -> Option<&mut dyn Wasm<Arch = Self::Arch, Error = Self::Error>>

(LLDB extension) Support for WebAssembly (Wasm)-specific commands.