Skip to main content Crate celox Copy item path Source pub use crate::testbench::AssertionResult ;pub use crate::testbench::TestResult ;pub use crate::testbench::TestResultDetailed ;pub use celox_frontend_sdk as frontend_sdk;pub use backend::wasm_codegen ;native_backend Re-exports for the custom native backend (for testing/integration). testbench Native testbench execution for Veryl #[test] modules. veryl_test AppendedNativeImage Result of finding and decoding an image appended to another byte sequence. BigUint A big unsigned integer type. Checkpoint Saved state of a SimulatorSimulator::checkpoint CompilationTrace CompilationTraceResult CraneliftDiagnostics Fine-grained Cranelift backend options beyond the optimization level. CraneliftOptions Fine-grained Cranelift backend options beyond the optimization level. DesignReflection DiagnosticsOptions Complete explicit diagnostics configuration for a simulator build. DpiSymbols Where the C functions of DPI-C imports are found. ElaboratedDesign Backend-neutral semantic design data after hierarchy flattening. EventRef Opaque handle to a compiled event (clock / async-reset) function.
Holds the JIT-compiled function pointer directly — no indirection.
Obtained once via JitBackend::resolve_eventJitBackend::eval_apply_ff_at EventTopology Source-independent event-domain topology after elaboration. FrontendArtifact Fully elaborated frontend result. The first SDK version intentionally
models one flattened module; hierarchical netlists can be flattened by the
producing frontend without affecting runtime signal names. FrontendLookup Source-language-independent lookup retained for diagnostics and public paths.
Parser-native IDs are projected into SourceVarId IOContext InjectedCall One synchronous call into an injected component implementation. InjectedComponents Component definitions injected by an embedding API for one simulator. InjectedNamedValue InjectedPort InjectedResult Effects returned by an injected callback. Outputs are staged using the
same component/NBA path as compiled native and Wasm components. InstanceHierarchy Hierarchical instance tree with resolved signals. InstancePath InterpBackend A SimBackend JitBackend LaidOutProgram Optimized SIR whose physical state layout has been finalized. LayoutRequirements Semantic constraints produced by optimization and consumed when physical
state layout is finalized. NamedEvent A named event with its resolved ID and event reference. NamedSignal A named signal with its resolved memory reference and metadata. NativeBackend NativeCodeEntry One callable function in a packed native code image. NativeCompilation A code-generated native program that has not been loaded into
executable memory or initialized as a simulator yet. NativeDiagnostics NativeDumpOptions NativeEventRef Compiled event handle for native backend.
Holds the function pointer directly — no indirection at call time. NativeProfileBlock One native JIT block selected by an external profile. NativeProgramImage Pointer-free native compiler artifact which can be attached to the
precompiled Celox runtime. NativeProgramInstance One independently mutable instance of a precompiled native program. OptimizeOptions Controls which SIR optimization passes are enabled. OptimizedSir A pre-layout compiler artifact whose SIR optimization pipeline has
completed successfully. ReflectionScope ReflectionScopeId ReflectionSignal ReflectionSignalId ResolvedAccess One memory access with its dynamic offset components resolved. RuntimeDesign Canonical runtime design model after frontend scheduling. RuntimeDiagnostics Diagnostics owned by the simulator facade and runtime. RuntimeEventDrain RuntimeFormatContext RuntimeInstance One elaborated runtime instance with direct state-address indices. RuntimeProgram Source-independent metadata retained while a compiled design is executing. RuntimeSchema Source-independent runtime diagnostics and observable event descriptions. RuntimeVariable Source-facing metadata for one flattened runtime state object. ScheduleRecord Scheduling state of a time-based simulation. ScheduledEvent A pending event of a time-based simulation, identified by name. SharedJitCode Immutable compilation result that can be shared across simulator instances. SharedNativeCode Shared compiled code for the native backend.
Can be cloned (via Arc) to create multiple simulator instances
that share the same compiled machine code. SignalRef Simulation A timed simulation wrapper around the core logic engine. SimulationCheckpoint Saved state of a SimulationSimulation::checkpoint Simulator The core logic evaluation engine. SimulatorBuilder A fluent builder for configuring and initializing a SimulatorSimulation SimulatorError A simulator error that may also carry accumulated compilation warnings. SimulatorOptions SirDiagnostics Diagnostics and additional verification for the SIR optimizer. SourceLocation SourceVarId Frontend-local identity of a source variable within one module. StateFile Contents of a state file. StateImage The design state of a memory image: the stable region after the state
header, tagged with the layout fingerprint it belongs to. StateMismatch Differences between a state file and the design it is loaded into. StateObject The saved value of one state object. StateSchema The state objects of a built design, with the paths and roles that state
files use for them. StoreSnapshot Pre-store snapshot of a stored range, used to detect whether a store
actually changed any covered bit before enabling comb capture observers. TieredBackend A SimBackend TieredEventRef Stable event handle for the tiered backend. TieredExecutionStats Deterministic execution measurements for one tiered simulator. TieredExecutionTiming Opt-in wall-clock measurement for a tiered execution interval. TraceOptions UnoptimizedSir Lowered SIR whose backend-independent optimization pipeline has not run. VariableInfo VcdSignalDesc Describes a signal for VCD recording. VcdStatistics VcdWriter WasmBackend The runtime WASM backend. AddrLookupError Error returned when a path-based variable or event lookup fails. CheckpointError Reasons a checkpoint cannot be taken or restored. ClockType CodegenError Structured failure while preparing executable simulator code. CompilationWarning A non-fatal source diagnostic retained by a successfully built simulator. CraneliftOptLevel Cranelift backend optimization level. DeadStorePolicy Controls which combinational stores dead store elimination preserves. DomainKind DpiError A failure to link the C functions of DPI-C imports. DumpError Why Simulator::try_dump FrontendArtifactError FrontendDiagnostic Celox-specific source diagnostics produced after Veryl analysis but before
source identities are discarded by lowering. InjectedHook The lifecycle operation requested from an injected component. InjectedValue A value crossing the boundary of an in-process component callback. InterpError Why an interpreted execution unit stopped abnormally. LoweringPhase The compilation phase where an unsupported feature was encountered. MemoryLayoutMode NativeImageArchitecture Native ISA required by an appended program image. NativeImageContainerError Failure while encoding or discovering a native image container. NativeProgramLoadError Failure while discovering or attaching a compiler-produced native image. NativeSignalIdentity Source-independent identity shared by reflected handles for one signal. OptLevel Optimization level presets, analogous to GCC’s -O flags. ParallelPartition How the compiler decides whether a phase gets a lane-partitioned kernel. ParserError PortTypeKind RegallocAlgorithm Register allocator algorithm for the Cranelift backend. ResetType RuntimeErrorCode RuntimeEvent HDL output is an arbitrary sequence of 8-bit character codes.
Message payloads are byte-exact; decode explicitly if text is required. SchedulerError SignalDirection SimulatorErrorKind The specific kind of simulator error. SirPass Individual SIR optimization passes that can be toggled. StateDifference A state object whose saved values differ between two files. StateError Why a state file could not be saved or loaded. StateFileError A state file that could not be read. StateRole How a state object gets its value. TierPromotion Controls when the tiered backend adopts background-compiled code. TieredExecutionTier Active execution tier reported by TieredExecutionStats TieredPromotionStatus State of background compilation and promotion. UnitExit Outcome of one interpreted unit invocation. VariableKind Source-language-independent role of a frontend variable. MAX_SIMULATION_THREADS Largest worker-thread count accepted by SimulatorBuilder::threads. STATE_HEADER_SIZE EventHandle Marker trait for backend-specific event handles. InjectedComponentHandler Synchronous component implementation supplied by an embedding runtime. InterpMachine Storage and side-effect interface driven by the interpreter. SimBackend Abstraction over different simulation backends (JIT, WASM, etc.). compile_frontend_to_sir Compile an elaborated external-frontend artifact to optimized SIR. compile_to_sir Compile Veryl source code to the SIR (Simulation IR) representation. execute_unit Execute one execution unit on the interpreter. format_state_value Format little-endian bytes as a hexadecimal number of width bits, with
X/Z bits from mask shown as x. get_byte_size register_static_component Registers an in-process Veryl component implementation. register_static_component_manifest Registers the manifest paired with an in-process component implementation. render_diagnostic Render a miette::Diagnostic to a plain-text string (no ANSI colors). AbsoluteAddr Source-independent identity of one elaborated state object. DefaultBackend Default simulation backend: custom native when it matches the compilation
target, and Cranelift when a host-side cross-codegen feature is enabled. DefaultEventRef MemoryLayout RuntimeErrorInfo SirProgram SourceAddr