Crate celox_testbench 

Source-independent testbench bytecode contracts.

Frontends translate source-language operators into this vocabulary before execution. No Veryl AST, parser ID, simulator backend, or runtime handle is part of the bytecode representation.

Structs

BindError

CompiledExpr

A compiled expression: flat bytecode evaluated on a stack VM.

ComponentBinding

ComponentConnection

ComponentConnectionBinding

ComponentLibrary

DisplayFormatArg

ExecutableArgument

ExecutableTestbench

ExprBytecode

FieldSpec

The flags and field width between % and a conversion character.

SemanticArgument

SemanticSignal

SourceLocation

StateLocation

TestbenchComponent

TestbenchProgram

TestbenchSelection

TestbenchTarget

Enums

AssertMessage

ClockCount

ComponentParameterValue

ExprOpcode

LoopBound

TestbenchOperator

TestbenchStatement

Source-independent testbench control program.

TestbenchValue

Stack value: either a native u64 or a heap-allocated BigUint.

Constants

MAX_FIELD_WIDTH

Ceiling on a field width: the digits come from source text, and a wider field would only be an allocation the source sizes by typing. Veryl’s simulator caps its field widths the same way.

Functions

format_display_arg

Format an argument as bytes. Character conversions never decode UTF-8.

format_sized_display_arg

Formats arg with the sizing of IEEE 1800-2023 21.2.1.2. Without a field_width, hexadecimal, octal, and binary values take as many digits as the largest value of the argument’s width, with leading zeros, and decimal values as many characters, with leading spaces. With one, the value is padded to that width (0 displays it in the minimum width), and a wider value is never truncated.

format_sv_display_arg

IEEE display sizing with the - and leading 0 field flags supported by Icarus and Verilator. As in Icarus, decimal zero padding follows the sign; left justification takes precedence over zero padding.

format_veryl_display_arg

Formats arg as Veryl’s simulator does. Hexadecimal, octal, and binary values take a digit for each group of the argument’s bits, and decimal values their minimum width. With %0, radices drop their leading zeros. A field width then pads as pad_veryl_field does.

pad_veryl_field

Pads a converted value to its field width as Veryl’s simulator does: on the left with spaces, on the right with -, or with zeros behind the sign for a number with a leading 0. A longer value is never truncated.

Type Aliases

ExecutableAssertMessage

ExecutableClockCount

ExecutableComponentBinding

ExecutableLoopBound

ExecutableStatement

SemanticComponentBinding

SemanticStatement