1pub mod backend;
4mod error;
5mod event_buffer;
6pub mod parallel;
7mod reflection;
8pub mod scheduler;
9mod simulation;
10mod state_file;
11mod testbench;
12mod vcd;
13
14pub use error::{SimulatorErrorCode, comb_fatal_code, comb_fatal_site};
15pub use event_buffer::RuntimeEventBuffer;
16pub use reflection::{
17 DesignReflection, ReflectionScope, ReflectionScopeId, ReflectionSignal, ReflectionSignalId,
18 SignalDirection,
19};
20pub use simulation::{
21 EventInfo, ProcessRefs, ScheduleParts, SimulationExecutor, SimulationSnapshot, SimulationState,
22};
23pub use state_file::{
24 ScheduleRecord, ScheduledEvent, StateDifference, StateFile, StateFileError, StateObject,
25 StateRole, format_state_value,
26};
27pub use testbench::bind_testbench_program;
28pub use vcd::{VcdExternalSignalDesc, VcdSignalDesc, VcdStatistics, VcdWriter};
29
30pub type AbsoluteAddr = celox_design::StateAddr;
31pub type MemoryLayout = celox_state_layout::MemoryLayout<AbsoluteAddr>;
32
33#[derive(
34 Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash, serde::Serialize, serde::Deserialize,
35)]
36pub struct SignalArrayLayout {
37 pub element_width: usize,
38 pub element_count: usize,
39 pub element_stride: usize,
40 pub plane_size: usize,
41}
42
43#[derive(
44 Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash, serde::Serialize, serde::Deserialize,
45)]
46pub struct SignalRef {
47 pub offset: usize,
48 pub width: usize,
49 pub is_4state: bool,
50 pub array_layout: Option<SignalArrayLayout>,
51}