[−][src]Struct cc3220sf::adc::RegisterBlock
Register block
Fields
ctrl: CTRL
0x00 - ADC control register.
ch0_gain: CH0_GAIN
0x04 - Channel 0 gain setting
ch1_gain: CH1_GAIN
0x08 - Channel 1 gain setting
ch2_gain: CH2_GAIN
0x0c - Channel 2 gain setting
ch3_gain: CH3_GAIN
0x10 - Channel 3 gain setting
ch4_gain: CH4_GAIN
0x14 - Channel 4 gain setting
ch5_gain: CH5_GAIN
0x18 - Channel 5 gain setting
ch6_gain: CH6_GAIN
0x1c - Channel 6 gain setting
ch7_gain: CH7_GAIN
0x20 - Channel 7 gain setting
ch0_irq_en: CH0_IRQ_EN
0x24 - Channel 0 interrupt enable register
ch1_irq_en: CH1_IRQ_EN
0x28 - Channel 1 interrupt enable register
ch2_irq_en: CH2_IRQ_EN
0x2c - Channel 2 interrupt enable register
ch3_irq_en: CH3_IRQ_EN
0x30 - Channel 3 interrupt enable register
ch4_irq_en: CH4_IRQ_EN
0x34 - Channel 4 interrupt enable register
ch5_irq_en: CH5_IRQ_EN
0x38 - Channel 5 interrupt enable register
ch6_irq_en: CH6_IRQ_EN
0x3c - Channel 6 interrupt enable register
ch7_irq_en: CH7_IRQ_EN
0x40 - Channel 7 interrupt enable register
ch0_irq_status: CH0_IRQ_STATUS
0x44 - Channel 0 interrupt status register
ch1_irq_status: CH1_IRQ_STATUS
0x48 - Channel 1 interrupt status register
ch2_irq_status: CH2_IRQ_STATUS
0x4c - CH2_IRQ_STATUS
ch3_irq_status: CH3_IRQ_STATUS
0x50 - Channel 3 interrupt status register
ch4_irq_status: CH4_IRQ_STATUS
0x54 - Channel 4 interrupt status register
ch5_irq_status: CH5_IRQ_STATUS
0x58 - CH5_IRQ_STATUS
ch6_irq_status: CH6_IRQ_STATUS
0x5c - Channel 6 interrupt status register
ch7_irq_status: CH7_IRQ_STATUS
0x60 - Channel 7 interrupt status register
dma_mode_en: DMA_MODE_EN
0x64 - DMA mode enable register
timer_configuration: TIMER_CONFIGURATION
0x68 - ADC timer configuration register
timer_current_count: TIMER_CURRENT_COUNT
0x70 - ADC timer current count register
channel0fifodata: CHANNEL0FIFODATA
0x74 - CH0 FIFO DATA register
channel1fifodata: CHANNEL1FIFODATA
0x78 - CH1 FIFO DATA register
channel2fifodata: CHANNEL2FIFODATA
0x7c - CH2 FIFO DATA register
channel3fifodata: CHANNEL3FIFODATA
0x80 - CH3 FIFO DATA register
channel4fifodata: CHANNEL4FIFODATA
0x84 - CH4 FIFO DATA register
channel5fifodata: CHANNEL5FIFODATA
0x88 - CH5 FIFO DATA register
channel6fifodata: CHANNEL6FIFODATA
0x8c - CH6 FIFO DATA register
channel7fifodata: CHANNEL7FIFODATA
0x90 - CH7 FIFO DATA register
ch0_fifo_lvl: CH0_FIFO_LVL
0x94 - channel 0 FIFO Level register
ch1_fifo_lvl: CH1_FIFO_LVL
0x98 - Channel 1 interrupt status register
ch2_fifo_lvl: CH2_FIFO_LVL
0x9c - CH2_FIFO_LVL
ch3_fifo_lvl: CH3_FIFO_LVL
0xa0 - Channel 3 interrupt status register
ch4_fifo_lvl: CH4_FIFO_LVL
0xa4 - Channel 4 interrupt status register
ch5_fifo_lvl: CH5_FIFO_LVL
0xa8 - CH5_FIFO_LVL
ch6_fifo_lvl: CH6_FIFO_LVL
0xac - Channel 6 interrupt status register
ch7_fifo_lvl: CH7_FIFO_LVL
0xb0 - Channel 7 interrupt status register
ch_enable: CH_ENABLE
0xb8 - CH_ENABLE
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