Type Definition cc3220sf::ocp_shared::gpio_pad_config_1::R

type R = R<u32, GPIO_PAD_CONFIG_1>;

Reader of register GPIO_PAD_CONFIG_1

Implementations

impl R

pub fn mem_gpio_pad_config_1(&self) -> MEM_GPIO_PAD_CONFIG_1_R

Bits 0:11 - GPIO 0 register: "Bit 0 - 3 is used for PAD IO mode selection. io_register={ "" 0 => """"CONFMODE[0]"""""" "" 1 => """"CONFMODE[1]"""""" "" 2 => """"CONFMODE[2]"""""" "" 3 => """"CONFMODE[3]"""" 4 => """"IODEN"""" --> When level 1 this disables the PMOS xtors of the output stages making them open-drain type." it can be used for I2C type of peripherals. 5 => """"I2MAEN"""" --> Level 1 enables the approx 2mA output stage""" """ 6 => """"I4MAEN"""" --> Level 1 enables the approx 4mA output stage""" """ 7 => """"I8MAEN"""" --> Level 1 enables the approx 8mA output stage. Note: any drive strength between 2mA and 14mA can be obtained with combination of 2mA 4mA and 8mA.""" """ 8 => """"IWKPUEN"""" --> 10uA pull up (weak strength)""" """ 9 => """"IWKPDEN"""" --> 10uA pull down (weak strength)""" """ 10 => """"IOE_N"""" --> output enable value. level 0 enables the IDO to PAD path. Else PAD is tristated (except for the PU/PD which are independent)." "Value gets latched at rising edge of RET33""" """ 11 =>"""" IOE_N_OV"""" --> output enable overirde. when bit is set to logic '1' IOE_N (bit 4) value will control IO IOE_N signal else IOE_N is control via selected HW logic. strong PULL UP and PULL Down control is disabled for all IO's. both controls are tied to logic level '0'.