1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
#[doc = "Reader of register GPIO_PAD_CONFIG_1"] pub type R = crate::R<u32, super::GPIO_PAD_CONFIG_1>; #[doc = "Writer for register GPIO_PAD_CONFIG_1"] pub type W = crate::W<u32, super::GPIO_PAD_CONFIG_1>; #[doc = "Register GPIO_PAD_CONFIG_1 `reset()`'s with value 0"] impl crate::ResetValue for super::GPIO_PAD_CONFIG_1 { type Type = u32; #[inline(always)] fn reset_value() -> Self::Type { 0 } } #[doc = "Reader of field `MEM_GPIO_PAD_CONFIG_1`"] pub type MEM_GPIO_PAD_CONFIG_1_R = crate::R<u16, u16>; #[doc = "Write proxy for field `MEM_GPIO_PAD_CONFIG_1`"] pub struct MEM_GPIO_PAD_CONFIG_1_W<'a> { w: &'a mut W, } impl<'a> MEM_GPIO_PAD_CONFIG_1_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u16) -> &'a mut W { self.w.bits = (self.w.bits & !0x0fff) | ((value as u32) & 0x0fff); self.w } } impl R { #[doc = "Bits 0:11 - GPIO 0 register: "Bit 0 - 3 is used for PAD IO mode selection. io_register={ "" 0 => """"CONFMODE\\[0\\]"""""" "" 1 => """"CONFMODE\\[1\\]"""""" "" 2 => """"CONFMODE\\[2\\]"""""" "" 3 => """"CONFMODE\\[3\\]"""" 4 => """"IODEN"""" --> When level 1 this disables the PMOS xtors of the output stages making them open-drain type." it can be used for I2C type of peripherals. 5 => """"I2MAEN"""" --> Level 1 enables the approx 2mA output stage""" """ 6 => """"I4MAEN"""" --> Level 1 enables the approx 4mA output stage""" """ 7 => """"I8MAEN"""" --> Level 1 enables the approx 8mA output stage. Note: any drive strength between 2mA and 14mA can be obtained with combination of 2mA 4mA and 8mA.""" """ 8 => """"IWKPUEN"""" --> 10uA pull up (weak strength)""" """ 9 => """"IWKPDEN"""" --> 10uA pull down (weak strength)""" """ 10 => """"IOE_N"""" --> output enable value. level 0 enables the IDO to PAD path. Else PAD is tristated (except for the PU/PD which are independent)." "Value gets latched at rising edge of RET33""" """ 11 =>"""" IOE_N_OV"""" --> output enable overirde. when bit is set to logic '1' IOE_N (bit 4) value will control IO IOE_N signal else IOE_N is control via selected HW logic. strong PULL UP and PULL Down control is disabled for all IO's. both controls are tied to logic level '0'."] #[inline(always)] pub fn mem_gpio_pad_config_1(&self) -> MEM_GPIO_PAD_CONFIG_1_R { MEM_GPIO_PAD_CONFIG_1_R::new((self.bits & 0x0fff) as u16) } } impl W { #[doc = "Bits 0:11 - GPIO 0 register: "Bit 0 - 3 is used for PAD IO mode selection. io_register={ "" 0 => """"CONFMODE\\[0\\]"""""" "" 1 => """"CONFMODE\\[1\\]"""""" "" 2 => """"CONFMODE\\[2\\]"""""" "" 3 => """"CONFMODE\\[3\\]"""" 4 => """"IODEN"""" --> When level 1 this disables the PMOS xtors of the output stages making them open-drain type." it can be used for I2C type of peripherals. 5 => """"I2MAEN"""" --> Level 1 enables the approx 2mA output stage""" """ 6 => """"I4MAEN"""" --> Level 1 enables the approx 4mA output stage""" """ 7 => """"I8MAEN"""" --> Level 1 enables the approx 8mA output stage. Note: any drive strength between 2mA and 14mA can be obtained with combination of 2mA 4mA and 8mA.""" """ 8 => """"IWKPUEN"""" --> 10uA pull up (weak strength)""" """ 9 => """"IWKPDEN"""" --> 10uA pull down (weak strength)""" """ 10 => """"IOE_N"""" --> output enable value. level 0 enables the IDO to PAD path. Else PAD is tristated (except for the PU/PD which are independent)." "Value gets latched at rising edge of RET33""" """ 11 =>"""" IOE_N_OV"""" --> output enable overirde. when bit is set to logic '1' IOE_N (bit 4) value will control IO IOE_N signal else IOE_N is control via selected HW logic. strong PULL UP and PULL Down control is disabled for all IO's. both controls are tied to logic level '0'."] #[inline(always)] pub fn mem_gpio_pad_config_1(&mut self) -> MEM_GPIO_PAD_CONFIG_1_W { MEM_GPIO_PAD_CONFIG_1_W { w: self } } }