Struct cc2538::gpio_c::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {
    pub data: DATA,
    pub dir: DIR,
    pub is: IS,
    pub ibe: IBE,
    pub iev: IEV,
    pub ie: IE,
    pub ris: RIS,
    pub mis: MIS,
    pub ic: IC,
    pub afsel: AFSEL,
    pub gpiolock: GPIOLOCK,
    pub gpiocr: GPIOCR,
    pub pmux: PMUX,
    pub p_edge_ctrl: P_EDGE_CTRL,
    pub usb_ctrl: USB_CTRL,
    pub pi_ien: PI_IEN,
    pub irq_detect_ack: IRQ_DETECT_ACK,
    pub usb_irq_ack: USB_IRQ_ACK,
    pub irq_detect_unmask: IRQ_DETECT_UNMASK,
    // some fields omitted
}

Register block

Fields

data: DATA

0x00 - This is the data register. In software control mode, values written in the GPIODATA register are transferred onto the GPOUT pins if the respective pins have been configured as outputs through the GPIODIR register. A read from GPIODATA returns the last bit value written if the respective pins are configured as output, or it returns the value on the corresponding input GPIN bit when these are configured as inputs.

dir: DIR

0x400 - The DIR register is the data direction register. All bits are cleared by a reset; therefore, the GPIO pins are input by default.

is: IS

0x404 - The IS register is the interrupt sense register.

ibe: IBE

0x408 - The IBE register is the interrupt both-edges register. When the corresponding bit in IS is set to detect edges, bits set to high in IBE configure the corresponding pin to detect both rising and falling edges, regardless of the corresponding bit in the IEV (interrupt event register). Clearing a bit configures the pin to be controlled by IEV.

iev: IEV

0x40c - The IEV register is the interrupt event register. Bits set to high in IEV configure the corresponding pin to detect rising edges or high levels, depending on the corresponding bit value in IS. Clearing a bit configures the pin to detect falling edges or low levels, depending on the corresponding bit value in IS.

ie: IE

0x410 - The IE register is the interrupt mask register. Bits set to high in IE allow the corresponding pins to trigger their individual interrupts and the combined GPIOINTR line. Clearing a bit disables interrupt triggering on that pin.

ris: RIS

0x414 - The RIS register is the raw interrupt status register. Bits read high in RIS reflect the status of interrupts trigger conditions detected (raw, before masking), indicating that all the requirements are met, before they are finally allowed to trigger by IE. Bits read as 0 indicate that corresponding input pins have not initiated an interrupt.

mis: MIS

0x418 - The MIS register is the masked interrupt status register. Bits read high in MIS reflect the status of input lines triggering an interrupt. Bits read as low indicate that either no interrupt has been generated, or the interrupt is masked. MIS is the state of the interrupt after masking.

ic: IC

0x41c - The IC register is the interrupt clear register. Writing 1 to a bit in this register clears the corresponding interrupt edge detection logic register. Writing 0 has no effect.

afsel: AFSEL

0x420 - The AFSEL register is the mode control select register. Writing 1 to any bit in this register selects the hardware (peripheral) control for the corresponding GPIO line. All bits are cleared by a reset, therefore no GPIO line is set to hardware control by default.

gpiolock: GPIOLOCK

0x520 - A write of the value 0x4C4F434B to the GPIOLOCK register unlocks the GPIO commit register (GPIOCR) for write access. A write of any other value reapplies the lock, preventing any register updates. Any write to the commit register (GPIOCR) causes the lock register to be locked.

gpiocr: GPIOCR

0x524 - The GPIOCR register is the commit register. The value of the GPIOCR register determines which bits of the AFSEL register is committed when a write to the AFSEL register is performed. If a bit in the GPIOCR register is 0, the data being written to the corresponding bit in the AFSEL register is not committed and retains its previous value. If a bit in the GPIOCR register is set to 1, the data being written to the corresponding bit of the AFSEL register is committed to the register and will reflect the new value. The contents of the GPIOCR register can only be modified if the GPIOLOCK register is unlocked. Writes to the GPIOCR register will be ignored if the GPIOLOCK register is locked. Any write to the commit register causes the lock register to be locked.

pmux: PMUX

0x700 - The PMUX register can be used to output external decouple control and clock_32k on I/O pins. Decouple control can be output on specific PB pins and clock_32k can be output on a specific PA or PB pin. These features override the current setting of the selected pin when enabled. The pin is set to output, pull-up and -down disabled, and analog mode disabled.

p_edge_ctrl: P_EDGE_CTRL

0x704 - The port edge control register is used to control which edge of each port input causes that port to generate a power-up interrupt to the system.

usb_ctrl: USB_CTRL

0x708 - This register is used to control which edge of the USB controller input generates a power-up interrupt to the system.

pi_ien: PI_IEN

0x710 - The power-up interrupt enable register selects, for its corresponding port A-D pin, whether interrupts are enabled or disabled.

irq_detect_ack: IRQ_DETECT_ACK

0x718 - If the IRQ detect ACK register is read, the value returned can be used to determine which enabled I/O port is responsible for creating a power-up interrupt to the system. Writing the IRQ detect ACK register is used to clear any number of individual port bits that may be signaling that an edge was detected as configured by the port edge control register and the interrupt control register. There is a self-clearing function to this register that generates a reset pulse to clear any interrupt which has its corresponding bit set to 1.

usb_irq_ack: USB_IRQ_ACK

0x71c - Same functionality as IRQ_DETECT_ACK, but for USB

irq_detect_unmask: IRQ_DETECT_UNMASK

0x720 - Same functionality as IRQ_DETECT_ACK, but this register handles masked interrupts