Struct cc2538::ioc::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {
    pub pa0_sel: PA0_SEL,
    pub pa1_sel: PA1_SEL,
    pub pa2_sel: PA2_SEL,
    pub pa3_sel: PA3_SEL,
    pub pa4_sel: PA4_SEL,
    pub pa5_sel: PA5_SEL,
    pub pa6_sel: PA6_SEL,
    pub pa7_sel: PA7_SEL,
    pub pb0_sel: PB0_SEL,
    pub pb1_sel: PB1_SEL,
    pub pb2_sel: PB2_SEL,
    pub pb3_sel: PB3_SEL,
    pub pb4_sel: PB4_SEL,
    pub pb5_sel: PB5_SEL,
    pub pb6_sel: PB6_SEL,
    pub pb7_sel: PB7_SEL,
    pub pc0_sel: PC0_SEL,
    pub pc1_sel: PC1_SEL,
    pub pc2_sel: PC2_SEL,
    pub pc3_sel: PC3_SEL,
    pub pc4_sel: PC4_SEL,
    pub pc5_sel: PC5_SEL,
    pub pc6_sel: PC6_SEL,
    pub pc7_sel: PC7_SEL,
    pub pd0_sel: PD0_SEL,
    pub pd1_sel: PD1_SEL,
    pub pd2_sel: PD2_SEL,
    pub pd3_sel: PD3_SEL,
    pub pd4_sel: PD4_SEL,
    pub pd5_sel: PD5_SEL,
    pub pd6_sel: PD6_SEL,
    pub pd7_sel: PD7_SEL,
    pub pa0_over: PA0_OVER,
    pub pa1_over: PA1_OVER,
    pub pa2_over: PA2_OVER,
    pub pa3_over: PA3_OVER,
    pub pa4_over: PA4_OVER,
    pub pa5_over: PA5_OVER,
    pub pa6_over: PA6_OVER,
    pub pa7_over: PA7_OVER,
    pub pb0_over: PB0_OVER,
    pub pb1_over: PB1_OVER,
    pub pb2_over: PB2_OVER,
    pub pb3_over: PB3_OVER,
    pub pb4_over: PB4_OVER,
    pub pb5_over: PB5_OVER,
    pub pb6_over: PB6_OVER,
    pub pb7_over: PB7_OVER,
    pub pc0_over: PC0_OVER,
    pub pc1_over: PC1_OVER,
    pub pc2_over: PC2_OVER,
    pub pc3_over: PC3_OVER,
    pub pc4_over: PC4_OVER,
    pub pc5_over: PC5_OVER,
    pub pc6_over: PC6_OVER,
    pub pc7_over: PC7_OVER,
    pub pd0_over: PD0_OVER,
    pub pd1_over: PD1_OVER,
    pub pd2_over: PD2_OVER,
    pub pd3_over: PD3_OVER,
    pub pd4_over: PD4_OVER,
    pub pd5_over: PD5_OVER,
    pub pd6_over: PD6_OVER,
    pub pd7_over: PD7_OVER,
    pub uartrxd_uart0: UARTRXD_UART0,
    pub uartcts_uart1: UARTCTS_UART1,
    pub uartrxd_uart1: UARTRXD_UART1,
    pub clk_ssi_ssi0: CLK_SSI_SSI0,
    pub ssirxd_ssi0: SSIRXD_SSI0,
    pub ssifssin_ssi0: SSIFSSIN_SSI0,
    pub clk_ssiin_ssi0: CLK_SSIIN_SSI0,
    pub clk_ssi_ssi1: CLK_SSI_SSI1,
    pub ssirxd_ssi1: SSIRXD_SSI1,
    pub ssifssin_ssi1: SSIFSSIN_SSI1,
    pub clk_ssiin_ssi1: CLK_SSIIN_SSI1,
    pub i2cmssda: I2CMSSDA,
    pub i2cmsscl: I2CMSSCL,
    pub gpt0ocp1: GPT0OCP1,
    pub gpt0ocp2: GPT0OCP2,
    pub gpt1ocp1: GPT1OCP1,
    pub gpt1ocp2: GPT1OCP2,
    pub gpt2ocp1: GPT2OCP1,
    pub gpt2ocp2: GPT2OCP2,
    pub gpt3ocp1: GPT3OCP1,
    pub gpt3ocp2: GPT3OCP2,
}

Register block

Fields

pa0_sel: PA0_SEL

0x00 - Peripheral select control for PA0

pa1_sel: PA1_SEL

0x04 - Peripheral select control for PA1

pa2_sel: PA2_SEL

0x08 - Peripheral select control for PA2

pa3_sel: PA3_SEL

0x0c - Peripheral select control for PA3

pa4_sel: PA4_SEL

0x10 - Peripheral select control for PA4

pa5_sel: PA5_SEL

0x14 - Peripheral select control for PA5

pa6_sel: PA6_SEL

0x18 - Peripheral select control for PA6

pa7_sel: PA7_SEL

0x1c - Peripheral select control for PA7

pb0_sel: PB0_SEL

0x20 - Peripheral select control for PB0

pb1_sel: PB1_SEL

0x24 - Peripheral select control for PB1

pb2_sel: PB2_SEL

0x28 - Peripheral select control for PB2

pb3_sel: PB3_SEL

0x2c - Peripheral select control for PB3

pb4_sel: PB4_SEL

0x30 - Peripheral select control for PB4

pb5_sel: PB5_SEL

0x34 - Peripheral select control for PB5

pb6_sel: PB6_SEL

0x38 - Peripheral select control for PB6

pb7_sel: PB7_SEL

0x3c - Peripheral select control for PB7

pc0_sel: PC0_SEL

0x40 - Peripheral select control for PC0

pc1_sel: PC1_SEL

0x44 - Peripheral select control for PC1

pc2_sel: PC2_SEL

0x48 - Peripheral select control for PC2

pc3_sel: PC3_SEL

0x4c - Peripheral select control for PC3

pc4_sel: PC4_SEL

0x50 - Peripheral select control for PC4

pc5_sel: PC5_SEL

0x54 - Peripheral select control for PC5

pc6_sel: PC6_SEL

0x58 - Peripheral select control for PC6

pc7_sel: PC7_SEL

0x5c - Peripheral select control for PC7

pd0_sel: PD0_SEL

0x60 - Peripheral select control for PD0

pd1_sel: PD1_SEL

0x64 - Peripheral select control for PD1

pd2_sel: PD2_SEL

0x68 - Peripheral select control for PD2

pd3_sel: PD3_SEL

0x6c - Peripheral select control for PD3

pd4_sel: PD4_SEL

0x70 - Peripheral select control for PD4

pd5_sel: PD5_SEL

0x74 - Peripheral select control for PD5

pd6_sel: PD6_SEL

0x78 - Peripheral select control for PD6

pd7_sel: PD7_SEL

0x7c - Peripheral select control for PD7

pa0_over: PA0_OVER

0x80 - This is the overide configuration register for each pad.

pa1_over: PA1_OVER

0x84 - This is the overide configuration register for each pad.

pa2_over: PA2_OVER

0x88 - This is the overide configuration register for each pad.

pa3_over: PA3_OVER

0x8c - This is the overide configuration register for each pad.

pa4_over: PA4_OVER

0x90 - This is the overide configuration register for each pad.

pa5_over: PA5_OVER

0x94 - This is the overide configuration register for each pad.

pa6_over: PA6_OVER

0x98 - This is the overide configuration register for each pad.

pa7_over: PA7_OVER

0x9c - This is the overide configuration register for each pad.

pb0_over: PB0_OVER

0xa0 - This is the overide configuration register for each pad.

pb1_over: PB1_OVER

0xa4 - This is the overide configuration register for each pad.

pb2_over: PB2_OVER

0xa8 - This is the overide configuration register for each pad.

pb3_over: PB3_OVER

0xac - This is the overide configuration register for each pad.

pb4_over: PB4_OVER

0xb0 - This is the overide configuration register for each pad.

pb5_over: PB5_OVER

0xb4 - This is the overide configuration register for each pad.

pb6_over: PB6_OVER

0xb8 - This is the overide configuration register for each pad.

pb7_over: PB7_OVER

0xbc - This is the overide configuration register for each pad.

pc0_over: PC0_OVER

0xc0 - This is the overide configuration register for each pad. PC0 has high drive capability.

pc1_over: PC1_OVER

0xc4 - This is the overide configuration register for each pad. PC1 has high drive capability.

pc2_over: PC2_OVER

0xc8 - This is the overide configuration register for each pad. PC2 has high drive capability.

pc3_over: PC3_OVER

0xcc - This is the overide configuration register for each pad. PC3 has high drive capability.

pc4_over: PC4_OVER

0xd0 - This is the overide configuration register for each pad.

pc5_over: PC5_OVER

0xd4 - This is the overide configuration register for each pad.

pc6_over: PC6_OVER

0xd8 - This is the overide configuration register for each pad.

pc7_over: PC7_OVER

0xdc - This is the overide configuration register for each pad.

pd0_over: PD0_OVER

0xe0 - This is the overide configuration register for each pad.

pd1_over: PD1_OVER

0xe4 - This is the overide configuration register for each pad.

pd2_over: PD2_OVER

0xe8 - This is the overide configuration register for each pad.

pd3_over: PD3_OVER

0xec - This is the overide configuration register for each pad.

pd4_over: PD4_OVER

0xf0 - This is the overide configuration register for each pad.

pd5_over: PD5_OVER

0xf4 - This is the overide configuration register for each pad.

pd6_over: PD6_OVER

0xf8 - This is the overide configuration register for each pad.

pd7_over: PD7_OVER

0xfc - This is the overide configuration register for each pad.

uartrxd_uart0: UARTRXD_UART0

0x100 - Selects one of the 32 pins on the four 8-pin I/O-ports (port A, port B, port C, and port D) to be the UART0 RX.

uartcts_uart1: UARTCTS_UART1

0x104 - Selects one of the 32 pins on the four 8-pin I/O-ports (port A, port B, port C, and port D) to be the UART1 CTS.

uartrxd_uart1: UARTRXD_UART1

0x108 - Selects one of the 32 pins on the four 8-pin I/O-ports (port A, port B, port C, and port D) to be the UART1 RX.

clk_ssi_ssi0: CLK_SSI_SSI0

0x10c - Selects one of the 32 pins on the four 8-pin I/O-ports (port A, port B, port C, and port D) to be the SSI0 CLK.

ssirxd_ssi0: SSIRXD_SSI0

0x110 - Selects one of the 32 pins on the four 8-pin I/O-ports (port A, port B, port C, and port D) to be the SSI0 RX.

ssifssin_ssi0: SSIFSSIN_SSI0

0x114 - Selects one of the 32 pins on the four 8-pin I/O-ports (port A, port B, port C, and port D) to be the SSI0 FSSIN.

clk_ssiin_ssi0: CLK_SSIIN_SSI0

0x118 - Selects one of the 32 pins on the four 8-pin I/O-ports (port A, port B, port C, and port D) to be the SSI0 CLK_SSIN.

clk_ssi_ssi1: CLK_SSI_SSI1

0x11c - Selects one of the 32 pins on the four 8-pin I/O-ports (port A, port B, port C, and port D) to be the SSI1 CLK.

ssirxd_ssi1: SSIRXD_SSI1

0x120 - Selects one of the 32 pins on the four 8-pin I/O-ports (port A, port B, port C, and port D) to be the SSI1 RX.

ssifssin_ssi1: SSIFSSIN_SSI1

0x124 - Selects one of the 32 pins on the four 8-pin I/O-ports (port A, port B, port C, and port D) to be the SSI1 FSSIN.

clk_ssiin_ssi1: CLK_SSIIN_SSI1

0x128 - Selects one of the 32 pins on the four 8-pin I/O-ports (port A, port B, port C, and port D) to be the SSI1 CLK_SSIN.

i2cmssda: I2CMSSDA

0x12c - Selects one of the 32 pins on the four 8-pin I/O-ports (port A, port B, port C, and port D) to be the I2C SDA.

i2cmsscl: I2CMSSCL

0x130 - Selects one of the 32 pins on the four 8-pin I/O-ports (port A, port B, port C, and port D) to be the I2C SCL.

gpt0ocp1: GPT0OCP1

0x134 - Selects one of the 32 pins on the four 8-pin I/O-ports (port A, port B, port C, and port D) to be the GPT0OCP1.

gpt0ocp2: GPT0OCP2

0x138 - Selects one of the 32 pins on the four 8-pin I/O-ports (port A, port B, port C, and port D) to be the GPT0OCP2.

gpt1ocp1: GPT1OCP1

0x13c - Selects one of the 32 pins on the four 8-pin I/O-ports (port A, port B, port C, and port D) to be the GPT1OCP1.

gpt1ocp2: GPT1OCP2

0x140 - Selects one of the 32 pins on the four 8-pin I/O-ports (port A, port B, port C, and port D) to be the GPT1OCP2.

gpt2ocp1: GPT2OCP1

0x144 - Selects one of the 32 pins on the four 8-pin I/O-ports (port A, port B, port C, and port D) to be the GPT2OCP1.

gpt2ocp2: GPT2OCP2

0x148 - Selects one of the 32 pins on the four 8-pin I/O-ports (port A, port B, port C, and port D) to be the GPT2OCP2.

gpt3ocp1: GPT3OCP1

0x14c - Selects one of the 32 pins on the four 8-pin I/O-ports (port A, port B, port C, and port D) to be the GPT3OCP1.

gpt3ocp2: GPT3OCP2

0x150 - Selects one of the 32 pins on the four 8-pin I/O-ports (port A, port B, port C, and port D) to be the GPT3OCP2.