[−][src]Type Definition cc2538::gptimer2::MIS
type MIS = Reg<u32, _MIS>;
GPTM masked interrupt status This register shows the state of the GPTM controller-level interrupt. If an interrupt is unmasked in IMR, and there is an event that causes the interrupt to be asserted, the corresponding bit is set in this register. All bits are cleared by writing 1 to the corresponding bit in ICR.
This register you can read
, reset
, write
, write_with_zero
, modify
. See API.
For information about avaliable fields see mis module