Type Definition cc2538::gptimer0::MIS

type MIS = Reg<u32, _MIS>;

GPTM masked interrupt status This register shows the state of the GPTM controller-level interrupt. If an interrupt is unmasked in IMR, and there is an event that causes the interrupt to be asserted, the corresponding bit is set in this register. All bits are cleared by writing 1 to the corresponding bit in ICR.

This register you can read, reset, write, write_with_zero, modify. See API.

For information about avaliable fields see mis module

Trait Implementations

impl Readable for MIS

read() method returns mis::R reader structure

impl Writable for MIS

write(|w| ..) method takes mis::W writer structure

impl ResetValue for MIS

Register MIS reset()'s with value 0

type Type = u32

Register size

fn reset_value() -> Self::Type

Reset value of the register