Module cc2538::gptimer0::mis

GPTM masked interrupt status This register shows the state of the GPTM controller-level interrupt. If an interrupt is unmasked in IMR, and there is an event that causes the interrupt to be asserted, the corresponding bit is set in this register. All bits are cleared by writing 1 to the corresponding bit in ICR.

Structs

CAEMIS_W	Write proxy for field CAEMIS
CAMMIS_W	Write proxy for field CAMMIS
CBEMIS_W	Write proxy for field CBEMIS
CBMMIS_W	Write proxy for field CBMMIS
RESERVED3_W	Write proxy for field Reserved3
RESERVED8_W	Write proxy for field Reserved8
RESERVED32_W	Write proxy for field Reserved32
TAMRIS_W	Write proxy for field TAMRIS
TATOMIS_W	Write proxy for field TATOMIS
TBMMIS_W	Write proxy for field TBMMIS
TBTOMIS_W	Write proxy for field TBTOMIS

Type Definitions

CAEMIS_R	Reader of field CAEMIS
CAMMIS_R	Reader of field CAMMIS
CBEMIS_R	Reader of field CBEMIS
CBMMIS_R	Reader of field CBMMIS
R	Reader of register MIS
RESERVED3_R	Reader of field Reserved3
RESERVED8_R	Reader of field Reserved8
RESERVED32_R	Reader of field Reserved32
TAMRIS_R	Reader of field TAMRIS
TATOMIS_R	Reader of field TATOMIS
TBMMIS_R	Reader of field TBMMIS
TBTOMIS_R	Reader of field TBTOMIS
W	Writer for register MIS