[][src]Type Definition cc2538::aes::ctrl_sw_reset::R

type R = R<u32, CTRL_SW_RESET>;

Reader of register CTRL_SW_RESET

Methods

impl R[src]

pub fn reserved31(&self) -> RESERVED31_R[src]

Bits 1:31 - 31:1] Bits should be written with 0s and ignored on read.

pub fn sw_reset(&self) -> SW_RESET_R[src]

Bit 0 - 0:0] If this bit is set to 1, the following modules are reset: - Master control internal state is reset. That includes interrupt, error status register, and result available interrupt generation FSM. - Key store module state is reset. That includes clearing the written area flags; therefore, the keys must be reloaded to the key store module. Writing 0 has no effect. The bit is self cleared after executing the reset.