Struct cc13x2_cc26x2_hal::aux_sysif::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {
    pub opmodereq: OPMODEREQ,
    pub opmodeack: OPMODEACK,
    pub progwu0cfg: PROGWU0CFG,
    pub progwu1cfg: PROGWU1CFG,
    pub progwu2cfg: PROGWU2CFG,
    pub progwu3cfg: PROGWU3CFG,
    pub swwutrig: SWWUTRIG,
    pub wuflags: WUFLAGS,
    pub wuflagsclr: WUFLAGSCLR,
    pub wugate: WUGATE,
    pub veccfg0: VECCFG0,
    pub veccfg1: VECCFG1,
    pub veccfg2: VECCFG2,
    pub veccfg3: VECCFG3,
    pub veccfg4: VECCFG4,
    pub veccfg5: VECCFG5,
    pub veccfg6: VECCFG6,
    pub veccfg7: VECCFG7,
    pub evsyncrate: EVSYNCRATE,
    pub peroprate: PEROPRATE,
    pub adcclkctl: ADCCLKCTL,
    pub tdcclkctl: TDCCLKCTL,
    pub tdcrefclkctl: TDCREFCLKCTL,
    pub timer2clkctl: TIMER2CLKCTL,
    pub timer2clkstat: TIMER2CLKSTAT,
    pub timer2clkswitch: TIMER2CLKSWITCH,
    pub timer2dbgctl: TIMER2DBGCTL,
    pub clkshiftdet: CLKSHIFTDET,
    pub rechargetrig: RECHARGETRIG,
    pub rechargedet: RECHARGEDET,
    pub rtcsubsecinc0: RTCSUBSECINC0,
    pub rtcsubsecinc1: RTCSUBSECINC1,
    pub rtcsubsecincctl: RTCSUBSECINCCTL,
    pub rtcsec: RTCSEC,
    pub rtcsubsec: RTCSUBSEC,
    pub rtcevclr: RTCEVCLR,
    pub batmonbat: BATMONBAT,
    pub batmontemp: BATMONTEMP,
    pub timerhalt: TIMERHALT,
    pub timer2bridge: TIMER2BRIDGE,
    pub swpwrprof: SWPWRPROF,
    // some fields omitted
}

Register block

Fields

opmodereq: OPMODEREQ

0x00 - Operational Mode Request AUX can operate in three operational modes. Each mode is associated with: - a SCE clock source or rate, given by AON_PMCTL:AUXSCECLK. This rate is termed SCE_RATE. - a system power supply state request. AUX can request powerdown (uLDO) or active (GLDO or DCDC) system power supply state. - a specific system response to an active AUX wakeup flag. The response is dependent on what operational mode is requested. uLDO power supply state offers limited current supply. AUX_SCE cannot use certain peripherals and functions such as AUX_DDI0_OSC, AUX_TDC and AUX_ANAIF ADC interface in this power supply state. Follow these rules: - It is not allowed to change a request until it has been acknowledged through OPMODEACK. - A change in mode request must happen stepwise along this sequence, the direction is irrelevant: PDA - A - LP - PDLP. Failure to follow these rules might result in unexpected behavior and must be avoided.

opmodeack: OPMODEACK

0x04 - Operational Mode Acknowledgement AUX_SCE program must assume that the current operational mode is the one acknowledged.

progwu0cfg: PROGWU0CFG

0x08 - Programmable Wakeup 0 Configuration Configure this register to enable a customized AUX wakeup flag. The wakeup flag will be captured by AON_PMCTL which responds according to the current operational mode. You can select WUFLAGS.PROG_WU0 to trigger execution of a programmable AUX_SCE vector by configuration of VECCFGn. You need to follow the procedure described in WUFLAGSCLR to clear this flag. You need to follow the procedure described in WUGATE to configure it.

progwu1cfg: PROGWU1CFG

0x0c - Programmable Wakeup 1 Configuration Configure this register to enable a customized AUX wakeup flag. The wakeup flag will be captured by AON_PMCTL which responds according to the current operational mode. You can select WUFLAGS.PROG_WU1 to trigger execution of a programmable AUX_SCE vector by configuration of VECCFGn. You need to follow the procedure described in WUFLAGSCLR to clear this flag. You need to follow the procedure described in WUGATE to configure it.

progwu2cfg: PROGWU2CFG

0x10 - Programmable Wakeup 2 Configuration Configure this register to enable a customized AUX wakeup flag. The wakeup flag will be captured by AON_PMCTL which responds according to the current operational mode. You can select WUFLAGS.PROG_WU2 to trigger execution of a programmable AUX_SCE vector by configuration of VECCFGn. You need to follow the procedure described in WUFLAGSCLR to clear this flag. You need to follow the procedure described in WUGATE to configure it.

progwu3cfg: PROGWU3CFG

0x14 - Programmable Wakeup 3 Configuration Configure this register to enable a customized AUX wakeup flag. The wakeup flag will be captured by AON_PMCTL which responds according to the current operational mode. You can select WUFLAGS.PROG_WU3 to trigger execution of a programmable AUX_SCE vector by configuration of VECCFGn. You need to follow the procedure described in WUFLAGSCLR to clear this flag. You need to follow the procedure described in WUGATE to configure it.

swwutrig: SWWUTRIG

0x18 - Software Wakeup Triggers System CPU uses these wakeup flags to perform handshaking with AUX_SCE. The wakeup flags can change the operational mode of AUX and guarantees a non-zero SCE clock rate. AUX_SCE wakeup vectors are configured in VECCFGn.

wuflags: WUFLAGS

0x1c - Wakeup Flags This register holds the eight AUX wakeup flags. Each flag can cause AUX operational mode to change as given in OPMODEREQ. To clear flag n you must set bit n in WUFLAGSCLR until flag n is read as 0. You must clear bit n in WUFLAGSCLR before flag n can be set again.

wuflagsclr: WUFLAGSCLR

0x20 - Wakeup Flags Clear This register clears AUX wakeup flags WUFLAGS. To clear programmable wakeup flags you must disable the AUX wakeup output first. After the programmable wakeup flags are cleared you must re-enable the AUX wakeup output. Write WUGATE to disable or enable the AUX wakeup output. This procedure is not required when you want to clear a software-triggered wakeup.

wugate: WUGATE

0x24 - Wakeup Gate You must disable the AUX wakeup output: - Before you clear a programmable wakeup flag. - Before you change the value of [PROGWUnCFG.EN] or [PROGWUnCFG.WU_SRC]. The AUX wakeup output must be re-enabled after clear operation or programmable wakeup configuration.

veccfg0: VECCFG0

0x28 - Vector Configuration 0 AUX_SCE wakeup vector 0 configuration

veccfg1: VECCFG1

0x2c - Vector Configuration 1 AUX_SCE wakeup vector 1 configuration

veccfg2: VECCFG2

0x30 - Vector Configuration 2 AUX_SCE wakeup vector 2 configuration

veccfg3: VECCFG3

0x34 - Vector Configuration 3 AUX_SCE wakeup vector 3 configuration

veccfg4: VECCFG4

0x38 - Vector Configuration 4 AUX_SCE wakeup vector 4 configuration

veccfg5: VECCFG5

0x3c - Vector Configuration 5 AUX_SCE wakeup vector 5 configuration

veccfg6: VECCFG6

0x40 - Vector Configuration 6 AUX_SCE wakeup vector 6 configuration

veccfg7: VECCFG7

0x44 - Vector Configuration 7 AUX_SCE wakeup vector 7 configuration

evsyncrate: EVSYNCRATE

0x48 - Event Synchronization Rate Configure synchronization rate for certain events to the synchronous AUX event bus. You must select SCE rate when AUX_SCE uses the event. You must select AUX bus rate when system CPU uses the event. SCE rate equals rate configured in AON_PMCTL:AUXSCECLK. AUX bus rate equals SCE rate, or SCLK_HF divided by two when MCU domain is active.

peroprate: PEROPRATE

0x4c - Peripheral Operational Rate Some AUX peripherals are operated at either SCE or at AUX bus rate. You must select SCE rate when AUX_SCE uses such peripheral or an event produced by it. You must select AUX bus rate when system CPU uses such peripheral. SCE rate equals rate configured in AON_PMCTL:AUXSCECLK. AUX bus rate equals SCE rate, or SCLK_HF divided by 2 when MCU domain is active.

adcclkctl: ADCCLKCTL

0x50 - ADC Clock Control

tdcclkctl: TDCCLKCTL

0x54 - TDC Counter Clock Control Controls if the AUX_TDC counter clock source is enabled. TDC counter clock source is configured in DDI_0_OSC:CTL0.ACLK_TDC_SRC_SEL.

tdcrefclkctl: TDCREFCLKCTL

0x58 - TDC Reference Clock Control Controls if the AUX_TDC reference clock source is enabled. This clock is compared against the AUX_TDC counter clock. TDC reference clock source is configured in DDI_0_OSC:CTL0.ACLK_REF_SRC_SEL.

timer2clkctl: TIMER2CLKCTL

0x5c - AUX_TIMER2 Clock Control Access to AUX_TIMER2 is only possible when TIMER2CLKSTAT.STAT is different from NONE.

timer2clkstat: TIMER2CLKSTAT

0x60 - AUX_TIMER2 Clock Status

timer2clkswitch: TIMER2CLKSWITCH

0x64 - AUX_TIMER2 Clock Switch

timer2dbgctl: TIMER2DBGCTL

0x68 - AUX_TIMER2 Debug Control

clkshiftdet: CLKSHIFTDET

0x70 - Clock Shift Detection A transition in the MCU domain state causes a non-accumulative change to the SCE clock period when the AUX clock rate is derived from SCLK_MF or SCLK_LF: - A single SCE clock cycle is 6 thru 8 SCLK_HF cycles longer when MCU domain enters active state. - A single SCE clock cycle is 6 thru 8 SCLK_HF cycles shorter when MCU domain exits active state. AUX_SCE detects if such events occurred to the SCE clock during the time period between a clear of STAT and a read of STAT.

rechargetrig: RECHARGETRIG

0x74 - VDDR Recharge Trigger

rechargedet: RECHARGEDET

0x78 - VDDR Recharge Detection Some applications can be sensitive to power noise caused by recharge of VDDR. You can detect if VDDR recharge occurs.

rtcsubsecinc0: RTCSUBSECINC0

0x7c - Real Time Counter Sub Second Increment 0 INC15_0 will replace bits 15:0 in AON_RTC:SUBSECINC when RTCSUBSECINCCTL.UPD_REQ is set.

rtcsubsecinc1: RTCSUBSECINC1

0x80 - Real Time Counter Sub Second Increment 1 INC23_16 will replace bits 23:16 in AON_RTC:SUBSECINC when RTCSUBSECINCCTL.UPD_REQ is set.

rtcsubsecincctl: RTCSUBSECINCCTL

0x84 - Real Time Counter Sub Second Increment Control

rtcsec: RTCSEC

0x88 - Real Time Counter Second System CPU must not access this register. Instead, system CPU must access AON_RTC:SEC.VALUE directly.

rtcsubsec: RTCSUBSEC

0x8c - Real Time Counter Sub-Second System CPU must not access this register. Instead, system CPU must access AON_RTC:SUBSEC.VALUE directly.

rtcevclr: RTCEVCLR

0x90 - AON_RTC Event Clear Request to clear events: - AON_RTC:EVFLAGS.CH2. - AON_RTC:EVFLAGS.CH2 delayed version. - AUX_EVCTL:EVSTAT2.AON_RTC_CH2. - AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY.

batmonbat: BATMONBAT

0x94 - AON_BATMON Battery Voltage Value Read access to AON_BATMON:BAT. System CPU must not access this register. Instead, system CPU must access AON_BATMON:BAT directly. AON_BATMON:BAT updates during VDDR recharge or active operational mode.

batmontemp: BATMONTEMP

0x9c - AON_BATMON Temperature Value Read access to AON_BATMON:TEMP. System CPU must not access this register. Instead, system CPU must access AON_BATMON:TEMP directly. AON_BATMON:TEMP updates during VDDR recharge or active operational mode.

timerhalt: TIMERHALT

0xa0 - Timer Halt Debug register

timer2bridge: TIMER2BRIDGE

0xb0 - AUX_TIMER2 Bridge

swpwrprof: SWPWRPROF

0xb4 - Software Power Profiler