[−][src]Struct cc13x2_cc26x2_hal::cpu_itm::RegisterBlock
Register block
Fields
stim0: STIM0
0x00 - Stimulus Port 0
stim1: STIM1
0x04 - Stimulus Port 1
stim2: STIM2
0x08 - Stimulus Port 2
stim3: STIM3
0x0c - Stimulus Port 3
stim4: STIM4
0x10 - Stimulus Port 4
stim5: STIM5
0x14 - Stimulus Port 5
stim6: STIM6
0x18 - Stimulus Port 6
stim7: STIM7
0x1c - Stimulus Port 7
stim8: STIM8
0x20 - Stimulus Port 8
stim9: STIM9
0x24 - Stimulus Port 9
stim10: STIM10
0x28 - Stimulus Port 10
stim11: STIM11
0x2c - Stimulus Port 11
stim12: STIM12
0x30 - Stimulus Port 12
stim13: STIM13
0x34 - Stimulus Port 13
stim14: STIM14
0x38 - Stimulus Port 14
stim15: STIM15
0x3c - Stimulus Port 15
stim16: STIM16
0x40 - Stimulus Port 16
stim17: STIM17
0x44 - Stimulus Port 17
stim18: STIM18
0x48 - Stimulus Port 18
stim19: STIM19
0x4c - Stimulus Port 19
stim20: STIM20
0x50 - Stimulus Port 20
stim21: STIM21
0x54 - Stimulus Port 21
stim22: STIM22
0x58 - Stimulus Port 22
stim23: STIM23
0x5c - Stimulus Port 23
stim24: STIM24
0x60 - Stimulus Port 24
stim25: STIM25
0x64 - Stimulus Port 25
stim26: STIM26
0x68 - Stimulus Port 26
stim27: STIM27
0x6c - Stimulus Port 27
stim28: STIM28
0x70 - Stimulus Port 28
stim29: STIM29
0x74 - Stimulus Port 29
stim30: STIM30
0x78 - Stimulus Port 30
stim31: STIM31
0x7c - Stimulus Port 31
ter: TER
0xe00 - Trace Enable Use the Trace Enable Register to generate trace data by writing to the corresponding stimulus port. Note: Privileged writes are accepted to this register if TCR.ITMENA is set. User writes are accepted to this register if TCR.ITMENA is set and the appropriate privilege mask is cleared. Privileged access to the stimulus ports enables an RTOS kernel to guarantee instrumentation slots or bandwidth as required.
tpr: TPR
0xe40 - Trace Privilege This register is used to enable an operating system to control which stimulus ports are accessible by user code. This register can only be used in privileged mode.
tcr: TCR
0xe80 - Trace Control Use this register to configure and control ITM transfers. This register can only be written in privilege mode. DWT is not enabled in the ITM block. However, DWT stimulus entry into the FIFO is controlled by DWTENA. If DWT requires timestamping, the TSENA bit must be set.
lar: LAR
0xfb0 - Lock Access This register is used to prevent write accesses to the Control Registers: TER, TPR and TCR.
lsr: LSR
0xfb4 - Lock Status Use this register to enable write accesses to the Control Register.
Auto Trait Implementations
impl Send for RegisterBlock
impl !Sync for RegisterBlock
Blanket Implementations
impl<T> From for T
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impl<T, U> TryFrom for T where
U: Into<T>,
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U: Into<T>,
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The type returned in the event of a conversion error.
fn try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>
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impl<T, U> TryInto for T where
U: TryFrom<T>,
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U: TryFrom<T>,
type Error = <U as TryFrom<T>>::Error
The type returned in the event of a conversion error.
fn try_into(self) -> Result<U, <U as TryFrom<T>>::Error>
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impl<T, U> Into for T where
U: From<T>,
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U: From<T>,
impl<T> Borrow for T where
T: ?Sized,
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T: ?Sized,
impl<T> BorrowMut for T where
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T: ?Sized,
fn borrow_mut(&mut self) -> &mut T
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impl<T> Any for T where
T: 'static + ?Sized,
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T: 'static + ?Sized,
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Should always be Self