[−][src]Struct cc13x2_cc26x2_hal::aux_timer2::ctl::W
Value to write to the register
Methods
impl W
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pub fn reset_value() -> W
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Reset value of the register
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self
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Writes raw bits to the register
pub fn reserved7(&mut self) -> _RESERVED7W
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Bits 7:31 - 31:7] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
pub fn ch3_reset(&mut self) -> _CH3_RESETW
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Bit 6 - 6:6] Channel 3 reset. 0: No effect. 1: Reset CH3CC, CH3PCC, CH3EVCFG, and CH3CCFG. Read returns 0.
pub fn ch2_reset(&mut self) -> _CH2_RESETW
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Bit 5 - 5:5] Channel 2 reset. 0: No effect. 1: Reset CH2CC, CH2PCC, CH2EVCFG, and CH2CCFG. Read returns 0.
pub fn ch1_reset(&mut self) -> _CH1_RESETW
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Bit 4 - 4:4] Channel 1 reset. 0: No effect. 1: Reset CH1CC, CH1PCC, CH1EVCFG, and CH1CCFG. Read returns 0.
pub fn ch0_reset(&mut self) -> _CH0_RESETW
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Bit 3 - 3:3] Channel 0 reset. 0: No effect. 1: Reset CH0CC, CH0PCC, CH0EVCFG, and CH0CCFG. Read returns 0.
pub fn target_en(&mut self) -> _TARGET_ENW
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Bit 2 - 2:2] Select counter target value. You must select TARGET to use shadow target functionality.
pub fn mode(&mut self) -> _MODEW
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Bits 0:1 - 1:0] Timer mode control. The timer restarts from 0 when you set MODE to UP_ONCE, UP_PER, or UPDWN_PER. When you write MODE all internally queued updates to [CHnCC.*] and TARGET clear.
Auto Trait Implementations
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