[−][src]Struct cc13x2_cc26x2_hal::aux_aiodio1::iomode::_IO0W
Proxy
Methods
impl<'a> _IO0W<'a>
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pub fn variant(self, variant: IO0W) -> &'a mut W
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Writes variant
to the field
pub fn open_source(self) -> &'a mut W
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Open-Source Mode: When IOPOE bit 0 is 0: - If GPIODOUT bit 0 is 0: AUXIO[8i+0] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If GPIODOUT bit 0 is 1: AUXIO[8i+0] is driven high. When IOPOE bit 0 is 1: - If signal selected by IO0PSEL.SRC is 0: AUXIO[8i+0] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If signal selected by IO0PSEL.SRC is 1: AUXIO[8i+0] is driven high.
pub fn open_drain(self) -> &'a mut W
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Open-Drain Mode: When IOPOE bit 0 is 0: - If GPIODOUT bit 0 is 0: AUXIO[8i+0] is driven low. - If GPIODOUT bit 0 is 1: AUXIO[8i+0] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. When IOPOE bit 0 is 1: - If signal selected by IO0PSEL.SRC is 0: AUXIO[8i+0] is driven low. - If signal selected by IO0PSEL.SRC is 1: AUXIO[8i+0] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
pub fn in_(self) -> &'a mut W
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Input Mode: When GPIODIE bit 0 is 0: AUXIO[8i+0] is enabled for analog signal transfer. When GPIODIE bit 0 is 1: AUXIO[8i+0] is enabled for digital input.
pub fn out(self) -> &'a mut W
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Output Mode: When IOPOE bit 0 is 0: GPIODOUT bit 0 drives AUXIO[8i+0]. When IOPOE bit 0 is 1: The signal selected by IO0PSEL.SRC drives AUXIO[8i+0].
pub fn bits(self, value: u8) -> &'a mut W
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Writes raw bits to the field
Auto Trait Implementations
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impl<T> From for T
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impl<T, U> TryFrom for T where
U: Into<T>,
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impl<T, U> TryInto for T where
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U: TryFrom<T>,
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T: 'static + ?Sized,
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