[−][src]Struct cc13x2_cc26x2_hal::aon_rtc::subsecinc::W
Value to write to the register
Methods
impl W
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pub fn reset_value() -> W
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Reset value of the register
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self
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Writes raw bits to the register
pub fn reserved24(&mut self) -> _RESERVED24W
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Bits 24:31 - 31:24] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
pub fn valueinc(&mut self) -> _VALUEINCW
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Bits 0:23 - 23:0] This value compensates for a SCLK_LF clock which has an offset from 32768 Hz. The compensation value can be found as 2^38 / freq, where freq is SCLK_LF clock frequency in Hertz This value is added to SUBSEC.VALUE on every cycle, and carry of this is added to SEC.VALUE. To perform the addition, bits [23:6] are aligned with SUBSEC.VALUE bits [17:0]. The remaining bits [5:0] are accumulated in a hidden 6-bit register that generates a carry into the above mentioned addition on overflow. The default value corresponds to incrementing by precisely 1/32768 of a second. NOTE: This register is read only. Modification of the register value must be done using registers AUX_SYSIF:RTCSUBSECINC0 , AUX_SYSIF:RTCSUBSECINC1 and AUX_SYSIF:RTCSUBSECINCCTL
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