[−][src]Struct cc13x2_cc26x2_hal::uart1::imsc::W
Value to write to the register
Methods
impl W
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pub fn reset_value() -> W
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Reset value of the register
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self
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Writes raw bits to the register
pub fn reserved12(&mut self) -> _RESERVED12W
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Bits 12:31 - 31:12] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
pub fn eotim(&mut self) -> _EOTIMW
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Bit 11 - 11:11] End of Transmission interrupt mask. A read returns the current mask for UART's EoT interrupt. On a write of 1, the mask of the EoT interrupt is set which means the interrupt state will be reflected in MIS.EOTMIS. A write of 0 clears the mask which means MIS.EOTMIS will not reflect the interrupt.
pub fn oeim(&mut self) -> _OEIMW
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Bit 10 - 10:10] Overrun error interrupt mask. A read returns the current mask for UART's overrun error interrupt. On a write of 1, the mask of the overrun error interrupt is set which means the interrupt state will be reflected in MIS.OEMIS. A write of 0 clears the mask which means MIS.OEMIS will not reflect the interrupt.
pub fn beim(&mut self) -> _BEIMW
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Bit 9 - 9:9] Break error interrupt mask. A read returns the current mask for UART's break error interrupt. On a write of 1, the mask of the overrun error interrupt is set which means the interrupt state will be reflected in MIS.BEMIS. A write of 0 clears the mask which means MIS.BEMIS will not reflect the interrupt.
pub fn peim(&mut self) -> _PEIMW
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Bit 8 - 8:8] Parity error interrupt mask. A read returns the current mask for UART's parity error interrupt. On a write of 1, the mask of the overrun error interrupt is set which means the interrupt state will be reflected in MIS.PEMIS. A write of 0 clears the mask which means MIS.PEMIS will not reflect the interrupt.
pub fn feim(&mut self) -> _FEIMW
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Bit 7 - 7:7] Framing error interrupt mask. A read returns the current mask for UART's framing error interrupt. On a write of 1, the mask of the overrun error interrupt is set which means the interrupt state will be reflected in MIS.FEMIS. A write of 0 clears the mask which means MIS.FEMIS will not reflect the interrupt.
pub fn rtim(&mut self) -> _RTIMW
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Bit 6 - 6:6] Receive timeout interrupt mask. A read returns the current mask for UART's receive timeout interrupt. On a write of 1, the mask of the overrun error interrupt is set which means the interrupt state will be reflected in MIS.RTMIS. A write of 0 clears the mask which means this bitfield will not reflect the interrupt. The raw interrupt for receive timeout RIS.RTRIS cannot be set unless the mask is set (RTIM = 1). This is because the mask acts as an enable for power saving. That is, the same status can be read from MIS.RTMIS and RIS.RTRIS.
pub fn txim(&mut self) -> _TXIMW
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Bit 5 - 5:5] Transmit interrupt mask. A read returns the current mask for UART's transmit interrupt. On a write of 1, the mask of the overrun error interrupt is set which means the interrupt state will be reflected in MIS.TXMIS. A write of 0 clears the mask which means MIS.TXMIS will not reflect the interrupt.
pub fn rxim(&mut self) -> _RXIMW
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Bit 4 - 4:4] Receive interrupt mask. A read returns the current mask for UART's receive interrupt. On a write of 1, the mask of the overrun error interrupt is set which means the interrupt state will be reflected in MIS.RXMIS. A write of 0 clears the mask which means MIS.RXMIS will not reflect the interrupt.
pub fn reserved2(&mut self) -> _RESERVED2W
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Bits 2:3 - 3:2] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
pub fn ctsmim(&mut self) -> _CTSMIMW
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Bit 1 - 1:1] Clear to Send (CTS) modem interrupt mask. A read returns the current mask for UART's clear to send interrupt. On a write of 1, the mask of the overrun error interrupt is set which means the interrupt state will be reflected in MIS.CTSMMIS. A write of 0 clears the mask which means MIS.CTSMMIS will not reflect the interrupt.
pub fn reserved0(&mut self) -> _RESERVED0W
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Bit 0 - 0:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
Auto Trait Implementations
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impl<T> From for T
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