[−][src]Struct cc13x2_cc26x2_hal::ssi0::mis::W
Value to write to the register
Methods
impl W
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pub fn reset_value() -> W
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Reset value of the register
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self
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Writes raw bits to the register
pub fn txmis(&mut self) -> _TXMISW
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Bit 3 - 3:3] Masked interrupt state of transmit FIFO interrupt: This field returns the masked interrupt state of transmit FIFO interrupt which is the AND product of raw interrupt state RIS.TXRIS and the mask setting IMSC.TXIM.
pub fn rxmis(&mut self) -> _RXMISW
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Bit 2 - 2:2] Masked interrupt state of receive FIFO interrupt: This field returns the masked interrupt state of receive FIFO interrupt which is the AND product of raw interrupt state RIS.RXRIS and the mask setting IMSC.RXIM.
pub fn rtmis(&mut self) -> _RTMISW
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Bit 1 - 1:1] Masked interrupt state of receive timeout interrupt: This field returns the masked interrupt state of receive timeout interrupt which is the AND product of raw interrupt state RIS.RTRIS and the mask setting IMSC.RTIM.
pub fn rormis(&mut self) -> _RORMISW
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Bit 0 - 0:0] Masked interrupt state of receive overrun interrupt: This field returns the masked interrupt state of receive overrun interrupt which is the AND product of raw interrupt state RIS.RORRIS and the mask setting IMSC.RORIM.
Auto Trait Implementations
Blanket Implementations
impl<T> From for T
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impl<T, U> TryFrom for T where
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impl<T, U> TryInto for T where
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U: TryFrom<T>,
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impl<T, U> Into for T where
U: From<T>,
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U: From<T>,
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