[−][src]Struct cc13x2_cc26x2_hal::gpt3::tbmr::R
Value read from the register
Methods
impl R
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pub fn bits(&self) -> u32
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Value of the register as raw bits
pub fn reserved16(&self) -> RESERVED16R
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Bits 16:31 - 31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
pub fn tcact(&self) -> TCACTR
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Bits 13:15 - 15:13] Timer Compare Action Select
pub fn tbcintd(&self) -> TBCINTDR
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Bit 12 - 12:12] One-Shot/Periodic Interrupt Mode
pub fn tbplo(&self) -> TBPLOR
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Bit 11 - 11:11] GPTM Timer B PWM Legacy Operation 0 Legacy operation with CCP pin driven Low when the TBILR register is reloaded after the timer reaches 0. 1 CCP is driven High when the TBILR register is reloaded after the timer reaches 0. This bit is only valid in PWM mode.
pub fn tbmrsu(&self) -> TBMRSUR
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Bit 10 - 10:10] Timer B Match Register Update mode This bit defines when the TBMATCHR and TBPR registers are updated If the timer is disabled (CTL.TBEN is clear) when this bit is set, TBMATCHR and TBPR are updated when the timer is enabled. If the timer is stalled (CTL.TBSTALL is set) when this bit is set, TBMATCHR and TBPR are updated according to the configuration of this bit.
pub fn tbpwmie(&self) -> TBPWMIER
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Bit 9 - 9:9] GPTM Timer B PWM Interrupt Enable This bit enables interrupts in PWM mode on rising, falling, or both edges of the CCP output, as defined by the CTL.TBEVENT In addition, when this bit is set and a capture event occurs, Timer A automatically generates triggers to the DMA if the trigger capability is enabled by setting the CTL.TBOTE bit and the DMAEV.CBEDMAEN bit respectively. 0 Capture event interrupt is disabled. 1 Capture event interrupt is enabled. This bit is only valid in PWM mode.
pub fn tbild(&self) -> TBILDR
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Bit 8 - 8:8] GPT Timer B PWM Interval Load Write
pub fn tbsnaps(&self) -> TBSNAPSR
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Bit 7 - 7:7] GPT Timer B Snap-Shot Mode
pub fn tbwot(&self) -> TBWOTR
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Bit 6 - 6:6] GPT Timer B Wait-On-Trigger
pub fn tbmie(&self) -> TBMIER
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Bit 5 - 5:5] GPT Timer B Match Interrupt Enable.
pub fn tbcdir(&self) -> TBCDIRR
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Bit 4 - 4:4] GPT Timer B Count Direction
pub fn tbams(&self) -> TBAMSR
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Bit 3 - 3:3] GPT Timer B Alternate Mode Note: To enable PWM mode, you must also clear TBCM bit and configure TBMR field to 0x2.
pub fn tbcm(&self) -> TBCMR
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Bit 2 - 2:2] GPT Timer B Capture Mode
pub fn tbmr(&self) -> TBMRR
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Bits 0:1 - 1:0] GPT Timer B Mode 0x0 Reserved 0x1 One-Shot Timer mode 0x2 Periodic Timer mode 0x3 Capture mode The Timer mode is based on the timer configuration defined by bits 2:0 in the CFG register
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