Struct cc13x2_cc26x2_hal::crypto::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {
    pub dmach0ctl: DMACH0CTL,
    pub dmach0extaddr: DMACH0EXTADDR,
    pub dmach0len: DMACH0LEN,
    pub dmastat: DMASTAT,
    pub dmaswreset: DMASWRESET,
    pub dmach1ctl: DMACH1CTL,
    pub dmach1extaddr: DMACH1EXTADDR,
    pub dmach1len: DMACH1LEN,
    pub dmabuscfg: DMABUSCFG,
    pub dmaporterr: DMAPORTERR,
    pub dmahwver: DMAHWVER,
    pub keywritearea: KEYWRITEAREA,
    pub keywrittenarea: KEYWRITTENAREA,
    pub keysize: KEYSIZE,
    pub keyreadarea: KEYREADAREA,
    pub aeskey2: AESKEY2,
    pub aeskey3: AESKEY3,
    pub aesiv: AESIV,
    pub aesctl: AESCTL,
    pub aesdatalen0: AESDATALEN0,
    pub aesdatalen1: AESDATALEN1,
    pub aesauthlen: AESAUTHLEN,
    pub aesdataout0: AESDATAOUT0,
    pub aesdataout1: AESDATAOUT1,
    pub aesdataout2: AESDATAOUT2,
    pub aesdataout3: AESDATAOUT3,
    pub aestagout: AESTAGOUT,
    pub hashdatain1: HASHDATAIN1,
    pub hashdatain2: HASHDATAIN2,
    pub hashdatain3: HASHDATAIN3,
    pub hashdatain4: HASHDATAIN4,
    pub hashdatain5: HASHDATAIN5,
    pub hashdatain6: HASHDATAIN6,
    pub hashdatain7: HASHDATAIN7,
    pub hashdatain8: HASHDATAIN8,
    pub hashdatain9: HASHDATAIN9,
    pub hashdatain10: HASHDATAIN10,
    pub hashdatain11: HASHDATAIN11,
    pub hashdatain12: HASHDATAIN12,
    pub hashdatain13: HASHDATAIN13,
    pub hashdatain14: HASHDATAIN14,
    pub hashdatain15: HASHDATAIN15,
    pub hashdatain16: HASHDATAIN16,
    pub hashdatain17: HASHDATAIN17,
    pub hashdatain18: HASHDATAIN18,
    pub hashdatain19: HASHDATAIN19,
    pub hashdatain20: HASHDATAIN20,
    pub hashdatain21: HASHDATAIN21,
    pub hashdatain22: HASHDATAIN22,
    pub hashdatain23: HASHDATAIN23,
    pub hashdatain24: HASHDATAIN24,
    pub hashdatain25: HASHDATAIN25,
    pub hashdatain26: HASHDATAIN26,
    pub hashdatain27: HASHDATAIN27,
    pub hashdatain28: HASHDATAIN28,
    pub hashdatain29: HASHDATAIN29,
    pub hashdatain30: HASHDATAIN30,
    pub hashdatain31: HASHDATAIN31,
    pub hashiobufctrl: HASHIOBUFCTRL,
    pub hashmode: HASHMODE,
    pub hashinlenl: HASHINLENL,
    pub hashinlenh: HASHINLENH,
    pub hashdigesta: HASHDIGESTA,
    pub hashdigestb: HASHDIGESTB,
    pub hashdigestc: HASHDIGESTC,
    pub hashdigestd: HASHDIGESTD,
    pub hashdigeste: HASHDIGESTE,
    pub hashdigestf: HASHDIGESTF,
    pub hashdigestg: HASHDIGESTG,
    pub hashdigesth: HASHDIGESTH,
    pub hashdigesti: HASHDIGESTI,
    pub hashdigestj: HASHDIGESTJ,
    pub hashdigestk: HASHDIGESTK,
    pub hashdigestl: HASHDIGESTL,
    pub hashdigestm: HASHDIGESTM,
    pub hashdigestn: HASHDIGESTN,
    pub hashdigesto: HASHDIGESTO,
    pub hashdigestp: HASHDIGESTP,
    pub algsel: ALGSEL,
    pub dmaprotctl: DMAPROTCTL,
    pub swreset: SWRESET,
    pub irqtype: IRQTYPE,
    pub irqen: IRQEN,
    pub irqclr: IRQCLR,
    pub irqset: IRQSET,
    pub irqstat: IRQSTAT,
    pub hwver: HWVER,
    // some fields omitted
}

Register block

Fields

dmach0ctl: DMACH0CTL

0x00 - Channel 0 Control This register is used for channel enabling and priority selection. When a channel is disabled, it becomes inactive only when all ongoing requests are finished.

dmach0extaddr: DMACH0EXTADDR

0x04 - Channel 0 External Address

dmach0len: DMACH0LEN

0x0c - Channel 0 DMA Length

dmastat: DMASTAT

0x18 - DMAC Status This register provides the actual state of each DMA channel. It also reports port errors in case these were received by the master interface module during the data transfer.

dmaswreset: DMASWRESET

0x1c - DMAC Software Reset Software reset is used to reset the DMAC to stop all transfers and clears the port error status register. After the software reset is performed, all the channels are disabled and no new requests are performed by the channels. The DMAC waits for the existing (active) requests to finish and accordingly sets the DMASTAT.

dmach1ctl: DMACH1CTL

0x20 - Channel 1 Control This register is used for channel enabling and priority selection. When a channel is disabled, it becomes inactive only when all ongoing requests are finished.

dmach1extaddr: DMACH1EXTADDR

0x24 - Channel 1 External Address

dmach1len: DMACH1LEN

0x2c - Channel 1 DMA Length

dmabuscfg: DMABUSCFG

0x78 - DMAC Master Run-time Parameters This register defines all the run-time parameters for the AHB master interface port. These parameters are required for the proper functioning of the EIP-101m AHB master adapter.

dmaporterr: DMAPORTERR

0x7c - DMAC Port Error Raw Status This register provides the actual status of individual port errors. It also indicates which channel is serviced by an external AHB port (which is frozen by a port error). A port error aborts operations on all serviced channels (channel enable bit is forced to 0) and prevents further transfers via that port until the error is cleared by writing to the DMASWRESET register.

dmahwver: DMAHWVER

0xfc - DMAC Version This register contains an indication (or signature) of the EIP type of this DMAC, as well as the hardware version/patch numbers.

keywritearea: KEYWRITEAREA

0x400 - Key Store Write Area This register defines where the keys should be written in the key store RAM. After writing this register, the key store module is ready to receive the keys through a DMA operation. In case the key data transfer triggered an error in the key store, the error will be available in the interrupt status register after the DMA is finished. The key store write-error is asserted when the programmed/selected area is not completely written. This error is also asserted when the DMA operation writes to ram areas that are not selected. The key store RAM is divided into 8 areas of 128 bits. 192-bit keys written in the key store RAM should start on boundaries of 256 bits. This means that writing a 192-bit key to the key store RAM must be done by writing 256 bits of data with the 64 most-significant bits set to 0. These bits are ignored by the AES engine.

keywrittenarea: KEYWRITTENAREA

0x404 - Key Store Written Area This register shows which areas of the key store RAM contain valid written keys. When a new key needs to be written to the key store, on a location that is already occupied by a valid key, this key area must be cleared first. This can be done by writing this register before the new key is written to the key store memory. Attempting to write to a key area that already contains a valid key is not allowed and results in an error.

keysize: KEYSIZE

0x408 - Key Store Size This register defines the size of the keys that are written with DMA. This register should be configured before writing to the KEY_STORE_WRITE_AREA register.

keyreadarea: KEYREADAREA

0x40c - Key Store Read Area This register selects the key store RAM area from where the key needs to be read that will be used for an AES operation. The operation directly starts after writing this register. When the operation is finished, the status of the key store read operation is available in the interrupt status register. Key store read error is asserted when a RAM area is selected which does not contain valid written key.

aeskey2: AESKEY2

0x500 - AES_KEY2_0 / AES_GHASH_H_IN_0 Second Key / GHASH Key (internal, but clearable) The following registers are not accessible through the host for reading and writing. They are used to store internally calculated key information and intermediate results. However, when the host performs a write to the any of the respective AES_KEY2_n or AES_KEY3_n addresses, respectively the whole 128-bit AES_KEY2_n or AES_KEY3_n register is cleared to 0s. The AES_GHASH_H_IN_n registers (required for GHASH, which is part of GCM) are mapped to the AES_KEY2_n registers. The (intermediate) authentication result for GCM and CCM is stored in the AES_KEY3_n register.

aeskey3: AESKEY3

0x510 - AES_KEY3_0 / AES_KEY2_4 Third Key / Second Key (internal, but clearable) The following registers are not accessible through the host for reading and writing. They are used to store internally calculated key information and intermediate results. However, when the host performs a write to the any of the respective AES_KEY2_n or AES_KEY3_n addresses, respectively the whole 128-bit AES_KEY2_n or AES_KEY3_n register is cleared to 0s. The AES_GHASH_H_IN_n registers (required for GHASH, which is part of GCM) are mapped to the AES_KEY2_n registers. The (intermediate) authentication result for GCM and CCM is stored in the AES_KEY3_n register.

aesiv: AESIV

0x540 - AES initialization vector registers These registers are used to provide and read the IV from the AES engine.

aesctl: AESCTL

0x550 - AES Control AES input/output buffer control and mode register This register specifies the AES mode of operation for the EIP-120t. Electronic codebook (ECB) mode is automatically selected if bits [28:5] of this register are all 0.

aesdatalen0: AESDATALEN0

0x554 - AES Crypto Length 0 (LSW) These registers are used to write the Length values to the EIP-120t. While processing, the length values decrement to 0. If both lengths are 0, the data stream is finished and a new context is requested. For basic AES modes (ECB, CBC, and CTR), a crypto length of 0 can be written if multiple streams need to be processed with the same key. Writing 0 length results in continued data requests until a new context is written. For the other modes (CBC-MAC, GCM, and CCM) no (new) data requests are done if the length decrements to or equals 0. It is advised to write a new length per packet. If the length registers decrement to 0, no new data is processed until a new context or length value is written. When writing a new mode without writing the length registers, the length register values from the previous context is reused.

aesdatalen1: AESDATALEN1

0x558 - AES Crypto Length 1 (MSW) These registers are used to write the Length values to the EIP-120t. While processing, the length values decrement to 0. If both lengths are 0, the data stream is finished and a new context is requested. For basic AES modes (ECB, CBC, and CTR), a crypto length of 0 can be written if multiple streams need to be processed with the same key. Writing 0 length results in continued data requests until a new context is written. For the other modes (CBC-MAC, GCM and CCM) no (new) data requests are done if the length decrements to or equals 0. It is advised to write a new length per packet. If the length registers decrement to 0, no new data is processed until a new context or length value is written. When writing a new mode without writing the length registers, the length register values from the previous context is reused.

aesauthlen: AESAUTHLEN

0x55c - AES Authentication Length

aesdataout0: AESDATAOUT0

0x560 - Data Input/Output

aesdataout1: AESDATAOUT1

0x564 - Data Input/Output

aesdataout2: AESDATAOUT2

0x568 - Data Input/Output

aesdataout3: AESDATAOUT3

0x56c - Data Input/Output

aestagout: AESTAGOUT

0x570 - AES Tag Out 0 The tag registers can be accessed via DMA or directly with host reads. These registers buffer the TAG from the EIP-120t. The registers are shared with the intermediate authentication result registers, but cannot be read until the processing is finished. While processing, a read from these registers returns 0s. If an operation does not return a TAG, reading from these registers returns an IV. If an operation returns a TAG plus an IV and both need to be read by the host, the host must first read the TAG followed by the IV. Reading these in reverse order will return the IV twice.

hashdatain1: HASHDATAIN1

0x604 - HASH Data Input 1 The data input registers should be used to provide input data to the hash module through the slave interface.

hashdatain2: HASHDATAIN2

0x608 - HASH Data Input 2 The data input registers should be used to provide input data to the hash module through the slave interface.

hashdatain3: HASHDATAIN3

0x60c - HASH Data Input 3 The data input registers should be used to provide input data to the hash module through the slave interface.

hashdatain4: HASHDATAIN4

0x610 - HASH Data Input 4 The data input registers should be used to provide input data to the hash module through the slave interface.

hashdatain5: HASHDATAIN5

0x614 - HASH Data Input 5 The data input registers should be used to provide input data to the hash module through the slave interface.

hashdatain6: HASHDATAIN6

0x618 - HASH Data Input 6 The data input registers should be used to provide input data to the hash module through the slave interface.

hashdatain7: HASHDATAIN7

0x61c - HASH Data Input 7 The data input registers should be used to provide input data to the hash module through the slave interface.

hashdatain8: HASHDATAIN8

0x620 - HASH Data Input 8 The data input registers should be used to provide input data to the hash module through the slave interface.

hashdatain9: HASHDATAIN9

0x624 - HASH Data Input 9 The data input registers should be used to provide input data to the hash module through the slave interface.

hashdatain10: HASHDATAIN10

0x628 - HASH Data Input 10 The data input registers should be used to provide input data to the hash module through the slave interface.

hashdatain11: HASHDATAIN11

0x62c - HASH Data Input 11 The data input registers should be used to provide input data to the hash module through the slave interface.

hashdatain12: HASHDATAIN12

0x630 - HASH Data Input 12 The data input registers should be used to provide input data to the hash module through the slave interface.

hashdatain13: HASHDATAIN13

0x634 - HASH Data Input 13 The data input registers should be used to provide input data to the hash module through the slave interface.

hashdatain14: HASHDATAIN14

0x638 - HASH Data Input 14 The data input registers should be used to provide input data to the hash module through the slave interface.

hashdatain15: HASHDATAIN15

0x63c - HASH Data Input 15 The data input registers should be used to provide input data to the hash module through the slave interface.

hashdatain16: HASHDATAIN16

0x640 - HASH Data Input 16 The data input registers should be used to provide input data to the hash module through the slave interface.

hashdatain17: HASHDATAIN17

0x644 - HASH Data Input 17 The data input registers should be used to provide input data to the hash module through the slave interface.

hashdatain18: HASHDATAIN18

0x648 - HASH Data Input 18 The data input registers should be used to provide input data to the hash module through the slave interface.

hashdatain19: HASHDATAIN19

0x64c - HASH Data Input 19 The data input registers should be used to provide input data to the hash module through the slave interface.

hashdatain20: HASHDATAIN20

0x650 - HASH Data Input 20 The data input registers should be used to provide input data to the hash module through the slave interface.

hashdatain21: HASHDATAIN21

0x654 - HASH Data Input 21 The data input registers should be used to provide input data to the hash module through the slave interface.

hashdatain22: HASHDATAIN22

0x658 - HASH Data Input 22 The data input registers should be used to provide input data to the hash module through the slave interface.

hashdatain23: HASHDATAIN23

0x65c - HASH Data Input 23 The data input registers should be used to provide input data to the hash module through the slave interface.

hashdatain24: HASHDATAIN24

0x660 - HASH Data Input 24 The data input registers should be used to provide input data to the hash module through the slave interface.

hashdatain25: HASHDATAIN25

0x664 - HASH Data Input 25 The data input registers should be used to provide input data to the hash module through the slave interface.

hashdatain26: HASHDATAIN26

0x668 - HASH Data Input 26 The data input registers should be used to provide input data to the hash module through the slave interface.

hashdatain27: HASHDATAIN27

0x66c - HASH Data Input 27 The data input registers should be used to provide input data to the hash module through the slave interface.

hashdatain28: HASHDATAIN28

0x670 - HASH Data Input 28 The data input registers should be used to provide input data to the hash module through the slave interface.

hashdatain29: HASHDATAIN29

0x674 - HASH Data Input 29 The data input registers should be used to provide input data to the hash module through the slave interface.

hashdatain30: HASHDATAIN30

0x678 - HASH Data Input 30 The data input registers should be used to provide input data to the hash module through the slave interface.

hashdatain31: HASHDATAIN31

0x67c - HASH Data Input 31 The data input registers should be used to provide input data to the hash module through the slave interface.

hashiobufctrl: HASHIOBUFCTRL

0x680 - HASH Input_Output Buffer Control This register pair shares a single address location and contains bits that control and monitor the data flow between the host and the hash engine.

hashmode: HASHMODE

0x684 - HASH Mode

hashinlenl: HASHINLENL

0x688 - HASH Input Length LSB

hashinlenh: HASHINLENH

0x68c - HASH Input Length MSB

hashdigesta: HASHDIGESTA

0x6c0 - HASH Digest A The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations.

hashdigestb: HASHDIGESTB

0x6c4 - HASH Digest B The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations.

hashdigestc: HASHDIGESTC

0x6c8 - HASH Digest C The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations.

hashdigestd: HASHDIGESTD

0x6cc - HASH Digest D The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations.

hashdigeste: HASHDIGESTE

0x6d0 - HASH Digest E The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations.

hashdigestf: HASHDIGESTF

0x6d4 - HASH Digest F The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations.

hashdigestg: HASHDIGESTG

0x6d8 - HASH Digest G The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations.

hashdigesth: HASHDIGESTH

0x6dc - HASH Digest H The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations.

hashdigesti: HASHDIGESTI

0x6e0 - HASH Digest I The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations.

hashdigestj: HASHDIGESTJ

0x6e4 - HASH Digest J The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations.

hashdigestk: HASHDIGESTK

0x6e8 - HASH Digest K The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations.

hashdigestl: HASHDIGESTL

0x6ec - HASH Digest L The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations.

hashdigestm: HASHDIGESTM

0x6f0 - HASH Digest M The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations.

hashdigestn: HASHDIGESTN

0x6f4 - HASH Digest N The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations.

hashdigesto: HASHDIGESTO

0x6f8 - HASH Digest 0 The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations.

hashdigestp: HASHDIGESTP

0x6fc - HASH Digest P The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations.

algsel: ALGSEL

0x700 - Algorithm Select This algorithm selection register configures the internal destination of the DMA controller.

dmaprotctl: DMAPROTCTL

0x704 - DMA Protection Control Master PROT privileged access enable This register enables the second bit (bit [1]) of the AHB HPROT bus of the AHB master interface when a read action of key(s) is performed on the AHB master interface for writing keys into the store module.

swreset: SWRESET

0x740 - Software Reset

irqtype: IRQTYPE

0x780 - Control Interrupt Configuration

irqen: IRQEN

0x784 - Control Interrupt Enable

irqclr: IRQCLR

0x788 - Control Interrupt Clear

irqset: IRQSET

0x78c - Control Interrupt Set

irqstat: IRQSTAT

0x790 - Control Interrupt Status

hwver: HWVER

0x7fc - Hardware Version