[−][src]Module cc13x2_cc26x2_hal::crypto
DMA Crypto Core is a low power low gate count crypto core with DMA capability and local key storage.
Modules
| aesauthlen | AES Authentication Length |
| aesctl | AES Control AES input/output buffer control and mode register This register specifies the AES mode of operation for the EIP-120t. Electronic codebook (ECB) mode is automatically selected if bits [28:5] of this register are all 0. |
| aesdatain0 | AES Data Input_Output 0 The data registers are typically accessed through the DMA and not with host writes and/or reads. However, for debugging purposes the data input/output registers can be accessed via host write and read operations. The registers are used to buffer the input/output data blocks to/from the EIP-120t. Note: The data input buffer (AES_DATA_IN_n) and data output buffer (AES_DATA_OUT_n) are mapped to the same address locations. Writes (both DMA and host) to these addresses load the Input Buffer while reads pull from the Output Buffer. Therefore, for write access, the data input buffer is written; for read access, the data output buffer is read. The data input buffer must be written before starting an operation. The data output buffer contains valid data on completion of an operation. Therefore, any 128-bit data block can be split over multiple 32-bit word transfers; these can be mixed with other host transfers over the external interface. |
| aesdatain1 | AES Data Input_Output 0 The data registers are typically accessed through the DMA and not with host writes and/or reads. However, for debugging purposes the data input/output registers can be accessed via host write and read operations. The registers are used to buffer the input/output data blocks to/from the EIP-120t. Note: The data input buffer (AES_DATA_IN_n) and data output buffer (AES_DATA_OUT_n) are mapped to the same address locations. Writes (both DMA and host) to these addresses load the Input Buffer while reads pull from the Output Buffer. Therefore, for write access, the data input buffer is written; for read access, the data output buffer is read. The data input buffer must be written before starting an operation. The data output buffer contains valid data on completion of an operation. Therefore, any 128-bit data block can be split over multiple 32-bit word transfers; these can be mixed with other host transfers over the external interface. |
| aesdatain2 | AES Data Input_Output 2 The data registers are typically accessed via DMA and not with host writes and/or reads. However, for debugging purposes the Data Input/Output Registers can be accessed via host write and read operations. The registers are used to buffer the input/output data blocks to/from the EIP-120t. Note: The data input buffer (AES_DATA_IN_n) and data output buffer (AES_DATA_OUT_n) are mapped to the same address locations. Writes (both DMA and host) to these addresses load the Input Buffer while reads pull from the Output Buffer. Therefore, for write access, the data input buffer is written; for read access, the data output buffer is read. The data input buffer must be written before starting an operation. The data output buffer contains valid data on completion of an operation. Therefore, any 128-bit data block can be split over multiple 32-bit word transfers; these can be mixed with other host transfers over the external interface. |
| aesdatain3 | AES Data Input_Output 3 The data registers are typically accessed via DMA and not with host writes and/or reads. However, for debugging purposes the Data Input/Output Registers can be accessed via host write and read operations. The registers are used to buffer the input/output data blocks to/from the EIP-120t. Note: The data input buffer (AES_DATA_IN_n) and data output buffer (AES_DATA_OUT_n) are mapped to the same address locations. Writes (both DMA and host) to these addresses load the Input Buffer while reads pull from the Output Buffer. Therefore, for write access, the data input buffer is written; for read access, the data output buffer is read. The data input buffer must be written before starting an operation. The data output buffer contains valid data on completion of an operation. Therefore, any 128-bit data block can be split over multiple 32-bit word transfers; these can be mixed with other host transfers over the external interface. |
| aesdatalen0 | AES Crypto Length 0 (LSW) These registers are used to write the Length values to the EIP-120t. While processing, the length values decrement to 0. If both lengths are 0, the data stream is finished and a new context is requested. For basic AES modes (ECB, CBC, and CTR), a crypto length of 0 can be written if multiple streams need to be processed with the same key. Writing 0 length results in continued data requests until a new context is written. For the other modes (CBC-MAC, GCM, and CCM) no (new) data requests are done if the length decrements to or equals 0. It is advised to write a new length per packet. If the length registers decrement to 0, no new data is processed until a new context or length value is written. When writing a new mode without writing the length registers, the length register values from the previous context is reused. |
| aesdatalen1 | AES Crypto Length 1 (MSW) These registers are used to write the Length values to the EIP-120t. While processing, the length values decrement to 0. If both lengths are 0, the data stream is finished and a new context is requested. For basic AES modes (ECB, CBC, and CTR), a crypto length of 0 can be written if multiple streams need to be processed with the same key. Writing 0 length results in continued data requests until a new context is written. For the other modes (CBC-MAC, GCM and CCM) no (new) data requests are done if the length decrements to or equals 0. It is advised to write a new length per packet. If the length registers decrement to 0, no new data is processed until a new context or length value is written. When writing a new mode without writing the length registers, the length register values from the previous context is reused. |
| aesdataout0 | Data Input/Output |
| aesdataout1 | Data Input/Output |
| aesdataout2 | Data Input/Output |
| aesdataout3 | Data Input/Output |
| aesiv | AES initialization vector registers These registers are used to provide and read the IV from the AES engine. |
| aeskey2 | AES_KEY2_0 / AES_GHASH_H_IN_0 Second Key / GHASH Key (internal, but clearable) The following registers are not accessible through the host for reading and writing. They are used to store internally calculated key information and intermediate results. However, when the host performs a write to the any of the respective AES_KEY2_n or AES_KEY3_n addresses, respectively the whole 128-bit AES_KEY2_n or AES_KEY3_n register is cleared to 0s. The AES_GHASH_H_IN_n registers (required for GHASH, which is part of GCM) are mapped to the AES_KEY2_n registers. The (intermediate) authentication result for GCM and CCM is stored in the AES_KEY3_n register. |
| aeskey3 | AES_KEY3_0 / AES_KEY2_4 Third Key / Second Key (internal, but clearable) The following registers are not accessible through the host for reading and writing. They are used to store internally calculated key information and intermediate results. However, when the host performs a write to the any of the respective AES_KEY2_n or AES_KEY3_n addresses, respectively the whole 128-bit AES_KEY2_n or AES_KEY3_n register is cleared to 0s. The AES_GHASH_H_IN_n registers (required for GHASH, which is part of GCM) are mapped to the AES_KEY2_n registers. The (intermediate) authentication result for GCM and CCM is stored in the AES_KEY3_n register. |
| aestagout | AES Tag Out 0 The tag registers can be accessed via DMA or directly with host reads. These registers buffer the TAG from the EIP-120t. The registers are shared with the intermediate authentication result registers, but cannot be read until the processing is finished. While processing, a read from these registers returns 0s. If an operation does not return a TAG, reading from these registers returns an IV. If an operation returns a TAG plus an IV and both need to be read by the host, the host must first read the TAG followed by the IV. Reading these in reverse order will return the IV twice. |
| algsel | Algorithm Select This algorithm selection register configures the internal destination of the DMA controller. |
| dmabuscfg | DMAC Master Run-time Parameters This register defines all the run-time parameters for the AHB master interface port. These parameters are required for the proper functioning of the EIP-101m AHB master adapter. |
| dmach0ctl | Channel 0 Control This register is used for channel enabling and priority selection. When a channel is disabled, it becomes inactive only when all ongoing requests are finished. |
| dmach0len | Channel 0 DMA Length |
| dmach0extaddr | Channel 0 External Address |
| dmach1ctl | Channel 1 Control This register is used for channel enabling and priority selection. When a channel is disabled, it becomes inactive only when all ongoing requests are finished. |
| dmach1extaddr | Channel 1 External Address |
| dmach1len | Channel 1 DMA Length |
| dmahwver | DMAC Version This register contains an indication (or signature) of the EIP type of this DMAC, as well as the hardware version/patch numbers. |
| dmaporterr | DMAC Port Error Raw Status This register provides the actual status of individual port errors. It also indicates which channel is serviced by an external AHB port (which is frozen by a port error). A port error aborts operations on all serviced channels (channel enable bit is forced to 0) and prevents further transfers via that port until the error is cleared by writing to the DMASWRESET register. |
| dmaprotctl | DMA Protection Control Master PROT privileged access enable This register enables the second bit (bit [1]) of the AHB HPROT bus of the AHB master interface when a read action of key(s) is performed on the AHB master interface for writing keys into the store module. |
| dmastat | DMAC Status This register provides the actual state of each DMA channel. It also reports port errors in case these were received by the master interface module during the data transfer. |
| dmaswreset | DMAC Software Reset Software reset is used to reset the DMAC to stop all transfers and clears the port error status register. After the software reset is performed, all the channels are disabled and no new requests are performed by the channels. The DMAC waits for the existing (active) requests to finish and accordingly sets the DMASTAT. |
| hashdatain1 | HASH Data Input 1 The data input registers should be used to provide input data to the hash module through the slave interface. |
| hashdatain2 | HASH Data Input 2 The data input registers should be used to provide input data to the hash module through the slave interface. |
| hashdatain3 | HASH Data Input 3 The data input registers should be used to provide input data to the hash module through the slave interface. |
| hashdatain4 | HASH Data Input 4 The data input registers should be used to provide input data to the hash module through the slave interface. |
| hashdatain5 | HASH Data Input 5 The data input registers should be used to provide input data to the hash module through the slave interface. |
| hashdatain6 | HASH Data Input 6 The data input registers should be used to provide input data to the hash module through the slave interface. |
| hashdatain7 | HASH Data Input 7 The data input registers should be used to provide input data to the hash module through the slave interface. |
| hashdatain8 | HASH Data Input 8 The data input registers should be used to provide input data to the hash module through the slave interface. |
| hashdatain9 | HASH Data Input 9 The data input registers should be used to provide input data to the hash module through the slave interface. |
| hashdatain10 | HASH Data Input 10 The data input registers should be used to provide input data to the hash module through the slave interface. |
| hashdatain11 | HASH Data Input 11 The data input registers should be used to provide input data to the hash module through the slave interface. |
| hashdatain12 | HASH Data Input 12 The data input registers should be used to provide input data to the hash module through the slave interface. |
| hashdatain13 | HASH Data Input 13 The data input registers should be used to provide input data to the hash module through the slave interface. |
| hashdatain14 | HASH Data Input 14 The data input registers should be used to provide input data to the hash module through the slave interface. |
| hashdatain15 | HASH Data Input 15 The data input registers should be used to provide input data to the hash module through the slave interface. |
| hashdatain16 | HASH Data Input 16 The data input registers should be used to provide input data to the hash module through the slave interface. |
| hashdatain17 | HASH Data Input 17 The data input registers should be used to provide input data to the hash module through the slave interface. |
| hashdatain18 | HASH Data Input 18 The data input registers should be used to provide input data to the hash module through the slave interface. |
| hashdatain19 | HASH Data Input 19 The data input registers should be used to provide input data to the hash module through the slave interface. |
| hashdatain20 | HASH Data Input 20 The data input registers should be used to provide input data to the hash module through the slave interface. |
| hashdatain21 | HASH Data Input 21 The data input registers should be used to provide input data to the hash module through the slave interface. |
| hashdatain22 | HASH Data Input 22 The data input registers should be used to provide input data to the hash module through the slave interface. |
| hashdatain23 | HASH Data Input 23 The data input registers should be used to provide input data to the hash module through the slave interface. |
| hashdatain24 | HASH Data Input 24 The data input registers should be used to provide input data to the hash module through the slave interface. |
| hashdatain25 | HASH Data Input 25 The data input registers should be used to provide input data to the hash module through the slave interface. |
| hashdatain26 | HASH Data Input 26 The data input registers should be used to provide input data to the hash module through the slave interface. |
| hashdatain27 | HASH Data Input 27 The data input registers should be used to provide input data to the hash module through the slave interface. |
| hashdatain28 | HASH Data Input 28 The data input registers should be used to provide input data to the hash module through the slave interface. |
| hashdatain29 | HASH Data Input 29 The data input registers should be used to provide input data to the hash module through the slave interface. |
| hashdatain30 | HASH Data Input 30 The data input registers should be used to provide input data to the hash module through the slave interface. |
| hashdatain31 | HASH Data Input 31 The data input registers should be used to provide input data to the hash module through the slave interface. |
| hashdigesta | HASH Digest A The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations. |
| hashdigestb | HASH Digest B The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations. |
| hashdigestc | HASH Digest C The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations. |
| hashdigestd | HASH Digest D The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations. |
| hashdigeste | HASH Digest E The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations. |
| hashdigestf | HASH Digest F The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations. |
| hashdigestg | HASH Digest G The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations. |
| hashdigesth | HASH Digest H The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations. |
| hashdigesti | HASH Digest I The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations. |
| hashdigestj | HASH Digest J The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations. |
| hashdigestk | HASH Digest K The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations. |
| hashdigestl | HASH Digest L The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations. |
| hashdigestm | HASH Digest M The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations. |
| hashdigestn | HASH Digest N The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations. |
| hashdigesto | HASH Digest 0 The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations. |
| hashdigestp | HASH Digest P The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations. |
| hashinlenh | HASH Input Length MSB |
| hashinlenl | HASH Input Length LSB |
| hashiobufctrl | HASH Input_Output Buffer Control This register pair shares a single address location and contains bits that control and monitor the data flow between the host and the hash engine. |
| hashmode | HASH Mode |
| hwver | Hardware Version |
| irqclr | Control Interrupt Clear |
| irqen | Control Interrupt Enable |
| irqset | Control Interrupt Set |
| irqstat | Control Interrupt Status |
| irqtype | Control Interrupt Configuration |
| keyreadarea | Key Store Read Area This register selects the key store RAM area from where the key needs to be read that will be used for an AES operation. The operation directly starts after writing this register. When the operation is finished, the status of the key store read operation is available in the interrupt status register. Key store read error is asserted when a RAM area is selected which does not contain valid written key. |
| keysize | Key Store Size This register defines the size of the keys that are written with DMA. This register should be configured before writing to the KEY_STORE_WRITE_AREA register. |
| keywritearea | Key Store Write Area This register defines where the keys should be written in the key store RAM. After writing this register, the key store module is ready to receive the keys through a DMA operation. In case the key data transfer triggered an error in the key store, the error will be available in the interrupt status register after the DMA is finished. The key store write-error is asserted when the programmed/selected area is not completely written. This error is also asserted when the DMA operation writes to ram areas that are not selected. The key store RAM is divided into 8 areas of 128 bits. 192-bit keys written in the key store RAM should start on boundaries of 256 bits. This means that writing a 192-bit key to the key store RAM must be done by writing 256 bits of data with the 64 most-significant bits set to 0. These bits are ignored by the AES engine. |
| keywrittenarea | Key Store Written Area This register shows which areas of the key store RAM contain valid written keys. When a new key needs to be written to the key store, on a location that is already occupied by a valid key, this key area must be cleared first. This can be done by writing this register before the new key is written to the key store memory. Attempting to write to a key area that already contains a valid key is not allowed and results in an error. |
| swreset | Software Reset |
Structs
| AESAUTHLEN | AES Authentication Length |
| AESCTL | AES Control AES input/output buffer control and mode register This register specifies the AES mode of operation for the EIP-120t. Electronic codebook (ECB) mode is automatically selected if bits [28:5] of this register are all 0. |
| AESDATAIN0 | AES Data Input_Output 0 The data registers are typically accessed through the DMA and not with host writes and/or reads. However, for debugging purposes the data input/output registers can be accessed via host write and read operations. The registers are used to buffer the input/output data blocks to/from the EIP-120t. Note: The data input buffer (AES_DATA_IN_n) and data output buffer (AES_DATA_OUT_n) are mapped to the same address locations. Writes (both DMA and host) to these addresses load the Input Buffer while reads pull from the Output Buffer. Therefore, for write access, the data input buffer is written; for read access, the data output buffer is read. The data input buffer must be written before starting an operation. The data output buffer contains valid data on completion of an operation. Therefore, any 128-bit data block can be split over multiple 32-bit word transfers; these can be mixed with other host transfers over the external interface. |
| AESDATAIN1 | AES Data Input_Output 0 The data registers are typically accessed through the DMA and not with host writes and/or reads. However, for debugging purposes the data input/output registers can be accessed via host write and read operations. The registers are used to buffer the input/output data blocks to/from the EIP-120t. Note: The data input buffer (AES_DATA_IN_n) and data output buffer (AES_DATA_OUT_n) are mapped to the same address locations. Writes (both DMA and host) to these addresses load the Input Buffer while reads pull from the Output Buffer. Therefore, for write access, the data input buffer is written; for read access, the data output buffer is read. The data input buffer must be written before starting an operation. The data output buffer contains valid data on completion of an operation. Therefore, any 128-bit data block can be split over multiple 32-bit word transfers; these can be mixed with other host transfers over the external interface. |
| AESDATAIN2 | AES Data Input_Output 2 The data registers are typically accessed via DMA and not with host writes and/or reads. However, for debugging purposes the Data Input/Output Registers can be accessed via host write and read operations. The registers are used to buffer the input/output data blocks to/from the EIP-120t. Note: The data input buffer (AES_DATA_IN_n) and data output buffer (AES_DATA_OUT_n) are mapped to the same address locations. Writes (both DMA and host) to these addresses load the Input Buffer while reads pull from the Output Buffer. Therefore, for write access, the data input buffer is written; for read access, the data output buffer is read. The data input buffer must be written before starting an operation. The data output buffer contains valid data on completion of an operation. Therefore, any 128-bit data block can be split over multiple 32-bit word transfers; these can be mixed with other host transfers over the external interface. |
| AESDATAIN3 | AES Data Input_Output 3 The data registers are typically accessed via DMA and not with host writes and/or reads. However, for debugging purposes the Data Input/Output Registers can be accessed via host write and read operations. The registers are used to buffer the input/output data blocks to/from the EIP-120t. Note: The data input buffer (AES_DATA_IN_n) and data output buffer (AES_DATA_OUT_n) are mapped to the same address locations. Writes (both DMA and host) to these addresses load the Input Buffer while reads pull from the Output Buffer. Therefore, for write access, the data input buffer is written; for read access, the data output buffer is read. The data input buffer must be written before starting an operation. The data output buffer contains valid data on completion of an operation. Therefore, any 128-bit data block can be split over multiple 32-bit word transfers; these can be mixed with other host transfers over the external interface. |
| AESDATALEN0 | AES Crypto Length 0 (LSW) These registers are used to write the Length values to the EIP-120t. While processing, the length values decrement to 0. If both lengths are 0, the data stream is finished and a new context is requested. For basic AES modes (ECB, CBC, and CTR), a crypto length of 0 can be written if multiple streams need to be processed with the same key. Writing 0 length results in continued data requests until a new context is written. For the other modes (CBC-MAC, GCM, and CCM) no (new) data requests are done if the length decrements to or equals 0. It is advised to write a new length per packet. If the length registers decrement to 0, no new data is processed until a new context or length value is written. When writing a new mode without writing the length registers, the length register values from the previous context is reused. |
| AESDATALEN1 | AES Crypto Length 1 (MSW) These registers are used to write the Length values to the EIP-120t. While processing, the length values decrement to 0. If both lengths are 0, the data stream is finished and a new context is requested. For basic AES modes (ECB, CBC, and CTR), a crypto length of 0 can be written if multiple streams need to be processed with the same key. Writing 0 length results in continued data requests until a new context is written. For the other modes (CBC-MAC, GCM and CCM) no (new) data requests are done if the length decrements to or equals 0. It is advised to write a new length per packet. If the length registers decrement to 0, no new data is processed until a new context or length value is written. When writing a new mode without writing the length registers, the length register values from the previous context is reused. |
| AESDATAOUT0 | Data Input/Output |
| AESDATAOUT1 | Data Input/Output |
| AESDATAOUT2 | Data Input/Output |
| AESDATAOUT3 | Data Input/Output |
| AESIV | AES initialization vector registers These registers are used to provide and read the IV from the AES engine. |
| AESKEY2 | AES_KEY2_0 / AES_GHASH_H_IN_0 Second Key / GHASH Key (internal, but clearable) The following registers are not accessible through the host for reading and writing. They are used to store internally calculated key information and intermediate results. However, when the host performs a write to the any of the respective AES_KEY2_n or AES_KEY3_n addresses, respectively the whole 128-bit AES_KEY2_n or AES_KEY3_n register is cleared to 0s. The AES_GHASH_H_IN_n registers (required for GHASH, which is part of GCM) are mapped to the AES_KEY2_n registers. The (intermediate) authentication result for GCM and CCM is stored in the AES_KEY3_n register. |
| AESKEY3 | AES_KEY3_0 / AES_KEY2_4 Third Key / Second Key (internal, but clearable) The following registers are not accessible through the host for reading and writing. They are used to store internally calculated key information and intermediate results. However, when the host performs a write to the any of the respective AES_KEY2_n or AES_KEY3_n addresses, respectively the whole 128-bit AES_KEY2_n or AES_KEY3_n register is cleared to 0s. The AES_GHASH_H_IN_n registers (required for GHASH, which is part of GCM) are mapped to the AES_KEY2_n registers. The (intermediate) authentication result for GCM and CCM is stored in the AES_KEY3_n register. |
| AESTAGOUT | AES Tag Out 0 The tag registers can be accessed via DMA or directly with host reads. These registers buffer the TAG from the EIP-120t. The registers are shared with the intermediate authentication result registers, but cannot be read until the processing is finished. While processing, a read from these registers returns 0s. If an operation does not return a TAG, reading from these registers returns an IV. If an operation returns a TAG plus an IV and both need to be read by the host, the host must first read the TAG followed by the IV. Reading these in reverse order will return the IV twice. |
| ALGSEL | Algorithm Select This algorithm selection register configures the internal destination of the DMA controller. |
| DMABUSCFG | DMAC Master Run-time Parameters This register defines all the run-time parameters for the AHB master interface port. These parameters are required for the proper functioning of the EIP-101m AHB master adapter. |
| DMACH0CTL | Channel 0 Control This register is used for channel enabling and priority selection. When a channel is disabled, it becomes inactive only when all ongoing requests are finished. |
| DMACH0LEN | Channel 0 DMA Length |
| DMACH0EXTADDR | Channel 0 External Address |
| DMACH1CTL | Channel 1 Control This register is used for channel enabling and priority selection. When a channel is disabled, it becomes inactive only when all ongoing requests are finished. |
| DMACH1EXTADDR | Channel 1 External Address |
| DMACH1LEN | Channel 1 DMA Length |
| DMAHWVER | DMAC Version This register contains an indication (or signature) of the EIP type of this DMAC, as well as the hardware version/patch numbers. |
| DMAPORTERR | DMAC Port Error Raw Status This register provides the actual status of individual port errors. It also indicates which channel is serviced by an external AHB port (which is frozen by a port error). A port error aborts operations on all serviced channels (channel enable bit is forced to 0) and prevents further transfers via that port until the error is cleared by writing to the DMASWRESET register. |
| DMAPROTCTL | DMA Protection Control Master PROT privileged access enable This register enables the second bit (bit [1]) of the AHB HPROT bus of the AHB master interface when a read action of key(s) is performed on the AHB master interface for writing keys into the store module. |
| DMASTAT | DMAC Status This register provides the actual state of each DMA channel. It also reports port errors in case these were received by the master interface module during the data transfer. |
| DMASWRESET | DMAC Software Reset Software reset is used to reset the DMAC to stop all transfers and clears the port error status register. After the software reset is performed, all the channels are disabled and no new requests are performed by the channels. The DMAC waits for the existing (active) requests to finish and accordingly sets the DMASTAT. |
| HASHDATAIN1 | HASH Data Input 1 The data input registers should be used to provide input data to the hash module through the slave interface. |
| HASHDATAIN2 | HASH Data Input 2 The data input registers should be used to provide input data to the hash module through the slave interface. |
| HASHDATAIN3 | HASH Data Input 3 The data input registers should be used to provide input data to the hash module through the slave interface. |
| HASHDATAIN4 | HASH Data Input 4 The data input registers should be used to provide input data to the hash module through the slave interface. |
| HASHDATAIN5 | HASH Data Input 5 The data input registers should be used to provide input data to the hash module through the slave interface. |
| HASHDATAIN6 | HASH Data Input 6 The data input registers should be used to provide input data to the hash module through the slave interface. |
| HASHDATAIN7 | HASH Data Input 7 The data input registers should be used to provide input data to the hash module through the slave interface. |
| HASHDATAIN8 | HASH Data Input 8 The data input registers should be used to provide input data to the hash module through the slave interface. |
| HASHDATAIN9 | HASH Data Input 9 The data input registers should be used to provide input data to the hash module through the slave interface. |
| HASHDATAIN10 | HASH Data Input 10 The data input registers should be used to provide input data to the hash module through the slave interface. |
| HASHDATAIN11 | HASH Data Input 11 The data input registers should be used to provide input data to the hash module through the slave interface. |
| HASHDATAIN12 | HASH Data Input 12 The data input registers should be used to provide input data to the hash module through the slave interface. |
| HASHDATAIN13 | HASH Data Input 13 The data input registers should be used to provide input data to the hash module through the slave interface. |
| HASHDATAIN14 | HASH Data Input 14 The data input registers should be used to provide input data to the hash module through the slave interface. |
| HASHDATAIN15 | HASH Data Input 15 The data input registers should be used to provide input data to the hash module through the slave interface. |
| HASHDATAIN16 | HASH Data Input 16 The data input registers should be used to provide input data to the hash module through the slave interface. |
| HASHDATAIN17 | HASH Data Input 17 The data input registers should be used to provide input data to the hash module through the slave interface. |
| HASHDATAIN18 | HASH Data Input 18 The data input registers should be used to provide input data to the hash module through the slave interface. |
| HASHDATAIN19 | HASH Data Input 19 The data input registers should be used to provide input data to the hash module through the slave interface. |
| HASHDATAIN20 | HASH Data Input 20 The data input registers should be used to provide input data to the hash module through the slave interface. |
| HASHDATAIN21 | HASH Data Input 21 The data input registers should be used to provide input data to the hash module through the slave interface. |
| HASHDATAIN22 | HASH Data Input 22 The data input registers should be used to provide input data to the hash module through the slave interface. |
| HASHDATAIN23 | HASH Data Input 23 The data input registers should be used to provide input data to the hash module through the slave interface. |
| HASHDATAIN24 | HASH Data Input 24 The data input registers should be used to provide input data to the hash module through the slave interface. |
| HASHDATAIN25 | HASH Data Input 25 The data input registers should be used to provide input data to the hash module through the slave interface. |
| HASHDATAIN26 | HASH Data Input 26 The data input registers should be used to provide input data to the hash module through the slave interface. |
| HASHDATAIN27 | HASH Data Input 27 The data input registers should be used to provide input data to the hash module through the slave interface. |
| HASHDATAIN28 | HASH Data Input 28 The data input registers should be used to provide input data to the hash module through the slave interface. |
| HASHDATAIN29 | HASH Data Input 29 The data input registers should be used to provide input data to the hash module through the slave interface. |
| HASHDATAIN30 | HASH Data Input 30 The data input registers should be used to provide input data to the hash module through the slave interface. |
| HASHDATAIN31 | HASH Data Input 31 The data input registers should be used to provide input data to the hash module through the slave interface. |
| HASHDIGESTA | HASH Digest A The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations. |
| HASHDIGESTB | HASH Digest B The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations. |
| HASHDIGESTC | HASH Digest C The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations. |
| HASHDIGESTD | HASH Digest D The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations. |
| HASHDIGESTE | HASH Digest E The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations. |
| HASHDIGESTF | HASH Digest F The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations. |
| HASHDIGESTG | HASH Digest G The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations. |
| HASHDIGESTH | HASH Digest H The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations. |
| HASHDIGESTI | HASH Digest I The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations. |
| HASHDIGESTJ | HASH Digest J The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations. |
| HASHDIGESTK | HASH Digest K The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations. |
| HASHDIGESTL | HASH Digest L The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations. |
| HASHDIGESTM | HASH Digest M The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations. |
| HASHDIGESTN | HASH Digest N The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations. |
| HASHDIGESTO | HASH Digest 0 The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations. |
| HASHDIGESTP | HASH Digest P The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations. |
| HASHINLENH | HASH Input Length MSB |
| HASHINLENL | HASH Input Length LSB |
| HASHIOBUFCTRL | HASH Input_Output Buffer Control This register pair shares a single address location and contains bits that control and monitor the data flow between the host and the hash engine. |
| HASHMODE | HASH Mode |
| HWVER | Hardware Version |
| IRQCLR | Control Interrupt Clear |
| IRQEN | Control Interrupt Enable |
| IRQSET | Control Interrupt Set |
| IRQSTAT | Control Interrupt Status |
| IRQTYPE | Control Interrupt Configuration |
| KEYREADAREA | Key Store Read Area This register selects the key store RAM area from where the key needs to be read that will be used for an AES operation. The operation directly starts after writing this register. When the operation is finished, the status of the key store read operation is available in the interrupt status register. Key store read error is asserted when a RAM area is selected which does not contain valid written key. |
| KEYSIZE | Key Store Size This register defines the size of the keys that are written with DMA. This register should be configured before writing to the KEY_STORE_WRITE_AREA register. |
| KEYWRITEAREA | Key Store Write Area This register defines where the keys should be written in the key store RAM. After writing this register, the key store module is ready to receive the keys through a DMA operation. In case the key data transfer triggered an error in the key store, the error will be available in the interrupt status register after the DMA is finished. The key store write-error is asserted when the programmed/selected area is not completely written. This error is also asserted when the DMA operation writes to ram areas that are not selected. The key store RAM is divided into 8 areas of 128 bits. 192-bit keys written in the key store RAM should start on boundaries of 256 bits. This means that writing a 192-bit key to the key store RAM must be done by writing 256 bits of data with the 64 most-significant bits set to 0. These bits are ignored by the AES engine. |
| KEYWRITTENAREA | Key Store Written Area This register shows which areas of the key store RAM contain valid written keys. When a new key needs to be written to the key store, on a location that is already occupied by a valid key, this key area must be cleared first. This can be done by writing this register before the new key is written to the key store memory. Attempting to write to a key area that already contains a valid key is not allowed and results in an error. |
| RegisterBlock | Register block |
| SWRESET | Software Reset |