Enum capstone_sys::arm_sysreg

#[repr(u32)]
pub enum arm_sysreg {
    ARM_SYSREG_INVALID = 0,
    ARM_SYSREG_SPSR_C = 1,
    ARM_SYSREG_SPSR_X = 2,
    ARM_SYSREG_SPSR_S = 4,
    ARM_SYSREG_SPSR_F = 8,
    ARM_SYSREG_CPSR_C = 16,
    ARM_SYSREG_CPSR_X = 32,
    ARM_SYSREG_CPSR_S = 64,
    ARM_SYSREG_CPSR_F = 128,
    ARM_SYSREG_APSR = 256,
    ARM_SYSREG_APSR_G = 257,
    ARM_SYSREG_APSR_NZCVQ = 258,
    ARM_SYSREG_APSR_NZCVQG = 259,
    ARM_SYSREG_IAPSR = 260,
    ARM_SYSREG_IAPSR_G = 261,
    ARM_SYSREG_IAPSR_NZCVQG = 262,
    ARM_SYSREG_IAPSR_NZCVQ = 263,
    ARM_SYSREG_EAPSR = 264,
    ARM_SYSREG_EAPSR_G = 265,
    ARM_SYSREG_EAPSR_NZCVQG = 266,
    ARM_SYSREG_EAPSR_NZCVQ = 267,
    ARM_SYSREG_XPSR = 268,
    ARM_SYSREG_XPSR_G = 269,
    ARM_SYSREG_XPSR_NZCVQG = 270,
    ARM_SYSREG_XPSR_NZCVQ = 271,
    ARM_SYSREG_IPSR = 272,
    ARM_SYSREG_EPSR = 273,
    ARM_SYSREG_IEPSR = 274,
    ARM_SYSREG_MSP = 275,
    ARM_SYSREG_PSP = 276,
    ARM_SYSREG_PRIMASK = 277,
    ARM_SYSREG_BASEPRI = 278,
    ARM_SYSREG_BASEPRI_MAX = 279,
    ARM_SYSREG_FAULTMASK = 280,
    ARM_SYSREG_CONTROL = 281,
    ARM_SYSREG_MSPLIM = 282,
    ARM_SYSREG_PSPLIM = 283,
    ARM_SYSREG_MSP_NS = 284,
    ARM_SYSREG_PSP_NS = 285,
    ARM_SYSREG_MSPLIM_NS = 286,
    ARM_SYSREG_PSPLIM_NS = 287,
    ARM_SYSREG_PRIMASK_NS = 288,
    ARM_SYSREG_BASEPRI_NS = 289,
    ARM_SYSREG_FAULTMASK_NS = 290,
    ARM_SYSREG_CONTROL_NS = 291,
    ARM_SYSREG_SP_NS = 292,
    ARM_SYSREG_R8_USR = 293,
    ARM_SYSREG_R9_USR = 294,
    ARM_SYSREG_R10_USR = 295,
    ARM_SYSREG_R11_USR = 296,
    ARM_SYSREG_R12_USR = 297,
    ARM_SYSREG_SP_USR = 298,
    ARM_SYSREG_LR_USR = 299,
    ARM_SYSREG_R8_FIQ = 300,
    ARM_SYSREG_R9_FIQ = 301,
    ARM_SYSREG_R10_FIQ = 302,
    ARM_SYSREG_R11_FIQ = 303,
    ARM_SYSREG_R12_FIQ = 304,
    ARM_SYSREG_SP_FIQ = 305,
    ARM_SYSREG_LR_FIQ = 306,
    ARM_SYSREG_LR_IRQ = 307,
    ARM_SYSREG_SP_IRQ = 308,
    ARM_SYSREG_LR_SVC = 309,
    ARM_SYSREG_SP_SVC = 310,
    ARM_SYSREG_LR_ABT = 311,
    ARM_SYSREG_SP_ABT = 312,
    ARM_SYSREG_LR_UND = 313,
    ARM_SYSREG_SP_UND = 314,
    ARM_SYSREG_LR_MON = 315,
    ARM_SYSREG_SP_MON = 316,
    ARM_SYSREG_ELR_HYP = 317,
    ARM_SYSREG_SP_HYP = 318,
    ARM_SYSREG_SPSR_FIQ = 319,
    ARM_SYSREG_SPSR_IRQ = 320,
    ARM_SYSREG_SPSR_SVC = 321,
    ARM_SYSREG_SPSR_ABT = 322,
    ARM_SYSREG_SPSR_UND = 323,
    ARM_SYSREG_SPSR_MON = 324,
    ARM_SYSREG_SPSR_HYP = 325,
}

Variants

ARM_SYSREG_INVALID = 0

Special registers for MSR

ARM_SYSREG_SPSR_C = 1

Special registers for MSR

ARM_SYSREG_SPSR_X = 2

Special registers for MSR

ARM_SYSREG_SPSR_S = 4

Special registers for MSR

ARM_SYSREG_SPSR_F = 8

Special registers for MSR

ARM_SYSREG_CPSR_C = 16

Special registers for MSR

ARM_SYSREG_CPSR_X = 32

Special registers for MSR

ARM_SYSREG_CPSR_S = 64

Special registers for MSR

ARM_SYSREG_CPSR_F = 128

Special registers for MSR

ARM_SYSREG_APSR = 256

Special registers for MSR

ARM_SYSREG_APSR_G = 257

Special registers for MSR

ARM_SYSREG_APSR_NZCVQ = 258

Special registers for MSR

ARM_SYSREG_APSR_NZCVQG = 259

Special registers for MSR

ARM_SYSREG_IAPSR = 260

Special registers for MSR

ARM_SYSREG_IAPSR_G = 261

Special registers for MSR

ARM_SYSREG_IAPSR_NZCVQG = 262

Special registers for MSR

ARM_SYSREG_IAPSR_NZCVQ = 263

Special registers for MSR

ARM_SYSREG_EAPSR = 264

Special registers for MSR

ARM_SYSREG_EAPSR_G = 265

Special registers for MSR

ARM_SYSREG_EAPSR_NZCVQG = 266

Special registers for MSR

ARM_SYSREG_EAPSR_NZCVQ = 267

Special registers for MSR

ARM_SYSREG_XPSR = 268

Special registers for MSR

ARM_SYSREG_XPSR_G = 269

Special registers for MSR

ARM_SYSREG_XPSR_NZCVQG = 270

Special registers for MSR

ARM_SYSREG_XPSR_NZCVQ = 271

Special registers for MSR

ARM_SYSREG_IPSR = 272

Special registers for MSR

ARM_SYSREG_EPSR = 273

Special registers for MSR

ARM_SYSREG_IEPSR = 274

Special registers for MSR

ARM_SYSREG_MSP = 275

Special registers for MSR

ARM_SYSREG_PSP = 276

Special registers for MSR

ARM_SYSREG_PRIMASK = 277

Special registers for MSR

ARM_SYSREG_BASEPRI = 278

Special registers for MSR

ARM_SYSREG_BASEPRI_MAX = 279

Special registers for MSR

ARM_SYSREG_FAULTMASK = 280

Special registers for MSR

ARM_SYSREG_CONTROL = 281

Special registers for MSR

ARM_SYSREG_MSPLIM = 282

Special registers for MSR

ARM_SYSREG_PSPLIM = 283

Special registers for MSR

ARM_SYSREG_MSP_NS = 284

Special registers for MSR

ARM_SYSREG_PSP_NS = 285

Special registers for MSR

ARM_SYSREG_MSPLIM_NS = 286

Special registers for MSR

ARM_SYSREG_PSPLIM_NS = 287

Special registers for MSR

ARM_SYSREG_PRIMASK_NS = 288

Special registers for MSR

ARM_SYSREG_BASEPRI_NS = 289

Special registers for MSR

ARM_SYSREG_FAULTMASK_NS = 290

Special registers for MSR

ARM_SYSREG_CONTROL_NS = 291

Special registers for MSR

ARM_SYSREG_SP_NS = 292

Special registers for MSR

ARM_SYSREG_R8_USR = 293

Special registers for MSR

ARM_SYSREG_R9_USR = 294

Special registers for MSR

ARM_SYSREG_R10_USR = 295

Special registers for MSR

ARM_SYSREG_R11_USR = 296

Special registers for MSR

ARM_SYSREG_R12_USR = 297

Special registers for MSR

ARM_SYSREG_SP_USR = 298

Special registers for MSR

ARM_SYSREG_LR_USR = 299

Special registers for MSR

ARM_SYSREG_R8_FIQ = 300

Special registers for MSR

ARM_SYSREG_R9_FIQ = 301

Special registers for MSR

ARM_SYSREG_R10_FIQ = 302

Special registers for MSR

ARM_SYSREG_R11_FIQ = 303

Special registers for MSR

ARM_SYSREG_R12_FIQ = 304

Special registers for MSR

ARM_SYSREG_SP_FIQ = 305

Special registers for MSR

ARM_SYSREG_LR_FIQ = 306

Special registers for MSR

ARM_SYSREG_LR_IRQ = 307

Special registers for MSR

ARM_SYSREG_SP_IRQ = 308

Special registers for MSR

ARM_SYSREG_LR_SVC = 309

Special registers for MSR

ARM_SYSREG_SP_SVC = 310

Special registers for MSR

ARM_SYSREG_LR_ABT = 311

Special registers for MSR

ARM_SYSREG_SP_ABT = 312

Special registers for MSR

ARM_SYSREG_LR_UND = 313

Special registers for MSR

ARM_SYSREG_SP_UND = 314

Special registers for MSR

ARM_SYSREG_LR_MON = 315

Special registers for MSR

ARM_SYSREG_SP_MON = 316

Special registers for MSR

ARM_SYSREG_ELR_HYP = 317

Special registers for MSR

ARM_SYSREG_SP_HYP = 318

Special registers for MSR

ARM_SYSREG_SPSR_FIQ = 319

Special registers for MSR

ARM_SYSREG_SPSR_IRQ = 320

Special registers for MSR

ARM_SYSREG_SPSR_SVC = 321

Special registers for MSR

ARM_SYSREG_SPSR_ABT = 322

Special registers for MSR

ARM_SYSREG_SPSR_UND = 323

Special registers for MSR

ARM_SYSREG_SPSR_MON = 324

Special registers for MSR

ARM_SYSREG_SPSR_HYP = 325

Special registers for MSR

Trait Implementations

impl Clone for arm_sysreg

fn clone(&self) -> arm_sysreg

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for arm_sysreg

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Hash for arm_sysreg

fn hash<__H: Hasher>(&self, state: &mut __H)

Feeds this value into the given Hasher.

fn hash_slice<H>(data: &[Self], state: &mut H)

where H: Hasher, Self: Sized,

Feeds a slice of this type into the given Hasher.

impl PartialEq for arm_sysreg

fn eq(&self, other: &arm_sysreg) -> bool

This method tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

This method tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for arm_sysreg

impl Eq for arm_sysreg

impl StructuralPartialEq for arm_sysreg