Enum capstone_sys::arm64_sys_op

source ·

#[repr(u32)]pub enum arm64_sys_op {
Show 105 variants    ARM64_SYS_INVALID = 0,
    ARM64_TLBI_IPAS2E1IS = 1,
    ARM64_TLBI_IPAS2LE1IS = 2,
    ARM64_TLBI_VMALLE1IS = 3,
    ARM64_TLBI_ALLE2IS = 4,
    ARM64_TLBI_ALLE3IS = 5,
    ARM64_TLBI_VAE1IS = 6,
    ARM64_TLBI_VAE2IS = 7,
    ARM64_TLBI_VAE3IS = 8,
    ARM64_TLBI_ASIDE1IS = 9,
    ARM64_TLBI_VAAE1IS = 10,
    ARM64_TLBI_ALLE1IS = 11,
    ARM64_TLBI_VALE1IS = 12,
    ARM64_TLBI_VALE2IS = 13,
    ARM64_TLBI_VALE3IS = 14,
    ARM64_TLBI_VMALLS12E1IS = 15,
    ARM64_TLBI_VAALE1IS = 16,
    ARM64_TLBI_IPAS2E1 = 17,
    ARM64_TLBI_IPAS2LE1 = 18,
    ARM64_TLBI_VMALLE1 = 19,
    ARM64_TLBI_ALLE2 = 20,
    ARM64_TLBI_ALLE3 = 21,
    ARM64_TLBI_VAE1 = 22,
    ARM64_TLBI_VAE2 = 23,
    ARM64_TLBI_VAE3 = 24,
    ARM64_TLBI_ASIDE1 = 25,
    ARM64_TLBI_VAAE1 = 26,
    ARM64_TLBI_ALLE1 = 27,
    ARM64_TLBI_VALE1 = 28,
    ARM64_TLBI_VALE2 = 29,
    ARM64_TLBI_VALE3 = 30,
    ARM64_TLBI_VMALLS12E1 = 31,
    ARM64_TLBI_VAALE1 = 32,
    ARM64_TLBI_VMALLE1OS = 33,
    ARM64_TLBI_VAE1OS = 34,
    ARM64_TLBI_ASIDE1OS = 35,
    ARM64_TLBI_VAAE1OS = 36,
    ARM64_TLBI_VALE1OS = 37,
    ARM64_TLBI_VAALE1OS = 38,
    ARM64_TLBI_IPAS2E1OS = 39,
    ARM64_TLBI_IPAS2LE1OS = 40,
    ARM64_TLBI_VAE2OS = 41,
    ARM64_TLBI_VALE2OS = 42,
    ARM64_TLBI_VMALLS12E1OS = 43,
    ARM64_TLBI_VAE3OS = 44,
    ARM64_TLBI_VALE3OS = 45,
    ARM64_TLBI_ALLE2OS = 46,
    ARM64_TLBI_ALLE1OS = 47,
    ARM64_TLBI_ALLE3OS = 48,
    ARM64_TLBI_RVAE1 = 49,
    ARM64_TLBI_RVAAE1 = 50,
    ARM64_TLBI_RVALE1 = 51,
    ARM64_TLBI_RVAALE1 = 52,
    ARM64_TLBI_RVAE1IS = 53,
    ARM64_TLBI_RVAAE1IS = 54,
    ARM64_TLBI_RVALE1IS = 55,
    ARM64_TLBI_RVAALE1IS = 56,
    ARM64_TLBI_RVAE1OS = 57,
    ARM64_TLBI_RVAAE1OS = 58,
    ARM64_TLBI_RVALE1OS = 59,
    ARM64_TLBI_RVAALE1OS = 60,
    ARM64_TLBI_RIPAS2E1IS = 61,
    ARM64_TLBI_RIPAS2LE1IS = 62,
    ARM64_TLBI_RIPAS2E1 = 63,
    ARM64_TLBI_RIPAS2LE1 = 64,
    ARM64_TLBI_RIPAS2E1OS = 65,
    ARM64_TLBI_RIPAS2LE1OS = 66,
    ARM64_TLBI_RVAE2 = 67,
    ARM64_TLBI_RVALE2 = 68,
    ARM64_TLBI_RVAE2IS = 69,
    ARM64_TLBI_RVALE2IS = 70,
    ARM64_TLBI_RVAE2OS = 71,
    ARM64_TLBI_RVALE2OS = 72,
    ARM64_TLBI_RVAE3 = 73,
    ARM64_TLBI_RVALE3 = 74,
    ARM64_TLBI_RVAE3IS = 75,
    ARM64_TLBI_RVALE3IS = 76,
    ARM64_TLBI_RVAE3OS = 77,
    ARM64_TLBI_RVALE3OS = 78,
    ARM64_AT_S1E1R = 79,
    ARM64_AT_S1E2R = 80,
    ARM64_AT_S1E3R = 81,
    ARM64_AT_S1E1W = 82,
    ARM64_AT_S1E2W = 83,
    ARM64_AT_S1E3W = 84,
    ARM64_AT_S1E0R = 85,
    ARM64_AT_S1E0W = 86,
    ARM64_AT_S12E1R = 87,
    ARM64_AT_S12E1W = 88,
    ARM64_AT_S12E0R = 89,
    ARM64_AT_S12E0W = 90,
    ARM64_AT_S1E1RP = 91,
    ARM64_AT_S1E1WP = 92,
    ARM64_DC_ZVA = 93,
    ARM64_DC_IVAC = 94,
    ARM64_DC_ISW = 95,
    ARM64_DC_CVAC = 96,
    ARM64_DC_CSW = 97,
    ARM64_DC_CVAU = 98,
    ARM64_DC_CIVAC = 99,
    ARM64_DC_CISW = 100,
    ARM64_DC_CVAP = 101,
    ARM64_IC_IALLUIS = 102,
    ARM64_IC_IALLU = 103,
    ARM64_IC_IVAU = 104,
}

Expand description

SYS operands (IC/DC/AC/TLBI)