Enum Arm64SysOp 

#[repr(u32)]
pub enum Arm64SysOp {
    ARM64_SYS_INVALID = 0,
    ARM64_TLBI_ALLE1 = 1,
    ARM64_TLBI_ALLE1IS = 2,
    ARM64_TLBI_ALLE1ISNXS = 3,
    ARM64_TLBI_ALLE1NXS = 4,
    ARM64_TLBI_ALLE1OS = 5,
    ARM64_TLBI_ALLE1OSNXS = 6,
    ARM64_TLBI_ALLE2 = 7,
    ARM64_TLBI_ALLE2IS = 8,
    ARM64_TLBI_ALLE2ISNXS = 9,
    ARM64_TLBI_ALLE2NXS = 10,
    ARM64_TLBI_ALLE2OS = 11,
    ARM64_TLBI_ALLE2OSNXS = 12,
    ARM64_TLBI_ALLE3 = 13,
    ARM64_TLBI_ALLE3IS = 14,
    ARM64_TLBI_ALLE3ISNXS = 15,
    ARM64_TLBI_ALLE3NXS = 16,
    ARM64_TLBI_ALLE3OS = 17,
    ARM64_TLBI_ALLE3OSNXS = 18,
    ARM64_TLBI_ASIDE1 = 19,
    ARM64_TLBI_ASIDE1IS = 20,
    ARM64_TLBI_ASIDE1ISNXS = 21,
    ARM64_TLBI_ASIDE1NXS = 22,
    ARM64_TLBI_ASIDE1OS = 23,
    ARM64_TLBI_ASIDE1OSNXS = 24,
    ARM64_TLBI_IPAS2E1 = 25,
    ARM64_TLBI_IPAS2E1IS = 26,
    ARM64_TLBI_IPAS2E1ISNXS = 27,
    ARM64_TLBI_IPAS2E1NXS = 28,
    ARM64_TLBI_IPAS2E1OS = 29,
    ARM64_TLBI_IPAS2E1OSNXS = 30,
    ARM64_TLBI_IPAS2LE1 = 31,
    ARM64_TLBI_IPAS2LE1IS = 32,
    ARM64_TLBI_IPAS2LE1ISNXS = 33,
    ARM64_TLBI_IPAS2LE1NXS = 34,
    ARM64_TLBI_IPAS2LE1OS = 35,
    ARM64_TLBI_IPAS2LE1OSNXS = 36,
    ARM64_TLBI_PAALL = 37,
    ARM64_TLBI_PAALLNXS = 38,
    ARM64_TLBI_PAALLOS = 39,
    ARM64_TLBI_PAALLOSNXS = 40,
    ARM64_TLBI_RIPAS2E1 = 41,
    ARM64_TLBI_RIPAS2E1IS = 42,
    ARM64_TLBI_RIPAS2E1ISNXS = 43,
    ARM64_TLBI_RIPAS2E1NXS = 44,
    ARM64_TLBI_RIPAS2E1OS = 45,
    ARM64_TLBI_RIPAS2E1OSNXS = 46,
    ARM64_TLBI_RIPAS2LE1 = 47,
    ARM64_TLBI_RIPAS2LE1IS = 48,
    ARM64_TLBI_RIPAS2LE1ISNXS = 49,
    ARM64_TLBI_RIPAS2LE1NXS = 50,
    ARM64_TLBI_RIPAS2LE1OS = 51,
    ARM64_TLBI_RIPAS2LE1OSNXS = 52,
    ARM64_TLBI_RPALOS = 53,
    ARM64_TLBI_RPALOSNXS = 54,
    ARM64_TLBI_RPAOS = 55,
    ARM64_TLBI_RPAOSNXS = 56,
    ARM64_TLBI_RVAAE1 = 57,
    ARM64_TLBI_RVAAE1IS = 58,
    ARM64_TLBI_RVAAE1ISNXS = 59,
    ARM64_TLBI_RVAAE1NXS = 60,
    ARM64_TLBI_RVAAE1OS = 61,
    ARM64_TLBI_RVAAE1OSNXS = 62,
    ARM64_TLBI_RVAALE1 = 63,
    ARM64_TLBI_RVAALE1IS = 64,
    ARM64_TLBI_RVAALE1ISNXS = 65,
    ARM64_TLBI_RVAALE1NXS = 66,
    ARM64_TLBI_RVAALE1OS = 67,
    ARM64_TLBI_RVAALE1OSNXS = 68,
    ARM64_TLBI_RVAE1 = 69,
    ARM64_TLBI_RVAE1IS = 70,
    ARM64_TLBI_RVAE1ISNXS = 71,
    ARM64_TLBI_RVAE1NXS = 72,
    ARM64_TLBI_RVAE1OS = 73,
    ARM64_TLBI_RVAE1OSNXS = 74,
    ARM64_TLBI_RVAE2 = 75,
    ARM64_TLBI_RVAE2IS = 76,
    ARM64_TLBI_RVAE2ISNXS = 77,
    ARM64_TLBI_RVAE2NXS = 78,
    ARM64_TLBI_RVAE2OS = 79,
    ARM64_TLBI_RVAE2OSNXS = 80,
    ARM64_TLBI_RVAE3 = 81,
    ARM64_TLBI_RVAE3IS = 82,
    ARM64_TLBI_RVAE3ISNXS = 83,
    ARM64_TLBI_RVAE3NXS = 84,
    ARM64_TLBI_RVAE3OS = 85,
    ARM64_TLBI_RVAE3OSNXS = 86,
    ARM64_TLBI_RVALE1 = 87,
    ARM64_TLBI_RVALE1IS = 88,
    ARM64_TLBI_RVALE1ISNXS = 89,
    ARM64_TLBI_RVALE1NXS = 90,
    ARM64_TLBI_RVALE1OS = 91,
    ARM64_TLBI_RVALE1OSNXS = 92,
    ARM64_TLBI_RVALE2 = 93,
    ARM64_TLBI_RVALE2IS = 94,
    ARM64_TLBI_RVALE2ISNXS = 95,
    ARM64_TLBI_RVALE2NXS = 96,
    ARM64_TLBI_RVALE2OS = 97,
    ARM64_TLBI_RVALE2OSNXS = 98,
    ARM64_TLBI_RVALE3 = 99,
    ARM64_TLBI_RVALE3IS = 100,
    ARM64_TLBI_RVALE3ISNXS = 101,
    ARM64_TLBI_RVALE3NXS = 102,
    ARM64_TLBI_RVALE3OS = 103,
    ARM64_TLBI_RVALE3OSNXS = 104,
    ARM64_TLBI_VAAE1 = 105,
    ARM64_TLBI_VAAE1IS = 106,
    ARM64_TLBI_VAAE1ISNXS = 107,
    ARM64_TLBI_VAAE1NXS = 108,
    ARM64_TLBI_VAAE1OS = 109,
    ARM64_TLBI_VAAE1OSNXS = 110,
    ARM64_TLBI_VAALE1 = 111,
    ARM64_TLBI_VAALE1IS = 112,
    ARM64_TLBI_VAALE1ISNXS = 113,
    ARM64_TLBI_VAALE1NXS = 114,
    ARM64_TLBI_VAALE1OS = 115,
    ARM64_TLBI_VAALE1OSNXS = 116,
    ARM64_TLBI_VAE1 = 117,
    ARM64_TLBI_VAE1IS = 118,
    ARM64_TLBI_VAE1ISNXS = 119,
    ARM64_TLBI_VAE1NXS = 120,
    ARM64_TLBI_VAE1OS = 121,
    ARM64_TLBI_VAE1OSNXS = 122,
    ARM64_TLBI_VAE2 = 123,
    ARM64_TLBI_VAE2IS = 124,
    ARM64_TLBI_VAE2ISNXS = 125,
    ARM64_TLBI_VAE2NXS = 126,
    ARM64_TLBI_VAE2OS = 127,
    ARM64_TLBI_VAE2OSNXS = 128,
    ARM64_TLBI_VAE3 = 129,
    ARM64_TLBI_VAE3IS = 130,
    ARM64_TLBI_VAE3ISNXS = 131,
    ARM64_TLBI_VAE3NXS = 132,
    ARM64_TLBI_VAE3OS = 133,
    ARM64_TLBI_VAE3OSNXS = 134,
    ARM64_TLBI_VALE1 = 135,
    ARM64_TLBI_VALE1IS = 136,
    ARM64_TLBI_VALE1ISNXS = 137,
    ARM64_TLBI_VALE1NXS = 138,
    ARM64_TLBI_VALE1OS = 139,
    ARM64_TLBI_VALE1OSNXS = 140,
    ARM64_TLBI_VALE2 = 141,
    ARM64_TLBI_VALE2IS = 142,
    ARM64_TLBI_VALE2ISNXS = 143,
    ARM64_TLBI_VALE2NXS = 144,
    ARM64_TLBI_VALE2OS = 145,
    ARM64_TLBI_VALE2OSNXS = 146,
    ARM64_TLBI_VALE3 = 147,
    ARM64_TLBI_VALE3IS = 148,
    ARM64_TLBI_VALE3ISNXS = 149,
    ARM64_TLBI_VALE3NXS = 150,
    ARM64_TLBI_VALE3OS = 151,
    ARM64_TLBI_VALE3OSNXS = 152,
    ARM64_TLBI_VMALLE1 = 153,
    ARM64_TLBI_VMALLE1IS = 154,
    ARM64_TLBI_VMALLE1ISNXS = 155,
    ARM64_TLBI_VMALLE1NXS = 156,
    ARM64_TLBI_VMALLE1OS = 157,
    ARM64_TLBI_VMALLE1OSNXS = 158,
    ARM64_TLBI_VMALLS12E1 = 159,
    ARM64_TLBI_VMALLS12E1IS = 160,
    ARM64_TLBI_VMALLS12E1ISNXS = 161,
    ARM64_TLBI_VMALLS12E1NXS = 162,
    ARM64_TLBI_VMALLS12E1OS = 163,
    ARM64_TLBI_VMALLS12E1OSNXS = 164,
    ARM64_AT_S1E1R = 165,
    ARM64_AT_S1E2R = 166,
    ARM64_AT_S1E3R = 167,
    ARM64_AT_S1E1W = 168,
    ARM64_AT_S1E2W = 169,
    ARM64_AT_S1E3W = 170,
    ARM64_AT_S1E0R = 171,
    ARM64_AT_S1E0W = 172,
    ARM64_AT_S12E1R = 173,
    ARM64_AT_S12E1W = 174,
    ARM64_AT_S12E0R = 175,
    ARM64_AT_S12E0W = 176,
    ARM64_AT_S1E1RP = 177,
    ARM64_AT_S1E1WP = 178,
    ARM64_DC_CGDSW = 179,
    ARM64_DC_CGDVAC = 180,
    ARM64_DC_CGDVADP = 181,
    ARM64_DC_CGDVAP = 182,
    ARM64_DC_CGSW = 183,
    ARM64_DC_CGVAC = 184,
    ARM64_DC_CGVADP = 185,
    ARM64_DC_CGVAP = 186,
    ARM64_DC_CIGDSW = 187,
    ARM64_DC_CIGDVAC = 188,
    ARM64_DC_CIGSW = 189,
    ARM64_DC_CIGVAC = 190,
    ARM64_DC_CISW = 191,
    ARM64_DC_CIVAC = 192,
    ARM64_DC_CSW = 193,
    ARM64_DC_CVAC = 194,
    ARM64_DC_CVADP = 195,
    ARM64_DC_CVAP = 196,
    ARM64_DC_CVAU = 197,
    ARM64_DC_GVA = 198,
    ARM64_DC_GZVA = 199,
    ARM64_DC_IGDSW = 200,
    ARM64_DC_IGDVAC = 201,
    ARM64_DC_IGSW = 202,
    ARM64_DC_IGVAC = 203,
    ARM64_DC_ISW = 204,
    ARM64_DC_IVAC = 205,
    ARM64_DC_ZVA = 206,
    ARM64_IC_IALLUIS = 207,
    ARM64_IC_IALLU = 208,
    ARM64_IC_IVAU = 209,
}

SYS operands (IC/DC/AC/TLBI)

Variants

ARM64_SYS_INVALID = 0

ARM64_TLBI_ALLE1 = 1

TLBI operations

ARM64_TLBI_ALLE1IS = 2

TLBI operations

ARM64_TLBI_ALLE1ISNXS = 3

TLBI operations

ARM64_TLBI_ALLE1NXS = 4

TLBI operations

ARM64_TLBI_ALLE1OS = 5

TLBI operations

ARM64_TLBI_ALLE1OSNXS = 6

TLBI operations

ARM64_TLBI_ALLE2 = 7

TLBI operations

ARM64_TLBI_ALLE2IS = 8

TLBI operations

ARM64_TLBI_ALLE2ISNXS = 9

TLBI operations

ARM64_TLBI_ALLE2NXS = 10

TLBI operations

ARM64_TLBI_ALLE2OS = 11

TLBI operations

ARM64_TLBI_ALLE2OSNXS = 12

TLBI operations

ARM64_TLBI_ALLE3 = 13

TLBI operations

ARM64_TLBI_ALLE3IS = 14

TLBI operations

ARM64_TLBI_ALLE3ISNXS = 15

TLBI operations

ARM64_TLBI_ALLE3NXS = 16

TLBI operations

ARM64_TLBI_ALLE3OS = 17

TLBI operations

ARM64_TLBI_ALLE3OSNXS = 18

TLBI operations

ARM64_TLBI_ASIDE1 = 19

TLBI operations

ARM64_TLBI_ASIDE1IS = 20

TLBI operations

ARM64_TLBI_ASIDE1ISNXS = 21

TLBI operations

ARM64_TLBI_ASIDE1NXS = 22

TLBI operations

ARM64_TLBI_ASIDE1OS = 23

TLBI operations

ARM64_TLBI_ASIDE1OSNXS = 24

TLBI operations

ARM64_TLBI_IPAS2E1 = 25

TLBI operations

ARM64_TLBI_IPAS2E1IS = 26

TLBI operations

ARM64_TLBI_IPAS2E1ISNXS = 27

TLBI operations

ARM64_TLBI_IPAS2E1NXS = 28

TLBI operations

ARM64_TLBI_IPAS2E1OS = 29

TLBI operations

ARM64_TLBI_IPAS2E1OSNXS = 30

TLBI operations

ARM64_TLBI_IPAS2LE1 = 31

TLBI operations

ARM64_TLBI_IPAS2LE1IS = 32

TLBI operations

ARM64_TLBI_IPAS2LE1ISNXS = 33

TLBI operations

ARM64_TLBI_IPAS2LE1NXS = 34

TLBI operations

ARM64_TLBI_IPAS2LE1OS = 35

TLBI operations

ARM64_TLBI_IPAS2LE1OSNXS = 36

TLBI operations

ARM64_TLBI_PAALL = 37

TLBI operations

ARM64_TLBI_PAALLNXS = 38

TLBI operations

ARM64_TLBI_PAALLOS = 39

TLBI operations

ARM64_TLBI_PAALLOSNXS = 40

TLBI operations

ARM64_TLBI_RIPAS2E1 = 41

TLBI operations

ARM64_TLBI_RIPAS2E1IS = 42

TLBI operations

ARM64_TLBI_RIPAS2E1ISNXS = 43

TLBI operations

ARM64_TLBI_RIPAS2E1NXS = 44

TLBI operations

ARM64_TLBI_RIPAS2E1OS = 45

TLBI operations

ARM64_TLBI_RIPAS2E1OSNXS = 46

TLBI operations

ARM64_TLBI_RIPAS2LE1 = 47

TLBI operations

ARM64_TLBI_RIPAS2LE1IS = 48

TLBI operations

ARM64_TLBI_RIPAS2LE1ISNXS = 49

TLBI operations

ARM64_TLBI_RIPAS2LE1NXS = 50

TLBI operations

ARM64_TLBI_RIPAS2LE1OS = 51

TLBI operations

ARM64_TLBI_RIPAS2LE1OSNXS = 52

TLBI operations

ARM64_TLBI_RPALOS = 53

TLBI operations

ARM64_TLBI_RPALOSNXS = 54

TLBI operations

ARM64_TLBI_RPAOS = 55

TLBI operations

ARM64_TLBI_RPAOSNXS = 56

TLBI operations

ARM64_TLBI_RVAAE1 = 57

TLBI operations

ARM64_TLBI_RVAAE1IS = 58

TLBI operations

ARM64_TLBI_RVAAE1ISNXS = 59

TLBI operations

ARM64_TLBI_RVAAE1NXS = 60

TLBI operations

ARM64_TLBI_RVAAE1OS = 61

TLBI operations

ARM64_TLBI_RVAAE1OSNXS = 62

TLBI operations

ARM64_TLBI_RVAALE1 = 63

TLBI operations

ARM64_TLBI_RVAALE1IS = 64

TLBI operations

ARM64_TLBI_RVAALE1ISNXS = 65

TLBI operations

ARM64_TLBI_RVAALE1NXS = 66

TLBI operations

ARM64_TLBI_RVAALE1OS = 67

TLBI operations

ARM64_TLBI_RVAALE1OSNXS = 68

TLBI operations

ARM64_TLBI_RVAE1 = 69

TLBI operations

ARM64_TLBI_RVAE1IS = 70

TLBI operations

ARM64_TLBI_RVAE1ISNXS = 71

TLBI operations

ARM64_TLBI_RVAE1NXS = 72

TLBI operations

ARM64_TLBI_RVAE1OS = 73

TLBI operations

ARM64_TLBI_RVAE1OSNXS = 74

TLBI operations

ARM64_TLBI_RVAE2 = 75

TLBI operations

ARM64_TLBI_RVAE2IS = 76

TLBI operations

ARM64_TLBI_RVAE2ISNXS = 77

TLBI operations

ARM64_TLBI_RVAE2NXS = 78

TLBI operations

ARM64_TLBI_RVAE2OS = 79

TLBI operations

ARM64_TLBI_RVAE2OSNXS = 80

TLBI operations

ARM64_TLBI_RVAE3 = 81

TLBI operations

ARM64_TLBI_RVAE3IS = 82

TLBI operations

ARM64_TLBI_RVAE3ISNXS = 83

TLBI operations

ARM64_TLBI_RVAE3NXS = 84

TLBI operations

ARM64_TLBI_RVAE3OS = 85

TLBI operations

ARM64_TLBI_RVAE3OSNXS = 86

TLBI operations

ARM64_TLBI_RVALE1 = 87

TLBI operations

ARM64_TLBI_RVALE1IS = 88

TLBI operations

ARM64_TLBI_RVALE1ISNXS = 89

TLBI operations

ARM64_TLBI_RVALE1NXS = 90

TLBI operations

ARM64_TLBI_RVALE1OS = 91

TLBI operations

ARM64_TLBI_RVALE1OSNXS = 92

TLBI operations

ARM64_TLBI_RVALE2 = 93

TLBI operations

ARM64_TLBI_RVALE2IS = 94

TLBI operations

ARM64_TLBI_RVALE2ISNXS = 95

TLBI operations

ARM64_TLBI_RVALE2NXS = 96

TLBI operations

ARM64_TLBI_RVALE2OS = 97

TLBI operations

ARM64_TLBI_RVALE2OSNXS = 98

TLBI operations

ARM64_TLBI_RVALE3 = 99

TLBI operations

ARM64_TLBI_RVALE3IS = 100

TLBI operations

ARM64_TLBI_RVALE3ISNXS = 101

TLBI operations

ARM64_TLBI_RVALE3NXS = 102

TLBI operations

ARM64_TLBI_RVALE3OS = 103

TLBI operations

ARM64_TLBI_RVALE3OSNXS = 104

TLBI operations

ARM64_TLBI_VAAE1 = 105

TLBI operations

ARM64_TLBI_VAAE1IS = 106

TLBI operations

ARM64_TLBI_VAAE1ISNXS = 107

TLBI operations

ARM64_TLBI_VAAE1NXS = 108

TLBI operations

ARM64_TLBI_VAAE1OS = 109

TLBI operations

ARM64_TLBI_VAAE1OSNXS = 110

TLBI operations

ARM64_TLBI_VAALE1 = 111

TLBI operations

ARM64_TLBI_VAALE1IS = 112

TLBI operations

ARM64_TLBI_VAALE1ISNXS = 113

TLBI operations

ARM64_TLBI_VAALE1NXS = 114

TLBI operations

ARM64_TLBI_VAALE1OS = 115

TLBI operations

ARM64_TLBI_VAALE1OSNXS = 116

TLBI operations

ARM64_TLBI_VAE1 = 117

TLBI operations

ARM64_TLBI_VAE1IS = 118

TLBI operations

ARM64_TLBI_VAE1ISNXS = 119

TLBI operations

ARM64_TLBI_VAE1NXS = 120

TLBI operations

ARM64_TLBI_VAE1OS = 121

TLBI operations

ARM64_TLBI_VAE1OSNXS = 122

TLBI operations

ARM64_TLBI_VAE2 = 123

TLBI operations

ARM64_TLBI_VAE2IS = 124

TLBI operations

ARM64_TLBI_VAE2ISNXS = 125

TLBI operations

ARM64_TLBI_VAE2NXS = 126

TLBI operations

ARM64_TLBI_VAE2OS = 127

TLBI operations

ARM64_TLBI_VAE2OSNXS = 128

TLBI operations

ARM64_TLBI_VAE3 = 129

TLBI operations

ARM64_TLBI_VAE3IS = 130

TLBI operations

ARM64_TLBI_VAE3ISNXS = 131

TLBI operations

ARM64_TLBI_VAE3NXS = 132

TLBI operations

ARM64_TLBI_VAE3OS = 133

TLBI operations

ARM64_TLBI_VAE3OSNXS = 134

TLBI operations

ARM64_TLBI_VALE1 = 135

TLBI operations

ARM64_TLBI_VALE1IS = 136

TLBI operations

ARM64_TLBI_VALE1ISNXS = 137

TLBI operations

ARM64_TLBI_VALE1NXS = 138

TLBI operations

ARM64_TLBI_VALE1OS = 139

TLBI operations

ARM64_TLBI_VALE1OSNXS = 140

TLBI operations

ARM64_TLBI_VALE2 = 141

TLBI operations

ARM64_TLBI_VALE2IS = 142

TLBI operations

ARM64_TLBI_VALE2ISNXS = 143

TLBI operations

ARM64_TLBI_VALE2NXS = 144

TLBI operations

ARM64_TLBI_VALE2OS = 145

TLBI operations

ARM64_TLBI_VALE2OSNXS = 146

TLBI operations

ARM64_TLBI_VALE3 = 147

TLBI operations

ARM64_TLBI_VALE3IS = 148

TLBI operations

ARM64_TLBI_VALE3ISNXS = 149

TLBI operations

ARM64_TLBI_VALE3NXS = 150

TLBI operations

ARM64_TLBI_VALE3OS = 151

TLBI operations

ARM64_TLBI_VALE3OSNXS = 152

TLBI operations

ARM64_TLBI_VMALLE1 = 153

TLBI operations

ARM64_TLBI_VMALLE1IS = 154

TLBI operations

ARM64_TLBI_VMALLE1ISNXS = 155

TLBI operations

ARM64_TLBI_VMALLE1NXS = 156

TLBI operations

ARM64_TLBI_VMALLE1OS = 157

TLBI operations

ARM64_TLBI_VMALLE1OSNXS = 158

TLBI operations

ARM64_TLBI_VMALLS12E1 = 159

TLBI operations

ARM64_TLBI_VMALLS12E1IS = 160

TLBI operations

ARM64_TLBI_VMALLS12E1ISNXS = 161

TLBI operations

ARM64_TLBI_VMALLS12E1NXS = 162

TLBI operations

ARM64_TLBI_VMALLS12E1OS = 163

TLBI operations

ARM64_TLBI_VMALLS12E1OSNXS = 164

TLBI operations

ARM64_AT_S1E1R = 165

AT operations

ARM64_AT_S1E2R = 166

AT operations

ARM64_AT_S1E3R = 167

AT operations

ARM64_AT_S1E1W = 168

AT operations

ARM64_AT_S1E2W = 169

AT operations

ARM64_AT_S1E3W = 170

AT operations

ARM64_AT_S1E0R = 171

AT operations

ARM64_AT_S1E0W = 172

AT operations

ARM64_AT_S12E1R = 173

AT operations

ARM64_AT_S12E1W = 174

AT operations

ARM64_AT_S12E0R = 175

AT operations

ARM64_AT_S12E0W = 176

AT operations

ARM64_AT_S1E1RP = 177

AT operations

ARM64_AT_S1E1WP = 178

AT operations

ARM64_DC_CGDSW = 179

DC operations

ARM64_DC_CGDVAC = 180

DC operations

ARM64_DC_CGDVADP = 181

DC operations

ARM64_DC_CGDVAP = 182

DC operations

ARM64_DC_CGSW = 183

DC operations

ARM64_DC_CGVAC = 184

DC operations

ARM64_DC_CGVADP = 185

DC operations

ARM64_DC_CGVAP = 186

DC operations

ARM64_DC_CIGDSW = 187

DC operations

ARM64_DC_CIGDVAC = 188

DC operations

ARM64_DC_CIGSW = 189

DC operations

ARM64_DC_CIGVAC = 190

DC operations

ARM64_DC_CISW = 191

DC operations

ARM64_DC_CIVAC = 192

DC operations

ARM64_DC_CSW = 193

DC operations

ARM64_DC_CVAC = 194

DC operations

ARM64_DC_CVADP = 195

DC operations

ARM64_DC_CVAP = 196

DC operations

ARM64_DC_CVAU = 197

DC operations

ARM64_DC_GVA = 198

DC operations

ARM64_DC_GZVA = 199

DC operations

ARM64_DC_IGDSW = 200

DC operations

ARM64_DC_IGDVAC = 201

DC operations

ARM64_DC_IGSW = 202

DC operations

ARM64_DC_IGVAC = 203

DC operations

ARM64_DC_ISW = 204

DC operations

ARM64_DC_IVAC = 205

DC operations

ARM64_DC_ZVA = 206

DC operations

ARM64_IC_IALLUIS = 207

IC operations

ARM64_IC_IALLU = 208

IC operations

ARM64_IC_IVAU = 209

IC operations

Trait Implementations

impl Clone for arm64_sys_op

fn clone(&self) -> arm64_sys_op

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for arm64_sys_op

fn fmt(&self, f: &mut Formatter<'_>) -> Result<(), Error>

Formats the value using the given formatter.

impl Hash for arm64_sys_op

fn hash<__H>(&self, state: &mut __H)

where __H: Hasher,

Feeds this value into the given Hasher.

fn hash_slice<H>(data: &[Self], state: &mut H)

where H: Hasher, Self: Sized,

Feeds a slice of this type into the given Hasher.

impl PartialEq for arm64_sys_op

fn eq(&self, other: &arm64_sys_op) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for arm64_sys_op

impl Eq for arm64_sys_op

impl StructuralPartialEq for arm64_sys_op