#[repr(u64)]pub enum Core {
Show 24 variants
LDM = 0,
LDD = 1,
LDI = 2,
LDX = 3,
LDR = 4,
MOV = 5,
STO = 6,
CMP = 7,
JPE = 8,
JPN = 9,
JMP = 10,
CMI = 11,
IN = 12,
OUT = 13,
END = 14,
INC = 15,
DEC = 16,
ADD = 17,
SUB = 18,
AND = 19,
OR = 20,
XOR = 21,
LSL = 22,
LSR = 23,
}
Expand description
The core instruction set
-
Memory and register manipulation:
LDM
,LDD
,LDI
,LDX
,LDR
,MOV
,STO
-
Comparison:
CMP
,JPE
,JPN
,JMP
,CMI
-
Basic I/O:
IN
,OUT
,END
-
Arithmetic:
INC
,DEC
,ADD
,SUB
-
Bit manipulation:
AND
,OR
,XOR
,LSL
,LSR
Variants§
LDM = 0
LDD = 1
LDI = 2
LDX = 3
LDR = 4
MOV = 5
STO = 6
CMP = 7
JPE = 8
JPN = 9
JMP = 10
CMI = 11
IN = 12
OUT = 13
END = 14
INC = 15
DEC = 16
ADD = 17
SUB = 18
AND = 19
OR = 20
XOR = 21
LSL = 22
LSR = 23
Trait Implementations§
Source§impl Display for Core
The core instruction set
impl Display for Core
The core instruction set
-
Memory and register manipulation:
LDM
,LDD
,LDI
,LDX
,LDR
,MOV
,STO
-
Comparison:
CMP
,JPE
,JPN
,JMP
,CMI
-
Basic I/O:
IN
,OUT
,END
-
Arithmetic:
INC
,DEC
,ADD
,SUB
-
Bit manipulation:
AND
,OR
,XOR
,LSL
,LSR
Source§impl FromStr for Core
The core instruction set
impl FromStr for Core
The core instruction set
-
Memory and register manipulation:
LDM
,LDD
,LDI
,LDX
,LDR
,MOV
,STO
-
Comparison:
CMP
,JPE
,JPN
,JMP
,CMI
-
Basic I/O:
IN
,OUT
,END
-
Arithmetic:
INC
,DEC
,ADD
,SUB
-
Bit manipulation:
AND
,OR
,XOR
,LSL
,LSR
Source§impl InstSet for Core
The core instruction set
impl InstSet for Core
The core instruction set
-
Memory and register manipulation:
LDM
,LDD
,LDI
,LDX
,LDR
,MOV
,STO
-
Comparison:
CMP
,JPE
,JPN
,JMP
,CMI
-
Basic I/O:
IN
,OUT
,END
-
Arithmetic:
INC
,DEC
,ADD
,SUB
-
Bit manipulation:
AND
,OR
,XOR
,LSL
,LSR