RegisterBlock

bl808_pac::emac

Struct RegisterBlock 

Source 
#[repr(C)]
pub struct RegisterBlock {
Show 19 fields
    pub mode: MODE,
    pub interrupt_source: INTERRUPT_SOURCE,
    pub interrupt_mask: INTERRUPT_MASK,
    pub backed_gap: BACKED_GAP,
    pub non_backed_gap_1: NON_BACKED_GAP_1,
    pub non_backed_gap_2: NON_BACKED_GAP_2,
    pub frame_length: FRAME_LENGTH,
    pub collision: COLLISION,
    pub transmit_buffer: TRANSMIT_BUFFER,
    pub flow_control: FLOW_CONTROL,
    pub mii_mode: MII_MODE,
    pub mii_command: MII_COMMAND,
    pub mii_address: MII_ADDRESS,
    pub control_write: CONTROL_WRITE,
    pub control_read: CONTROL_READ,
    pub mii_state: MII_STATE,
    pub mac_address: [MAC_ADDRESS; 2],
    pub hash: [HASH; 2],
    pub transmit_control: TRANSMIT_CONTROL,

}
Expand description

Register block

Fields§

§mode: MODE

0x00 - Interface enables and configurations

§interrupt_source: INTERRUPT_SOURCE

0x04 - Interrupt source register

§interrupt_mask: INTERRUPT_MASK

0x08 - Interrupt mask register

§backed_gap: BACKED_GAP

0x0c - Back-to-back inter-packet gap register

§non_backed_gap_1: NON_BACKED_GAP_1

0x10 - Non back-to-back inter-packet gap register 1

§non_backed_gap_2: NON_BACKED_GAP_2

0x14 - Non back-to-back inter-packet gap register 2

§frame_length: FRAME_LENGTH

0x18 - Minimum and maximum ethernet frame length

§collision: COLLISION

0x1c - Collision time window and maximum retries

§transmit_buffer: TRANSMIT_BUFFER

0x20 - Transmit buffer descriptor

§flow_control: FLOW_CONTROL

0x24 - Control frame function register

§mii_mode: MII_MODE

0x28 - MII clock divider and premable enable

§mii_command: MII_COMMAND

0x2c - MII control data, read and scan state

§mii_address: MII_ADDRESS

0x30 - Physical layer bus address

§control_write: CONTROL_WRITE

0x34 - Write data to MII physcial layer

§control_read: CONTROL_READ

0x38 - Read data from MII physcial layer

§mii_state: MII_STATE

0x3c - MII bus and link layer state

§mac_address: [MAC_ADDRESS; 2]

0x40..0x48 - Media Access Control address

§hash: [HASH; 2]

0x48..0x50 - Hash register

§transmit_control: TRANSMIT_CONTROL

0x50 - Transmit control register

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